Re: [PATCH 08/10] target/arm: Implement FEAT_PMUv3p5 cycle counter disable bits

2022-08-22 Thread Peter Maydell
On Sat, 20 Aug 2022 at 18:33, Richard Henderson wrote: > > On 8/11/22 10:16, Peter Maydell wrote: > > FEAT_PMUv3p5 introduces new bits MDCR_EL2.HCCD and MDCR_EL3.SCCD, > > which disable the cycle counter from counting at EL2 and EL3. > > Add the code to support these bits. > > While HCCD is v3p5,

Re: [PATCH 08/10] target/arm: Implement FEAT_PMUv3p5 cycle counter disable bits

2022-08-20 Thread Richard Henderson
On 8/11/22 10:16, Peter Maydell wrote: FEAT_PMUv3p5 introduces new bits MDCR_EL2.HCCD and MDCR_EL3.SCCD, which disable the cycle counter from counting at EL2 and EL3. Add the code to support these bits. While HCCD is v3p5, it seems MCCD (typo above) is v3p7. +if (counter == 31) { +

[PATCH 08/10] target/arm: Implement FEAT_PMUv3p5 cycle counter disable bits

2022-08-11 Thread Peter Maydell
FEAT_PMUv3p5 introduces new bits MDCR_EL2.HCCD and MDCR_EL3.SCCD, which disable the cycle counter from counting at EL2 and EL3. Add the code to support these bits. Signed-off-by: Peter Maydell --- target/arm/cpu.h| 20 target/arm/helper.c | 20 2 fil