On Sat, 20 Aug 2022 at 18:33, Richard Henderson <richard.hender...@linaro.org> wrote: > > On 8/11/22 10:16, Peter Maydell wrote: > > FEAT_PMUv3p5 introduces new bits MDCR_EL2.HCCD and MDCR_EL3.SCCD, > > which disable the cycle counter from counting at EL2 and EL3. > > Add the code to support these bits. > > While HCCD is v3p5, it seems MCCD (typo above) is v3p7.
DDI0487H.a page D13-6158 says # SCCD, bit [23] # When FEAT_PMUv3p5 is implemented: # [...] MDCR_EL3.MCCD is a different bit, bit 34, which is indeed v3p7. It looks like I've got confused between the two and implemented the wrong thing. MDCR_EL3.SCCD: bit 23: v3p5: don't count in Secure state MDCR_EL3.MCCD: bit 34: v3p7: don't count in EL3 and for completeness MDCR_EL2.HCCD: bit 23: v3p5: don't count in EL2 I'll redo the patch to implement HCCD and SCCD. (We can leave MCCD until we get to the PMUv3p7 feature.) thanks -- PMM
