On Tue, 3 Dec 2019 at 22:53, Richard Henderson
wrote:
>
> For aarch64, there's a dedicated msr (imm, reg) insn.
> For aarch32, this is done via msr to cpsr; and writes
> from el0 are ignored.
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/cpu.h | 2 ++
> target/arm/helper.c
For aarch64, there's a dedicated msr (imm, reg) insn.
For aarch32, this is done via msr to cpsr; and writes
from el0 are ignored.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 2 ++
target/arm/helper.c| 22 ++
target/arm/translate-a64.c | 14 +
