On Tue, 3 Dec 2019 at 22:53, Richard Henderson
<richard.hender...@linaro.org> wrote:
>
> For aarch64, there's a dedicated msr (imm, reg) insn.
> For aarch32, this is done via msr to cpsr; and writes
> from el0 are ignored.
>
> Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
> ---
> target/arm/cpu.h | 2 ++
> target/arm/helper.c | 22 ++++++++++++++++++++++
> target/arm/translate-a64.c | 14 ++++++++++++++
> target/arm/translate.c | 4 ++++
> 4 files changed, 42 insertions(+)
>
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index 170dd5b124..f0e61bf34f 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -1159,6 +1159,7 @@ void pmu_init(ARMCPU *cpu);
> * We will need to move AArch32 SS somewhere else at that point.
> */
> #define CPSR_RESERVED (1U << 21)
> +#define CPSR_PAN (1U << 22)
> #define CPSR_J (1U << 24)
> #define CPSR_IT_0_1 (3U << 25)
> #define CPSR_Q (1U << 27)
> @@ -1225,6 +1226,7 @@ void pmu_init(ARMCPU *cpu);
> #define PSTATE_BTYPE (3U << 10)
> #define PSTATE_IL (1U << 20)
> #define PSTATE_SS (1U << 21)
> +#define PSTATE_PAN (1U << 22)
> #define PSTATE_V (1U << 28)
> #define PSTATE_C (1U << 29)
> #define PSTATE_Z (1U << 30)
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index 4e3fe00316..512be5c644 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -4112,6 +4112,17 @@ static void aa64_daif_write(CPUARMState *env, const
> ARMCPRegInfo *ri,
> env->daif = value & PSTATE_DAIF;
> }
>
> +static uint64_t aa64_pan_read(CPUARMState *env, const ARMCPRegInfo *ri)
> +{
> + return env->pstate & PSTATE_PAN;
> +}
> +
> +static void aa64_pan_write(CPUARMState *env, const ARMCPRegInfo *ri,
> + uint64_t value)
> +{
> + env->pstate = (env->pstate & ~PSTATE_PAN) | (value & PSTATE_PAN);
> +}
> +
> static CPAccessResult aa64_cacheop_access(CPUARMState *env,
> const ARMCPRegInfo *ri,
> bool isread)
> @@ -7405,6 +7416,17 @@ void register_cp_regs_for_features(ARMCPU *cpu)
> define_arm_cp_regs(cpu, lor_reginfo);
> }
>
> + if (cpu_isar_feature(aa64_pan, cpu)) {
> + static const ARMCPRegInfo pan_reginfo[] = {
> + { .name = "PAN", .state = ARM_CP_STATE_AA64,
> + .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 3,
> + .type = ARM_CP_NO_RAW, .access = PL1_RW,
> + .readfn = aa64_pan_read, .writefn = aa64_pan_write, },
> + REGINFO_SENTINEL
> + };
Same remarks about regdef as for UAO.
> + define_arm_cp_regs(cpu, pan_reginfo);
> + }
> +
> if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu))
> {
> static const ARMCPRegInfo vhe_reginfo[] = {
> { .name = "CONTEXTIDR_EL2", .state = ARM_CP_STATE_AA64,
> diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
> index b5c7bc2d76..7f5a68106b 100644
> --- a/target/arm/translate-a64.c
> +++ b/target/arm/translate-a64.c
> @@ -1601,6 +1601,20 @@ static void handle_msr_i(DisasContext *s, uint32_t
> insn,
> s->base.is_jmp = DISAS_NEXT;
> break;
>
> + case 0x04: /* PAN */
> + if (!dc_isar_feature(aa64_pan, s) || s->current_el == 0) {
> + goto do_unallocated;
> + }
> + if (crm & 1) {
> + set_pstate_bits(PSTATE_PAN);
> + } else {
> + clear_pstate_bits(PSTATE_PAN);
> + }
> + t1 = tcg_const_i32(s->current_el);
> + gen_helper_rebuild_hflags_a64(cpu_env, t1);
> + tcg_temp_free_i32(t1);
> + break;
and same question about whether we need to break the TB here.
> +
> case 0x05: /* SPSel */
> if (s->current_el == 0) {
> goto do_unallocated;
> diff --git a/target/arm/translate.c b/target/arm/translate.c
> index 47a374b53d..98e6072dd4 100644
> --- a/target/arm/translate.c
> +++ b/target/arm/translate.c
> @@ -2785,6 +2785,10 @@ static int gen_set_psr(DisasContext *s, uint32_t mask,
> int spsr, TCGv_i32 t0)
> tcg_gen_or_i32(tmp, tmp, t0);
> store_cpu_field(tmp, spsr);
> } else {
> + /* Data writes to CPSR.PAN using an MSR insn at EL0 are ignored. */
> + if (IS_USER(s)) {
> + mask &= ~CPSR_PAN;
> + }
I think we should also ignore the write if the PAN feature
isn't present (see remark on earlier patch).
> gen_set_cpsr(t0, mask);
> }
> tcg_temp_free_i32(t0);
> --
> 2.17.1
thanks
-- PMM
