Re: [PATCH 04/11 v2] target/riscv: Update CSR xie in CLIC mode

2024-09-05 Thread Alistair Francis
On Fri, Sep 6, 2024 at 12:58 PM Alistair Francis wrote: > > On Tue, Aug 20, 2024 at 2:15 AM Ian Brockbank > wrote: > > > > From: Ian Brockbank > > > > The xie CSR appears hardwired to zero in CLIC mode, replaced by separate > > memory-mapped interrupt enables (clicintie[i]). Writes to xie will

Re: [PATCH 04/11 v2] target/riscv: Update CSR xie in CLIC mode

2024-09-05 Thread Alistair Francis
On Tue, Aug 20, 2024 at 2:15 AM Ian Brockbank wrote: > > From: Ian Brockbank > > The xie CSR appears hardwired to zero in CLIC mode, replaced by separate > memory-mapped interrupt enables (clicintie[i]). Writes to xie will be > ignored and will not trap (i.e., no access faults). > > Signed-off-by

[PATCH 04/11 v2] target/riscv: Update CSR xie in CLIC mode

2024-08-19 Thread Ian Brockbank
From: Ian Brockbank The xie CSR appears hardwired to zero in CLIC mode, replaced by separate memory-mapped interrupt enables (clicintie[i]). Writes to xie will be ignored and will not trap (i.e., no access faults). Signed-off-by: LIU Zhiwei Signed-off-by: Ian Brockbank --- target/riscv/csr.c