On Fri, Sep 6, 2024 at 12:58 PM Alistair Francis <alistai...@gmail.com> wrote: > > On Tue, Aug 20, 2024 at 2:15 AM Ian Brockbank <ian.brockb...@cirrus.com> > wrote: > > > > From: Ian Brockbank <ian.brockb...@cirrus.com> > > > > The xie CSR appears hardwired to zero in CLIC mode, replaced by separate > > memory-mapped interrupt enables (clicintie[i]). Writes to xie will be > > ignored and will not trap (i.e., no access faults). > > > > Signed-off-by: LIU Zhiwei <zhiwei_...@c-sky.com> > > Signed-off-by: Ian Brockbank <ian.brockb...@cirrus.com> > > --- > > target/riscv/csr.c | 34 ++++++++++++++++++++++------------ > > 1 file changed, 22 insertions(+), 12 deletions(-) > > > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > > index 9c824c0d8f..a5978e0929 100644 > > --- a/target/riscv/csr.c > > +++ b/target/riscv/csr.c > > @@ -30,6 +30,10 @@ > > #include "qemu/guest-random.h" > > #include "qapi/error.h" > > > > +#if !defined(CONFIG_USER_ONLY) > > +#include "hw/intc/riscv_clic.h" > > +#endif > > This doesn't seem like the way to go
Urgh! Ok, it's trickier than that. I think ideally we don't want to pull in a bunch of CLIC stuff, just the bare minimum. It's probably better to implement the CLIC functions for CSR access in the target/riscv directory instead of in hw/intc Also, to make it easier to review it would be great to add the functions when they are used. Then patch 3 will be smaller and the other patches easier to see what is being added Alistair
