On Tue May 16, 2023 at 11:54 AM AEST, Narayana Murty N wrote:
>
> On 5/15/23 12:02, Nicholas Piggin wrote:
> > On Sat Apr 29, 2023 at 12:30 AM AEST, Fabiano Rosas wrote:
> Could you describe in more detail what is your setup? Specifically
> whether both guests are running TCG or KVM (info
On 5/15/23 12:02, Nicholas Piggin wrote:
On Sat Apr 29, 2023 at 12:30 AM AEST, Fabiano Rosas wrote:
Vaibhav Jain writes:
Hi Fabiano,
Thanks for looking into this patch and apologies for the delayed reponse.
Fabiano Rosas writes:
Narayana Murty N writes:
On PPC64 the HILE(Hypervisor In
On Sat Apr 29, 2023 at 12:30 AM AEST, Fabiano Rosas wrote:
> Vaibhav Jain writes:
>
> > Hi Fabiano,
> >
> > Thanks for looking into this patch and apologies for the delayed reponse.
> > Fabiano Rosas writes:
> >
> >> Narayana Murty N writes:
> >>
> >>> On PPC64 the HILE(Hypervisor Interrupt Litt
On 4/28/23 20:00, Fabiano Rosas wrote:
Vaibhav Jain writes:
Hi Fabiano,
Thanks for looking into this patch and apologies for the delayed reponse.
Fabiano Rosas writes:
Narayana Murty N writes:
On PPC64 the HILE(Hypervisor Interrupt Little Endian) bit in HID-0
register needs to be initia
Vaibhav Jain writes:
> Hi Fabiano,
>
> Thanks for looking into this patch and apologies for the delayed reponse.
> Fabiano Rosas writes:
>
>> Narayana Murty N writes:
>>
>>> On PPC64 the HILE(Hypervisor Interrupt Little Endian) bit in HID-0
>>> register needs to be initialized as per isa 3.0b[1
Hi Fabiano,
Thanks for looking into this patch and apologies for the delayed reponse.
Fabiano Rosas writes:
> Narayana Murty N writes:
>
>> On PPC64 the HILE(Hypervisor Interrupt Little Endian) bit in HID-0
>> register needs to be initialized as per isa 3.0b[1] section
>> 2.10. This bit gets
Narayana Murty N writes:
> On PPC64 the HILE(Hypervisor Interrupt Little Endian) bit in HID-0
> register needs to be initialized as per isa 3.0b[1] section
> 2.10. This bit gets copied to the MSR_LE when handling interrupts that
> are handled in HV mode to establish the Endianess mode of the inte
On PPC64 the HILE(Hypervisor Interrupt Little Endian) bit in HID-0
register needs to be initialized as per isa 3.0b[1] section
2.10. This bit gets copied to the MSR_LE when handling interrupts that
are handled in HV mode to establish the Endianess mode of the interrupt
handler.
Qemu's ppc_interrup
Hi Narayana,
Minor comments inline below.
On 4/20/23 20:20, Narayana Murty N wrote:
On PPC64 the HILE(Hypervisor Interrupt Little Endian) bit in HID-0
register needs to be initialized as per isa 3.0b[1] section
2.10. This bit gets copied to the MSR_LE when handling interrupts that
are handled i
