Narayana Murty N <nnmli...@linux.ibm.com> writes: > On PPC64 the HILE(Hypervisor Interrupt Little Endian) bit in HID-0 > register needs to be initialized as per isa 3.0b[1] section > 2.10. This bit gets copied to the MSR_LE when handling interrupts that > are handled in HV mode to establish the Endianess mode of the interrupt > handler. > > Qemu's ppc_interrupts_little_endian() depends on HILE to determine Host > endianness which is then used to determine the endianess of the guest dump. >
Not quite. We use the interrupt endianness as a proxy to guest endianness to avoid reading MSR_LE at an inopportune moment when the guest is switching endianness. This is not dependent on host endianness. The HILE check is used when taking a memory dump of a HV-capable machine such as the emulated powernv. I think the actual issue might be that we're calling ppc_interrupts_little_endian with hv=true for the dump. > Currently the HILE bit is never set in the HID0 register even if the > qemu is running in Little-Endian mode. This causes the guest dumps to be > always taken in Big-Endian byte ordering. A guest memory dump of a > Little-Endian guest running on Little-Endian qemu guest fails with the > crash tool as illustrated below: > Could you describe in more detail what is your setup? Specifically whether both guests are running TCG or KVM (info kvm) and the state of the nested-hv capability in QEMU command line.
