Re: [PATCH] target/riscv: Fix definition of MSTATUS_TW and MSTATUS_TSR

On Mon, Nov 30, 2020 at 9:07 AM Alex Richardson wrote: > > The TW and TSR fields should be bits 21 and 22 and not 30/29. > This was found while comparing QEMU behaviour against the sail formal > model (https://github.com/rems-project/sail-riscv/). > > Signed-off-by: Alex Richardson Reviewed-by:

[PATCH] target/riscv: Fix definition of MSTATUS_TW and MSTATUS_TSR

The TW and TSR fields should be bits 21 and 22 and not 30/29. This was found while comparing QEMU behaviour against the sail formal model (https://github.com/rems-project/sail-riscv/). Signed-off-by: Alex Richardson --- target/riscv/cpu_bits.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletio