On Mon, Nov 30, 2020 at 9:07 AM Alex Richardson <alexander.richard...@cl.cam.ac.uk> wrote: > > The TW and TSR fields should be bits 21 and 22 and not 30/29. > This was found while comparing QEMU behaviour against the sail formal > model (https://github.com/rems-project/sail-riscv/). > > Signed-off-by: Alex Richardson <alexander.richard...@cl.cam.ac.uk>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> Alistair > --- > target/riscv/cpu_bits.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h > index 24b24c69c5..92147332c6 100644 > --- a/target/riscv/cpu_bits.h > +++ b/target/riscv/cpu_bits.h > @@ -379,8 +379,8 @@ > #define MSTATUS_MXR 0x00080000 > #define MSTATUS_VM 0x1F000000 /* until: priv-1.9.1 */ > #define MSTATUS_TVM 0x00100000 /* since: priv-1.10 */ > -#define MSTATUS_TW 0x20000000 /* since: priv-1.10 */ > -#define MSTATUS_TSR 0x40000000 /* since: priv-1.10 */ > +#define MSTATUS_TW 0x00200000 /* since: priv-1.10 */ > +#define MSTATUS_TSR 0x00400000 /* since: priv-1.10 */ > #define MSTATUS_GVA 0x4000000000ULL > #define MSTATUS_MPV 0x8000000000ULL > > -- > 2.29.2 > >
