Got it.
As the first step, I just summit a new patch:
[PATCH] riscv: Add helper to make NaN-boxing for FP register
I'd like to carry out other fixes after this patch is reviewed.
Richard Henderson 于2020年1月24日周五 上午2:53写道：
>
> On 1/22/20 6:05 PM, Ian Jiang wrote:
> > But I am not clear where to cal
On 1/22/20 6:05 PM, Ian Jiang wrote:
> But I am not clear where to call this new helper gen_nanbox_fpr(). Is
> there a position that could affect all floating-point instructions? So
> that we don't have to modify so many translating functions. Please
> give more details.
No, this will have to be c
Richard Henderson 于2020年1月23日周四 上午11:07写道：
>
> On 1/22/20 2:48 PM, Ian Jiang wrote:
> > Richard Henderson 于2020年1月23日周四 上午1:11写道：
> >>
> >> On 1/21/20 11:53 PM, Ian Jiang wrote:
> >>> --
> >>> Ian Jiang
> >>>
> >>> Richard Henderson 于2020年1月22日周三 下午4:53写道：
>
> On 1/21/20 9:24 PM, Ian J
On 1/22/20 2:48 PM, Ian Jiang wrote:
> Richard Henderson 于2020年1月23日周四 上午1:11写道：
>>
>> On 1/21/20 11:53 PM, Ian Jiang wrote:
>>> --
>>> Ian Jiang
>>>
>>> Richard Henderson 于2020年1月22日周三 下午4:53写道：
On 1/21/20 9:24 PM, Ian Jiang wrote:
> For FMV.W.X that moves the lower 32 bits of an i
Richard Henderson 于2020年1月23日周四 上午1:11写道：
>
> On 1/21/20 11:53 PM, Ian Jiang wrote:
> > --
> > Ian Jiang
> >
> > Richard Henderson 于2020年1月22日周三 下午4:53写道：
> >>
> >> On 1/21/20 9:24 PM, Ian Jiang wrote:
> >>> For FMV.W.X that moves the lower 32 bits of an integer register to a
> >>> floating-point
On 1/21/20 11:53 PM, Ian Jiang wrote:
> --
> Ian Jiang
>
> Richard Henderson 于2020年1月22日周三 下午4:53写道：
>>
>> On 1/21/20 9:24 PM, Ian Jiang wrote:
>>> For FMV.W.X that moves the lower 32 bits of an integer register to a
>>> floating-point register, Rd should encoded with NoN-boxing scheme.
>>> Note:
--
Ian Jiang
Richard Henderson 于2020年1月22日周三 下午4:53写道：
>
> On 1/21/20 9:24 PM, Ian Jiang wrote:
> > For FMV.W.X that moves the lower 32 bits of an integer register to a
> > floating-point register, Rd should encoded with NoN-boxing scheme.
> > Note: This applies to RV64 only.
> >
> > Signed-off-b
On 1/21/20 9:24 PM, Ian Jiang wrote:
> For FMV.W.X that moves the lower 32 bits of an integer register to a
> floating-point register, Rd should encoded with NoN-boxing scheme.
> Note: This applies to RV64 only.
>
> Signed-off-by: Ian Jiang
> ---
> target/riscv/insn_trans/trans_rvf.inc.c | 1 +
>
For FMV.W.X that moves the lower 32 bits of an integer register to a
floating-point register, Rd should encoded with NoN-boxing scheme.
Note: This applies to RV64 only.
Signed-off-by: Ian Jiang
---
target/riscv/insn_trans/trans_rvf.inc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target
