On 1/21/20 9:24 PM, Ian Jiang wrote: > For FMV.W.X that moves the lower 32 bits of an integer register to a > floating-point register, Rd should encoded with NoN-boxing scheme. > Note: This applies to RV64 only. > > Signed-off-by: Ian Jiang <ianjiang....@gmail.com> > --- > target/riscv/insn_trans/trans_rvf.inc.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/target/riscv/insn_trans/trans_rvf.inc.c > b/target/riscv/insn_trans/trans_rvf.inc.c > index 172dbfa919..62b7a36567 100644 > --- a/target/riscv/insn_trans/trans_rvf.inc.c > +++ b/target/riscv/insn_trans/trans_rvf.inc.c > @@ -368,6 +368,7 @@ static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x > *a) > > #if defined(TARGET_RISCV64) > tcg_gen_mov_i64(cpu_fpr[a->rd], t0); > + tcg_gen_ori_i64(cpu_fpr[a->rd], cpu_fpr[a->rd], 0xffffffff00000000ULL); > #else > tcg_gen_extu_i32_i64(cpu_fpr[a->rd], t0); > #endif >
This doesn't look right. There's nothing in the spec that says the nan-boxing is restricted to rv64. NaN-boxing is all about FLEN, not XLEN. r~
