: Bin Meng
Sent: Monday 19 October 2020 09:38
To: Ivan Griffin
Cc: Alistair Francis ; QEMU Trivial
; open list:RISC-V ;
qemu-devel@nongnu.org Developers
Subject: Re: [PATCH] hw/riscv: microchip_pfsoc: IOSCBCTRL memmap entry
Hi Ivan,
On Mon, Oct 19, 2020 at 4:17 PM Ivan Griffin wrote:
>
>
Bin Meng ; open
> list:RISC-V ; qemu-devel@nongnu.org Developers
>
> Subject: Re: [PATCH] hw/riscv: microchip_pfsoc: IOSCBCTRL memmap entry
>
> Hi Ivan,
>
> On Sat, Oct 17, 2020 at 12:31 AM Ivan Griffin wrote:
> >
> > I don't know why it isn't documen
n
Cc: Alistair Francis ; QEMU Trivial
; Bin Meng ; open list:RISC-V
; qemu-devel@nongnu.org Developers
Subject: Re: [PATCH] hw/riscv: microchip_pfsoc: IOSCBCTRL memmap entry
Hi Ivan,
On Sat, Oct 17, 2020 at 12:31 AM Ivan Griffin wrote:
>
> I don't know why it isn't documented i
Hi Ivan,
On Sat, Oct 17, 2020 at 12:31 AM Ivan Griffin wrote:
>
> I don't know why it isn't documented in that PDF (or in the register map),
> but if you check
> https://github.com/polarfire-soc/polarfire-soc-bare-metal-library/blob/master/src/platform/drivers/mss_sys_services/mss_sys_services.
ot documented in the official documentation though?
Otherwise it will confuse developers.
Alistair
>
>
> Cheers,
> Ivan
>
>
> -Original Message-
> From: Alistair Francis
> Sent: Friday 16 October 2020 17:08
> To: Ivan Griffin
> Cc: Bin Meng ; QEMU Trivial
;
open list:RISC-V ; qemu-devel@nongnu.org Developers
Subject: Re: [PATCH] hw/riscv: microchip_pfsoc: IOSCBCTRL memmap entry
On Fri, Oct 16, 2020 at 8:04 AM Ivan Griffin wrote:
>
> Adding the PolarFire SoC IOSCBCTRL memory region to prevent QEMU
> reporting a STORE/AMO Access Fault.
&
On Fri, Oct 16, 2020 at 8:04 AM Ivan Griffin wrote:
>
> Adding the PolarFire SoC IOSCBCTRL memory region to prevent QEMU
> reporting a STORE/AMO Access Fault.
>
> This region is used by the PolarFire SoC port of U-Boot to
> interact with the FPGA system controller.
>
> Signed-off-by: Ivan Griffin
Adding the PolarFire SoC IOSCBCTRL memory region to prevent QEMU
reporting a STORE/AMO Access Fault.
This region is used by the PolarFire SoC port of U-Boot to
interact with the FPGA system controller.
Signed-off-by: Ivan Griffin
---
hw/riscv/microchip_pfsoc.c | 6 ++
include/hw/ris
