On Mon, 26 Jul 2021 at 09:06, Sebastian Huber
wrote:
> Ok, I will remove this part from the patch in v2. I probably didn't
> fully understand how the Qemu GICv2 emulation works. What I wanted to
> address is this behaviour (see GICv2 manual) when someone changes the
> GICD_ITARGETSR (n > 1):
>
> "
Hello Luc,
thanks for having a look at the patch.
On 25/07/2021 10:08, Luc Michel wrote:
Hi Sebastian,
On 11:49 Fri 09 Jul , Sebastian Huber wrote:
According to the GICv3 specification register GICD_ISPENDR0 is Banked for each
You're referring to GICv3 but actually modifying GICv2 model.
Hi Sebastian,
On 11:49 Fri 09 Jul , Sebastian Huber wrote:
> According to the GICv3 specification register GICD_ISPENDR0 is Banked for each
You're referring to GICv3 but actually modifying GICv2 model. Having a
look at GICv2 reference manual, your affirmation still hold though.
> connected PE
Cc'ing qemu-arm@
On 7/9/21 11:49 AM, Sebastian Huber wrote:
> According to the GICv3 specification register GICD_ISPENDR0 is Banked for each
> connected PE with GICR_TYPER.Processor_Number < 8. For Qemu this is the case
> since GIC_NCPU == 8.
>
> For SPI, make the interrupt pending on all CPUs a
On 09/07/2021 11:49, Sebastian Huber wrote:
According to the GICv3 specification register GICD_ISPENDR0 is Banked for each
connected PE with GICR_TYPER.Processor_Number < 8. For Qemu this is the case
since GIC_NCPU == 8.
For SPI, make the interrupt pending on all CPUs and not just the processor
According to the GICv3 specification register GICD_ISPENDR0 is Banked for each
connected PE with GICR_TYPER.Processor_Number < 8. For Qemu this is the case
since GIC_NCPU == 8.
For SPI, make the interrupt pending on all CPUs and not just the processor
targets of the interrupt.
This behaviour is
