Cc'ing qemu-arm@
On 7/9/21 11:49 AM, Sebastian Huber wrote:
> According to the GICv3 specification register GICD_ISPENDR0 is Banked for each
> connected PE with GICR_TYPER.Processor_Number < 8. For Qemu this is the case
> since GIC_NCPU == 8.
>
> For SPI, make the interrupt pending on all CPUs and not just the processor
> targets of the interrupt.
>
> This behaviour is at least present on the i.MX7D which uses an
> Cortex-A7MPCore.
>
> Signed-off-by: Sebastian Huber <sebastian.hu...@embedded-brains.de>
> ---
> hw/intc/arm_gic.c | 11 ++++++-----
> 1 file changed, 6 insertions(+), 5 deletions(-)
>
> diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
> index a994b1f024..8e377bac59 100644
> --- a/hw/intc/arm_gic.c
> +++ b/hw/intc/arm_gic.c
> @@ -1294,12 +1294,14 @@ static void gic_dist_writeb(void *opaque, hwaddr
> offset,
>
> for (i = 0; i < 8; i++) {
> if (value & (1 << i)) {
> + int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK;
> +
> if (s->security_extn && !attrs.secure &&
> !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) {
> continue; /* Ignore Non-secure access of Group0 IRQ */
> }
>
> - GIC_DIST_SET_PENDING(irq + i, GIC_DIST_TARGET(irq + i));
> + GIC_DIST_SET_PENDING(irq + i, cm);
> }
> }
> } else if (offset < 0x300) {
> @@ -1317,11 +1319,10 @@ static void gic_dist_writeb(void *opaque, hwaddr
> offset,
> continue; /* Ignore Non-secure access of Group0 IRQ */
> }
>
> - /* ??? This currently clears the pending bit for all CPUs, even
> - for per-CPU interrupts. It's unclear whether this is the
> - corect behavior. */
> if (value & (1 << i)) {
> - GIC_DIST_CLEAR_PENDING(irq + i, ALL_CPU_MASK);
> + int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK;
> +
> + GIC_DIST_CLEAR_PENDING(irq + i, cm);
> }
> }
> } else if (offset < 0x380) {
>
