When Enabled bit is cleared in GITS_CTLR,ITS feature continues
to be enabled.This patch fixes the issue.
Signed-off-by: Shashi Mallela
---
hw/intc/arm_gicv3_its.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
index
Since LPIs do not have an active or active and pending state,the current implementation only clears the LPI pending state from the pending table once ICC_IAR1_EL1 acknowledges the interrupt.But, as part of gicv3_lpi_pending() processing, cs->hpplpi is updated with the next best priotiy lpi (only if
From: Leif LindholmSent: November 11, 2021 1:21 PMTo: Peter MaydellCc: Shashi Mallela; Radoslaw Biernacki; Michael S. Tsirkin; Igor Mammedov; qemu-arm; QEMU Developers; Eric Auger; narmstr...@baylibre.com; Alex Bennée; Marcin JuszkiewiczSubject: Re: [PATCH v8 07/10] hw/arm/sbsa-ref: add ITS
level
to 1 if any of the maintenance interrupt attributes are set.
Confirmed that the GIC maintanence interrupts are triggered and
sbsa acs test cases passed with this change.
Signed-off-by: Shashi Mallela
---
hw/intc/arm_gicv3_cpuif.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff
Hi Eric,
On Mon, 2021-09-13 at 10:19 +0200, Eric Auger wrote:
> Hi Shashi,
>
> On 9/10/21 3:32 PM, shashi.mall...@linaro.org wrote:
> > So that would be the driver code running in guest OS because i see
> > tables being setup by arm-smmu driver code in linux,which is
> > similar to
> > what happen
0 00 00 00 00 00 00 00 00 00 FF FF 00 00 //
0070: 00 00 00 00 30 00 00 00 00 00 00 00 // ....0...
Signed-off-by: Shashi Mallela
Acked-by: Igor Mammedov
Reviewed-by: Peter Maydell
---
tests/data/acpi/virt/IORT | Bin 0 -> 124 bytes
tests/data/acpi/virt/IORT.me
Included creation of ITS as part of virt platform GIC
initialization. This Emulated ITS model now co-exists with kvm
ITS and is enabled in absence of kvm irq kernel support in a
platform.
Signed-off-by: Shashi Mallela
Reviewed-by: Peter Maydell
---
hw/arm/virt.c | 29
Added expected IORT files applicable with latest GICv3
ITS changes.Temporarily differences in these files are
okay.
Signed-off-by: Shashi Mallela
Acked-by: Igor Mammedov
Reviewed-by: Peter Maydell
---
tests/data/acpi/virt/IORT | 0
tests/data/acpi/virt/IORT.memhp
of ITS INT,CLEAR,DISCARD command and
GITS_TRANSLATER processing.
Signed-off-by: Shashi Mallela
Tested-by: Neil Armstrong
Reviewed-by: Peter Maydell
---
hw/intc/arm_gicv3.c| 14 +++
hw/intc/arm_gicv3_common.c | 1 +
hw/intc/arm_gicv3_cpuif.c | 7 +-
hw/intc
Added functionality to trigger ITS command queue processing on
write to CWRITE register and process each command queue entry to
identify the command type and handle commands like MAPD,MAPC,SYNC.
Signed-off-by: Shashi Mallela
Reviewed-by: Peter Maydell
Reviewed-by: Eric Auger
Tested-by: Neil
commands make use of other functionalities implemented to
get device table entry,collection table entry or interrupt translation
table entry required for their processing.
Signed-off-by: Shashi Mallela
Reviewed-by: Peter Maydell
---
hw/intc/arm_gicv3_its.c| 365
Added properties to enable ITS feature and define qemu system
address space memory in gicv3 common,setup distributor and
redistributor registers to indicate LPI support.
Signed-off-by: Shashi Mallela
Reviewed-by: Peter Maydell
Tested-by: Neil Armstrong
---
hw/intc/arm_gicv3_common.c
subsequent ITS processing) and
initialize the same in ITS device.
Signed-off-by: Shashi Mallela
Reviewed-by: Peter Maydell
Reviewed-by: Eric Auger
Tested-by: Neil Armstrong
---
hw/intc/arm_gicv3_its.c| 376 +
hw/intc/gicv3_internal.h | 29
kvm_unit_tests PASS
- Verified Linux Boot functionality
Shashi Mallela (9):
hw/intc: GICv3 ITS initial framework
hw/intc: GICv3 ITS register definitions added
hw/intc: GICv3 ITS command queue framework
hw/intc: GICv3 ITS Command processing
hw/intc: GICv3 ITS Feature enablement
hw/intc: GICv3
Added register definitions relevant to ITS,implemented overall
ITS device framework with stubs for ITS control and translater
regions read/write,extended ITS common to handle mmio init between
existing kvm device and newer qemu device.
Signed-off-by: Shashi Mallela
Reviewed-by: Peter Maydell
So that would be the driver code running in guest OS because i see
tables being setup by arm-smmu driver code in linux,which is similar to
what happens with ITS(table base addresses programmed in registers by
linux driver).
On Fri, 2021-09-10 at 13:54 +0100, Peter Maydell wrote:
> On Fri, 10 Sept
I am referring to the latter,"purely emulated QEMU with an emulated
SMMU that handles accesses to emulated devices"
Thanks
Shashi
On Fri, 2021-09-10 at 10:25 +0100, Peter Maydell wrote:
> On Thu, 9 Sept 2021 at 21:18, wrote:
> > I am trying to understand the approach required for an emulated
> >
Hi All,
I am trying to understand the approach required for an emulated SMMU to
convert IPAs(from each qemu guest) to PAs(respective host addresses)
using stage 2 tables.
The questions i have are:-
1) Since SMMU stage 2 tables are expected to be created and managed by
a hypervisor,if there is no
On Thu, 2021-08-19 at 14:27 +0100, Peter Maydell wrote:
> On Thu, 12 Aug 2021 at 17:53, Shashi Mallela <
> shashi.mall...@linaro.org> wrote:
> > Included creation of ITS as part of SBSA platform GIC
> > initialization.
> >
> > Signed-off-by: Shashi Mallela
On Fri, 2021-08-06 at 13:09 +0200, Igor Mammedov wrote:
> On Thu, 5 Aug 2021 18:30:01 -0400
> Shashi Mallela wrote:
>
> > Included creation of ITS as part of virt platform GIC
> > initialization. This Emulated ITS model now co-exists with kvm
> > ITS and is enabled i
Included creation of ITS as part of virt platform GIC
initialization. This Emulated ITS model now co-exists with kvm
ITS and is enabled in absence of kvm irq kernel support in a
platform.
Signed-off-by: Shashi Mallela
Reviewed-by: Peter Maydell
---
hw/arm/virt.c | 28
Included creation of ITS as part of SBSA platform GIC
initialization.
Signed-off-by: Shashi Mallela
---
hw/arm/sbsa-ref.c | 79 ---
1 file changed, 75 insertions(+), 4 deletions(-)
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index c1629df603
0 00 00 00 00 00 00 00 00 00 FF FF 00 00 //
0070: 00 00 00 00 30 00 00 00 00 00 00 00 // ....0...
Signed-off-by: Shashi Mallela
Acked-by: Igor Mammedov
---
tests/data/acpi/virt/IORT | Bin 0 -> 124 bytes
tests/data/acpi/virt/IORT.memhp | Bin 0 ->
Added expected IORT files applicable with latest GICv3
ITS changes.Temporarily differences in these files are
okay.
Signed-off-by: Shashi Mallela
Acked-by: Igor Mammedov
---
tests/data/acpi/virt/IORT | 0
tests/data/acpi/virt/IORT.memhp | 0
tests/data/acpi/virt
commands make use of other functionalities implemented to
get device table entry,collection table entry or interrupt translation
table entry required for their processing.
Signed-off-by: Shashi Mallela
Reviewed-by: Peter Maydell
---
hw/intc/arm_gicv3_its.c| 351
of ITS INT,CLEAR,DISCARD command and
GITS_TRANSLATER processing.
Signed-off-by: Shashi Mallela
Tested-by: Neil Armstrong
---
hw/intc/arm_gicv3.c| 14 +++
hw/intc/arm_gicv3_common.c | 1 +
hw/intc/arm_gicv3_cpuif.c | 7 +-
hw/intc/arm_gicv3_its.c
Added properties to enable ITS feature and define qemu system
address space memory in gicv3 common,setup distributor and
redistributor registers to indicate LPI support.
Signed-off-by: Shashi Mallela
Reviewed-by: Peter Maydell
Tested-by: Neil Armstrong
---
hw/intc/arm_gicv3_common.c
subsequent ITS processing) and
initialize the same in ITS device.
Signed-off-by: Shashi Mallela
Reviewed-by: Peter Maydell
Reviewed-by: Eric Auger
Tested-by: Neil Armstrong
---
hw/intc/arm_gicv3_its.c| 376 +
hw/intc/gicv3_internal.h | 29
Added functionality to trigger ITS command queue processing on
write to CWRITE register and process each command queue entry to
identify the command type and handle commands like MAPD,MAPC,SYNC.
Signed-off-by: Shashi Mallela
Reviewed-by: Peter Maydell
Reviewed-by: Eric Auger
Tested-by: Neil
Added register definitions relevant to ITS,implemented overall
ITS device framework with stubs for ITS control and translater
regions read/write,extended ITS common to handle mmio init between
existing kvm device and newer qemu device.
Signed-off-by: Shashi Mallela
Reviewed-by: Peter Maydell
functionality.
Changes in v8:
- moved tcg ITS support to virt platform 6.1 options (since it will be
supported in 6.2)
- modified the ite entry access offset based on latest test results
- All kvm_unit_tests PASS
- Verified Linux Boot functionality
Shashi Mallela (10):
hw/intc: GICv3 ITS
Thanks for sharing the observations Neil.
Will take care of it in the next patch-set.
On Fri, 2021-08-06 at 10:58 +0200, Neil Armstrong wrote:
> Hi,
>
> On 06/08/2021 00:29, Shashi Mallela wrote:
> > Added ITS command queue handling for MAPTI,MAPI commands,handled
> > ITS
Included creation of ITS as part of virt platform GIC
initialization. This Emulated ITS model now co-exists with kvm
ITS and is enabled in absence of kvm irq kernel support in a
platform.
Signed-off-by: Shashi Mallela
Reviewed-by: Peter Maydell
---
hw/arm/virt.c | 28
0 00 00 00 00 00 00 00 00 00 FF FF 00 00 //
0070: 00 00 00 00 30 00 00 00 00 00 00 00 // ....0...
Signed-off-by: Shashi Mallela
---
tests/data/acpi/virt/IORT | Bin 0 -> 124 bytes
tests/data/acpi/virt/IORT.memhp | Bin 0 -> 124 bytes
tests/data/a
of ITS INT,CLEAR,DISCARD command and
GITS_TRANSLATER processing.
Signed-off-by: Shashi Mallela
---
hw/intc/arm_gicv3.c| 14 +++
hw/intc/arm_gicv3_common.c | 1 +
hw/intc/arm_gicv3_cpuif.c | 7 +-
hw/intc/arm_gicv3_its.c| 23 +
hw/intc
commands make use of other functionalities implemented to
get device table entry,collection table entry or interrupt translation
table entry required for their processing.
Signed-off-by: Shashi Mallela
Reviewed-by: Peter Maydell
---
hw/intc/arm_gicv3_its.c| 348
Added expected IORT files applicable with latest GICv3
ITS changes.Temporarily differences in these files are
okay.
Signed-off-by: Shashi Mallela
---
tests/data/acpi/virt/IORT | 0
tests/data/acpi/virt/IORT.memhp | 0
tests/data/acpi/virt/IORT.numamem | 0
subsequent ITS processing) and
initialize the same in ITS device.
Signed-off-by: Shashi Mallela
Reviewed-by: Peter Maydell
Reviewed-by: Eric Auger
---
hw/intc/arm_gicv3_its.c| 376 +
hw/intc/gicv3_internal.h | 29 ++
include/hw/intc
Added functionality to trigger ITS command queue processing on
write to CWRITE register and process each command queue entry to
identify the command type and handle commands like MAPD,MAPC,SYNC.
Signed-off-by: Shashi Mallela
Reviewed-by: Peter Maydell
Reviewed-by: Eric Auger
---
hw/intc
Added properties to enable ITS feature and define qemu system
address space memory in gicv3 common,setup distributor and
redistributor registers to indicate LPI support.
Signed-off-by: Shashi Mallela
Reviewed-by: Peter Maydell
---
hw/intc/arm_gicv3_common.c | 12
hw/intc
Included creation of ITS as part of SBSA platform GIC
initialization.
Signed-off-by: Shashi Mallela
---
hw/arm/sbsa-ref.c | 79 ---
1 file changed, 75 insertions(+), 4 deletions(-)
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index c1629df603
Added register definitions relevant to ITS,implemented overall
ITS device framework with stubs for ITS control and translater
regions read/write,extended ITS common to handle mmio init between
existing kvm device and newer qemu device.
Signed-off-by: Shashi Mallela
Reviewed-by: Peter Maydell
-ref versioning to reflect the latest its memory
map change and subsequent future use for helper functions
- All kvm_unit_tests PASS
- Verified Linux Boot functionality
Shashi Mallela (10):
hw/intc: GICv3 ITS initial framework
hw/intc: GICv3 ITS register definitions added
hw/intc: GICv3 ITS com
On Thu, 2021-07-08 at 19:27 +0200, Eric Auger wrote:
> Hi Shashi,
>
> On 7/6/21 11:29 AM, Eric Auger wrote:
> > Hi,
> >
> > On 6/30/21 5:31 PM, Shashi Mallela wrote:
> > > Defined descriptors for ITS device table,collection table and ITS
> > > com
On Thu, 2021-07-08 at 23:05 +0100, Leif Lindholm wrote:
> On Thu, Jul 08, 2021 at 21:05:02 +0100, Peter Maydell wrote:
> > On Thu, 8 Jul 2021 at 20:40, Leif Lindholm
> > wrote:
> > > I think my summary-summary would be:
> > > - I think we will need to introduce a compatiblity-breaking
> > > change
0 00 00 00 00 00 00 00 00 00 FF FF 00 00 //
0070: 00 00 00 00 30 00 00 00 00 00 00 00 // ....0...
Signed-off-by: Shashi Mallela
---
tests/data/acpi/virt/IORT | Bin 0 -> 124 bytes
tests/data/acpi/virt/IORT.memhp | Bin 0 -> 124 bytes
tests/data/a
Added expected IORT files applicable with latest GICv3
ITS changes.Temporarily differences in these files are
okay.
Signed-off-by: Shashi Mallela
---
tests/data/acpi/virt/IORT | 0
tests/data/acpi/virt/IORT.memhp | 0
tests/data/acpi/virt/IORT.numamem | 0
Included creation of ITS as part of SBSA platform GIC
initialization.
Signed-off-by: Shashi Mallela
---
hw/arm/sbsa-ref.c | 26 +++---
1 file changed, 23 insertions(+), 3 deletions(-)
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index 43c19b4923..3d9c073636 100644
of ITS INT,CLEAR,DISCARD command and
GITS_TRANSLATER processing.
Signed-off-by: Shashi Mallela
---
hw/intc/arm_gicv3.c| 14 +++
hw/intc/arm_gicv3_common.c | 1 +
hw/intc/arm_gicv3_cpuif.c | 7 +-
hw/intc/arm_gicv3_its.c| 23 +
hw/intc
Added properties to enable ITS feature and define qemu system
address space memory in gicv3 common,setup distributor and
redistributor registers to indicate LPI support.
Signed-off-by: Shashi Mallela
Reviewed-by: Peter Maydell
---
hw/intc/arm_gicv3_common.c | 12
hw/intc
Added register definitions relevant to ITS,implemented overall
ITS device framework with stubs for ITS control and translater
regions read/write,extended ITS common to handle mmio init between
existing kvm device and newer qemu device.
Signed-off-by: Shashi Mallela
Reviewed-by: Peter Maydell
Added functionality to trigger ITS command queue processing on
write to CWRITE register and process each command queue entry to
identify the command type and handle commands like MAPD,MAPC,SYNC.
Signed-off-by: Shashi Mallela
Reviewed-by: Peter Maydell
Reviewed-by: Eric Auger
---
hw/intc
commands make use of other functionalities implemented to
get device table entry,collection table entry or interrupt translation
table entry required for their processing.
Signed-off-by: Shashi Mallela
---
hw/intc/arm_gicv3_its.c| 354 -
hw/intc/gicv3_internal.h
Included creation of ITS as part of virt platform GIC
initialization. This Emulated ITS model now co-exists with kvm
ITS and is enabled in absence of kvm irq kernel support in a
platform.
Signed-off-by: Shashi Mallela
Reviewed-by: Peter Maydell
---
hw/arm/virt.c | 28
and
gicv3_internal.h #defines
- All kvm_unit_tests PASS
Shashi Mallela (10):
hw/intc: GICv3 ITS initial framework
hw/intc: GICv3 ITS register definitions added
hw/intc: GICv3 ITS command queue framework
hw/intc: GICv3 ITS Command processing
hw/intc: GICv3 ITS Feature enablement
hw
subsequent ITS processing) and
initialize the same in ITS device.
Signed-off-by: Shashi Mallela
Reviewed-by: Peter Maydell
Reviewed-by: Eric Auger
---
hw/intc/arm_gicv3_its.c| 376 +
hw/intc/gicv3_internal.h | 29 ++
include/hw/intc
> > > > On Wed, 30 Jun 2021 at 16:32, Shashi Mallela <
> > > > > shashi.mall...@linaro.org> wrote:
> > > > > > Added register definitions relevant to ITS,implemented
> > > > > > overall
> > > > > > ITS device fram
On Tue, 2021-07-06 at 14:27 +0100, Peter Maydell wrote:
> On Tue, 6 Jul 2021 at 13:46, wrote:
> > On Tue, 2021-07-06 at 10:19 +0100, Peter Maydell wrote:
> > > On Tue, 6 Jul 2021 at 04:25, wrote:
> > >
> > > But the pseudocode for MAPTI does not say anywhere that we should
> > > be checking the
On Tue, 2021-07-06 at 09:44 +0200, Eric Auger wrote:
> Hi,
>
> On 6/30/21 5:31 PM, Shashi Mallela wrote:
> > Added register definitions relevant to ITS,implemented overall
> > ITS device framework with stubs for ITS control and translater
> > regions read/write,extende
On Tue, 2021-07-06 at 11:27 +0200, Eric Auger wrote:
> Hi,
>
> On 7/5/21 4:07 PM, Peter Maydell wrote:
> > On Wed, 30 Jun 2021 at 16:32, Shashi Mallela <
> > shashi.mall...@linaro.org> wrote:
> > > Added ITS command queue handling for MAPTI,MAPI commands,handl
; > Hi,
> > >
> > > On 6/11/21 6:21 PM, Eric Auger wrote:
> > > > Hi,
> > > >
> > > > On 6/2/21 8:00 PM, Shashi Mallela wrote:
> > > > > Added register definitions relevant to ITS,implemented
> > > > > overall
&g
Hi Eric,
Please find my response inline(below):-
On Tue, 2021-07-06 at 09:38 +0200, Eric Auger wrote:
> Hi,
>
> On 6/11/21 6:21 PM, Eric Auger wrote:
> > Hi,
> >
> > On 6/2/21 8:00 PM, Shashi Mallela wrote:
> > > Added register definitions relevant to ITS,
On Tue, 2021-07-06 at 10:19 +0100, Peter Maydell wrote:
> On Tue, 6 Jul 2021 at 04:25, wrote:
> > On Mon, 2021-07-05 at 20:47 -0400, shashi.mall...@linaro.org wrote:
> > > On Mon, 2021-07-05 at 15:54 +0100, Peter Maydell wrote:
> > > > I missed this the first time around, but I don't think this is
On Mon, 2021-07-05 at 20:47 -0400, shashi.mall...@linaro.org wrote:
> On Mon, 2021-07-05 at 15:54 +0100, Peter Maydell wrote:
> > On Wed, 30 Jun 2021 at 16:32, Shashi Mallela <
> > shashi.mall...@linaro.org> wrote:
> > > Added ITS command queue handling for MAPTI,M
On Mon, 2021-07-05 at 15:54 +0100, Peter Maydell wrote:
> On Wed, 30 Jun 2021 at 16:32, Shashi Mallela <
> shashi.mall...@linaro.org> wrote:
> > Added ITS command queue handling for MAPTI,MAPI commands,handled
> > ITS
> > translation which triggers an LPI via INT c
On Mon, 2021-07-05 at 17:25 +0100, Peter Maydell wrote:
> On Mon, 5 Jul 2021 at 16:55, wrote:
> > On Mon, 2021-07-05 at 15:58 +0100, Peter Maydell wrote:
> > > On Wed, 30 Jun 2021 at 16:32, Shashi Mallela <
> > > shashi.mall...@linaro.org> wrote:
> > > &g
On Mon, 2021-07-05 at 15:58 +0100, Peter Maydell wrote:
> On Wed, 30 Jun 2021 at 16:32, Shashi Mallela <
> shashi.mall...@linaro.org> wrote:
> > Added register definitions relevant to ITS,implemented overall
> > ITS device framework with stubs for ITS control and translate
Updated expected IORT files applicable with latest GICv3
ITS changes.
Signed-off-by: Shashi Mallela
---
tests/data/acpi/virt/IORT | Bin 0 -> 124 bytes
tests/data/acpi/virt/IORT.memhp | Bin 0 -> 124 bytes
tests/data/acpi/virt/IORT.numamem | Bin 0
Included creation of ITS as part of virt platform GIC
initialization. This Emulated ITS model now co-exists with kvm
ITS and is enabled in absence of kvm irq kernel support in a
platform.
Signed-off-by: Shashi Mallela
Reviewed-by: Peter Maydell
---
hw/arm/virt.c | 28
Added expected IORT files applicable with latest GICv3
ITS changes.Temporarily differences in these files are
okay.
Signed-off-by: Shashi Mallela
---
tests/data/acpi/virt/IORT | 0
tests/data/acpi/virt/IORT.memhp | 0
tests/data/acpi/virt/IORT.numamem | 0
Included creation of ITS as part of SBSA platform GIC
initialization.
Signed-off-by: Shashi Mallela
---
hw/arm/sbsa-ref.c | 26 +++---
1 file changed, 23 insertions(+), 3 deletions(-)
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index 43c19b4923..3d9c073636 100644
Added properties to enable ITS feature and define qemu system
address space memory in gicv3 common,setup distributor and
redistributor registers to indicate LPI support.
Signed-off-by: Shashi Mallela
---
hw/intc/arm_gicv3_common.c | 12
hw/intc/arm_gicv3_dist.c
of ITS INT,CLEAR,DISCARD command and
GITS_TRANSLATER processing.
Signed-off-by: Shashi Mallela
---
hw/intc/arm_gicv3.c| 14 +++
hw/intc/arm_gicv3_common.c | 1 +
hw/intc/arm_gicv3_cpuif.c | 7 +-
hw/intc/arm_gicv3_its.c| 24 -
hw/intc
commands make use of other functionalities implemented to
get device table entry,collection table entry or interrupt translation
table entry required for their processing.
Signed-off-by: Shashi Mallela
---
hw/intc/arm_gicv3_its.c| 361 -
hw/intc/gicv3_internal.h
subsequent ITS processing) and
initialize the same in ITS device.
Signed-off-by: Shashi Mallela
Reviewed-by: Peter Maydell
---
hw/intc/arm_gicv3_its.c| 376 +
hw/intc/gicv3_internal.h | 31 +-
include/hw/intc/arm_gicv3_common.h | 3
Added register definitions relevant to ITS,implemented overall
ITS device framework with stubs for ITS control and translater
regions read/write,extended ITS common to handle mmio init between
existing kvm device and newer qemu device.
Signed-off-by: Shashi Mallela
Reviewed-by: Peter Maydell
functionality.
Changes in v5:
- v4 review comments addressed
- All kvm_unit_tests PASS
Shashi Mallela (10):
hw/intc: GICv3 ITS initial framework
hw/intc: GICv3 ITS register definitions added
hw/intc: GICv3 ITS command queue framework
hw/intc: GICv3 ITS Command processing
hw/intc: GICv3 ITS
Added functionality to trigger ITS command queue processing on
write to CWRITE register and process each command queue entry to
identify the command type and handle commands like MAPD,MAPC,SYNC.
Signed-off-by: Shashi Mallela
Reviewed-by: Peter Maydell
---
hw/intc/arm_gicv3_its.c | 305
elow):-
> >
> > On Sun, 2021-06-13 at 17:55 +0200, Eric Auger wrote:
> > > Hi Shashi,
> > >
> > > On 6/2/21 8:00 PM, Shashi Mallela wrote:
> > > > Added ITS command queue handling for MAPTI,MAPI
> > > > commands,handled
>
gt; > On Sun, 2021-06-13 at 16:13 +0200, Eric Auger wrote:
> > > Hi Sashi,
> > >
> > > On 6/2/21 8:00 PM, Shashi Mallela wrote:
> > > > Added functionality to trigger ITS command queue processing on
> > > > write to CWRITE register and process ea
> >
> > On Sat, 2021-06-12 at 08:08 +0200, Eric Auger wrote:
> > > On 6/2/21 8:00 PM, Shashi Mallela wrote:
> > > > Defined descriptors for ITS device table,collection table and
> > > > ITS
> > > > command queue entities.Implemented register
Hi Eric,
Had missed this comment earlier.Please find my response (inline)below:-
On Sun, 2021-06-13 at 16:39 +0200, Eric Auger wrote:
> Hi,
>
> On 6/2/21 8:00 PM, Shashi Mallela wrote:
> > Added functionality to trigger ITS command queue processing on
> > write to CWRITE
qemu-xhci,p2=8,p3=8,id=usb,bus=pci.2,addr=0x0 -device
> virtio-scsi-pci,id=scsi0,bus=pci.3,addr=0x0 -drive
> file=/var/lib/libvirt/images/EulerOS-2.8-
> Rich.qcow2,format=qcow2,if=none,id=drive-scsi0-0-0-0
> -device
> scsi-hd,bus=scsi0.0,channel=0,scsi-id=0,lun=0,drive=drive-s
Hi Eric,
Have accepted all comments with responses inline (below):-
On Sun, 2021-06-13 at 18:26 +0200, Eric Auger wrote:
> Hi Shashi,
>
> On 6/2/21 8:00 PM, Shashi Mallela wrote:
> > Implemented lpi processing at redistributor to get lpi config info
> s/Implemented/Implement
Hi Eric,
Please find my responses inline (below):-
On Sun, 2021-06-13 at 16:13 +0200, Eric Auger wrote:
> Hi Sashi,
>
> On 6/2/21 8:00 PM, Shashi Mallela wrote:
> > Added functionality to trigger ITS command queue processing on
> > write to CWRITE register and process eac
Hi Eric,
Please find my responses inline (below):-
On Sun, 2021-06-13 at 17:55 +0200, Eric Auger wrote:
> Hi Shashi,
>
> On 6/2/21 8:00 PM, Shashi Mallela wrote:
> > Added ITS command queue handling for MAPTI,MAPI commands,handled
> > ITS
> > translation which trigger
Hi Eric,
Please find my responses inline (below):-
On Sat, 2021-06-12 at 08:08 +0200, Eric Auger wrote:
>
> On 6/2/21 8:00 PM, Shashi Mallela wrote:
> > Defined descriptors for ITS device table,collection table and ITS
> > command queue entities.Implemented register re
On Jun 11 2021, at 4:30 am, Peter Maydell wrote:
> On Fri, 11 Jun 2021 at 00:39, Shashi Mallela
> wrote:
> >
> > Have addressed all comments except the ones with responses(inline) below:-
> >
> > On Jun 8 2021, at 9:57 am, Peter Maydell wrote:
> >
>
On Jun 11 2021, at 12:21 pm, Eric Auger wrote:
> Hi,
>
> On 6/2/21 8:00 PM, Shashi Mallela wrote:
> > Added register definitions relevant to ITS,implemented overall
> > ITS device framework with stubs for ITS control and translater
> > regions read/write,extended ITS
Have addressed all comments except the ones with responses(inline) below:-
On Jun 8 2021, at 9:57 am, Peter Maydell wrote:
> On Wed, 2 Jun 2021 at 19:00, Shashi Mallela wrote:
> >
> > Implemented lpi processing at redistributor to get lpi config info
> > from lpi configur
On Fri, 2021-06-04 at 11:42 +0100, Leif Lindholm wrote:
> On Thu, Jun 03, 2021 at 11:31:21 -0400, shashi.mall...@linaro.org
> wrote:
> > On Thu, 2021-06-03 at 12:42 +0100, Leif Lindholm wrote:
> > > On Wed, Jun 02, 2021 at 14:00:41 -0400, Shashi Mallela wrote:
> > >
On Thu, 2021-06-03 at 12:42 +0100, Leif Lindholm wrote:
> On Wed, Jun 02, 2021 at 14:00:41 -0400, Shashi Mallela wrote:
> > Included creation of ITS as part of SBSA platform GIC
> > initialization.
> >
> > Signed-off-by: Shashi Mallela
> >
Yes it does.
Thanks
Shashi
On Jun 3 2021, at 8:56 am, Peter Maydell wrote:
> On Thu, 3 Jun 2021 at 12:01, Jean-Philippe Brucker
> wrote:
> >
> > Commit 382c7160d1cd ("hw/intc/arm_gicv3_cpuif: Fix EOIR write access
> > check logic") added an assert_not_reached() if the guest writes the EOIR
> >
Added expected IORT files applicable with latest
GICv3 ITS changes.
Signed-off-by: Shashi Mallela
---
tests/data/acpi/virt/IORT | Bin 0 -> 124 bytes
tests/data/acpi/virt/IORT.memhp | Bin 0 -> 124 bytes
tests/data/acpi/virt/IORT.numamem | Bin 0 -> 124 bytes
tests/data/
Included creation of ITS as part of virt platform GIC
initialization.This Emulated ITS model now co-exists with kvm
ITS and is enabled in absence of kvm irq kernel support in a
platform.
Signed-off-by: Shashi Mallela
---
hw/arm/virt.c | 27 +--
include/hw/arm
Included creation of ITS as part of SBSA platform GIC
initialization.
Signed-off-by: Shashi Mallela
---
hw/arm/sbsa-ref.c | 26 +++---
1 file changed, 23 insertions(+), 3 deletions(-)
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index 43c19b4923..3d9c073636 100644
of ITS INT,CLEAR,DISCARD command and
GITS_TRANSLATER processing.
Signed-off-by: Shashi Mallela
---
hw/intc/arm_gicv3.c| 9 ++
hw/intc/arm_gicv3_common.c | 1 +
hw/intc/arm_gicv3_cpuif.c | 7 +-
hw/intc/arm_gicv3_its.c| 14 ++-
hw/intc
Added properties to enable ITS feature and define qemu system
address space memory in gicv3 common,setup distributor and
redistributor registers to indicate LPI support.
Signed-off-by: Shashi Mallela
---
hw/intc/arm_gicv3_common.c | 12
hw/intc/arm_gicv3_dist.c
commands make use of other functionalities implemented to
get device table entry,collection table entry or interrupt translation
table entry required for their processing.
Signed-off-by: Shashi Mallela
---
hw/intc/arm_gicv3_its.c| 334 +
hw/intc/gicv3_internal.h
Added functionality to trigger ITS command queue processing on
write to CWRITE register and process each command queue entry to
identify the command type and handle commands like MAPD,MAPC,SYNC.
Signed-off-by: Shashi Mallela
---
hw/intc/arm_gicv3_its.c | 295
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