= (region->flags & 0x1)) {
> > +return CXL_MBOX_UNSUPPORTED;
> > +}
> > +
> > +if (in->reg_id >= DCD_MAX_NUM_REGION) {
> > +return CXL_MBOX_UNSUPPORTED;
> > +}
> > +
> > +/* Return success if new block size ==
On Mon, 2 Jun 2025 19:29:42 +0530
Arpit Kumar wrote:
Very interesting to see support for this. It will enable a load
of additional test cases.
> added assert-deassert PERST implementation, reset PPB
> for physical port.
Added
Please also include some details of testing done and what happens.
> > > +/* CXL r3.2 Section 7.6.7.6.5 Initiate Dynamic Capacity Add (Opcode
> > > 5604h) */
> > > +static CXLRetCode cmd_fm_initiate_dc_add(const struct cxl_cmd *cmd,
> > > + uint8_t *payload_in,
> > > + size_t len_in
On Mon, 2 Jun 2025 19:29:40 +0530
Arpit Kumar wrote:
> Physical ports info is stored for both mailbox cci &
> mctp based cci type as per spec CXL r3.2 Table 8-230: Physical Switch
>
> Signed-off-by: Arpit Kumar
Hi Arpit,
Sorry for slow response. I got behind on reviews in general and missed
t
On Fri, 6 Jun 2025 11:21:08 -0700
Fan Ni wrote:
> On Thu, Jun 05, 2025 at 11:42:22PM +, anisa.su...@gmail.com wrote:
> > From: Anisa Su
> >
> > FM DCD Management command 0x5604 implemented per CXL r3.2 Spec Section
> > 7.6.7.6.5
> >
> > Signed-off-by: Anisa Su
>
> See below...
A few f
On Mon, 9 Jun 2025 17:33:31 +0100
Jonathan Cameron via wrote:
> The CCI and Fabric Manager APIs are used to configure CXL switches and
> devices. DMTF has defined an MCTP binding specification to carry these
> messages. The end goal of this work is to hook this up to emulated CXL
>
On Fri, 6 Jun 2025 00:28:42 +
Anisa Su wrote:
> On Mon, Jun 02, 2025 at 05:46:57PM +, Anisa Su wrote:
> > On Fri, May 30, 2025 at 03:26:55PM +0100, Jonathan Cameron wrote:
> > > On Tue, 20 May 2025 14:39:47 +0100
> > > Jonathan Cameron via wrote:
> >
On Mon, 2 Jun 2025 19:29:41 +0530
Arpit Kumar wrote:
> Modified Identify Switch Device (Opcode 5100h)
> & Get Physical Port State(Opcode 5101h)
> using physical ports info stored during enumeration
>
> Signed-off-by: Arpit Kumar
A few additional comments in here.
J
> ---
> hw/cxl/cxl-mailbox
On Tue, 10 Jun 2025 07:53:31 +0900
Itaru Kitayama wrote:
> On Thu, May 29, 2025 at 04:08:01PM +0100, Jonathan Cameron wrote:
> > On Wed, 28 May 2025 12:07:23 +0100
> > Jonathan Cameron wrote:
> >
> > > Previously these somewhat device like structures were tra
From: Klaus Jensen
Add i2c_smbus_pec() to calculate the SMBus Packet Error Code for a
message.
Reviewed-by: Jonathan Cameron
Signed-off-by: Klaus Jensen
Acked-by: Corey Minyard
Link: https://lore.kernel.org/r/20230914-nmi-i2c-v6-1-11bbb4f74...@samsung.com
Signed-off-by: Jonathan Cameron
i2c target mode, this can currently only be used with
an SoC that includes the Aspeed I2C controller.
Note, only get timestamp added for now.
Signed-off-by: Jonathan Cameron
---
include/hw/cxl/cxl_device.h | 8 +
include/hw/pci-bridge/cxl_upstream_port.h | 1 +
hw/cxl/cxl-mailbox
t a tree with this on at gitlab.com/jic23/qemu shortly
(cxl-).
Jonathan Cameron (3):
hw/cxl/i2c_mctp_cxl: Initial device emulation
docs: cxl: Add example commandline for MCTP CXL CCIs
usb/mctp/cxl: CXL FMAPI interface via MCTP over usb.
Klaus Jensen (2):
hw/i2c: add smbus pec utili
Add initial documentation for the MCTP over I2C management device. At
current time this can only be used with the Aspeed I2C controller which
is only available in aspeed SoCs, though can be added to other
emulated boards.
Signed-off-by: Jonathan Cameron
---
docs/system/devices/cxl.rst | 27
all error conditions are fully checked / handled.
- MTU in the 'to host' direction is ignored. Seems the Linux
stack doesn't care about this today but that should be brought
into compliance with the specification anyway.
Signed-off-by: Jonathan Cameron
---
include/hw/usb.h |
code[1] previously posted by
Jonathan Cameron.
Squashed a fix[2] from Matt Johnston.
[1]:
https://lore.kernel.org/qemu-devel/20220520170128.4436-1-jonathan.came...@huawei.com/
[2]:
https://lore.kernel.org/qemu-devel/20221121080445.ga29...@codeconstruct.com.au/
Tested-by: Jonathan Cameron
On Fri, 30 May 2025 02:59:40 +
"Zhijian Li (Fujitsu)" wrote:
> On 29/05/2025 21:48, Jonathan Cameron via wrote:
> > This has been wrong from day 1. For now we only have
> > two entries (component and device registers).
>
> Wow, I finally understood this
On Fri, 30 May 2025 14:05:16 +0200
Igor Mammedov wrote:
> On Fri, 30 May 2025 11:02:27 +0100
> Jonathan Cameron wrote:
>
> > On Tue, 27 May 2025 09:40:07 +0200
> > Eric Auger wrote:
> >
> > > acpi_dsdt_add_pci_osc() name is confusing as it gives the
On Tue, 20 May 2025 14:39:47 +0100
Jonathan Cameron via wrote:
> On Thu, 8 May 2025 00:00:56 +
> anisa.su...@gmail.com wrote:
>
> > From: Anisa Su
> >
> > This patchset adds support for 6 FM API DCD Management commands
> > (0x5600-0x5605)
> > acco
On Thu, 8 May 2025 00:00:58 +
anisa.su...@gmail.com wrote:
> From: Anisa Su
>
> FM DCD Management command 0x5600 implemented per CXL 3.2 Spec Section
> 7.6.7.6.1.
>
> Signed-off-by: Anisa Su
Looks like a missing include - though probably due to some indirect include
going away.
> ---
>
t; > > hw/cxl/cxl-mailbox-utils.c | 68 ++--
> > > include/hw/cxl/cxl_opcodes.h | 64 +
> >
> > Should we put the opcodes into include/hw/cxl/cxl_mailbox.h instead of
> > creating a new file.
On Tue, 27 May 2025 09:40:15 +0200
Eric Auger wrote:
> We plan to reuse build_append_notification_callback() on ARM
> so let's move it to pcihp.c.
>
> No functional change intended.
>
> Signed-off-by: Eric Auger
> Reviewed-by: Gustavo Romero
FWIW given it's jus
On Thu, 29 May 2025 14:48:28 +0100
Jonathan Cameron wrote:
> This has been wrong from day 1. For now we only have
> two entries (component and device registers).
>
> The wrong size could lead to arbitrary data off the stack being presented
> in PCIe config space.
As noted in r
On Tue, 27 May 2025 09:40:06 +0200
Eric Auger wrote:
> Add a new argument to acpi_dsdt_add_pci_osc to be able to disable
> native pci hotplug.
>
> Signed-off-by: Eric Auger
> Reviewed-by: Gustavo Romero
Hi Eric,
Makes me wonder what we should do for CXL - I was expecting
a very similar chang
ions in a different order in the destination
would be a good thing to add to this description?
Either way
Reviewed-by: Jonathan Cameron
>
> No functional change intended.
>
> Signed-off-by: Eric Auger
> Reviewed-by: Gustavo Romero
> ---
> include/hw/acpi/pci.h | 1 -
On Tue, 27 May 2025 09:40:14 +0200
Eric Auger wrote:
> On ARM we will put the operation regions in AML_SYSTEM_MEMORY.
> So let's allow this configuration.
>
> Signed-off-by: Eric Auger
> Reviewed-by: Gustavo Romero
Reviewed-by: Jonathan Cameron
vo Romero
Trivial comment inline.
Reviewed-by: Jonathan Cameron
> ---
> include/hw/acpi/pcihp.h | 2 ++
> hw/acpi/pcihp.c | 20
> hw/i386/acpi-build.c| 15 ++-
> 3 files changed, 24 insertions(+), 13 deletions(-)
>
> diff --git
On Tue, 27 May 2025 09:40:08 +0200
Eric Auger wrote:
> Propagate the type of pci hotplug mode downto the gpex
> acpi code. In case machine acpi_pcihp is unset we configure
> pci native hotplug on pci0. For expander bridges we keep
> legacy pci native hotplug, as done on x86 q35.
>
> Signed-off-b
On Tue, 27 May 2025 09:40:11 +0200
Eric Auger wrote:
> gpex build_host_bridge_osc() and x86 originated
> build_pci_host_bridge_osc_method() are mostly identical.
>
> In GPEX, SUPP is set to CDW2 but is not further used. CTRL
> is same as Local0.
>
> So let gpex code reuse build_pci_host_bridge_
On Tue, 27 May 2025 09:40:07 +0200
Eric Auger wrote:
> acpi_dsdt_add_pci_osc() name is confusing as it gives the impression
> it appends the _OSC method but in fact it also appends the _DSM method
> for the host bridge. Let's split the function into two separate ones
> and let them return the met
On Fri, 30 May 2025 10:27:11 +0100
Jonathan Cameron wrote:
> On Tue, 27 May 2025 09:40:06 +0200
> Eric Auger wrote:
>
> > Add a new argument to acpi_dsdt_add_pci_osc to be able to disable
> > native pci hotplug.
> >
> > Signed-off-by: Eric Auger
> >
plug is renamed into build_acpi_pci_hotplug().
>
> No code change intended.
>
> Also fix the reference to acpi_pci_hotplug.rst documentation
>
> Signed-off-by: Eric Auger
> Reviewed-by: Gustavo Romero
Indeed moves the code as described...
Reviewed-by: Jonathan Cameron
ed-off-by: Eric Auger
> Reviewed-by: Gustavo Romero
Seems fine though I'm not sure on the default for 10.1
I don't feel that strongly about it though.
Reviewed-by: Jonathan Cameron
On Tue, 27 May 2025 09:40:03 +0200
Eric Auger wrote:
> No need to export aml_pci_device_dsm() as it is only used
> in hw/i386/acpi-build.c.
>
> Signed-off-by: Eric Auger
> Reviewed-by: Gustavo Romero
> Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Jonathan Cameron
&
amic capacity
> "nr_extents_accepted" which explicitly tracks number of the extents
> accepted by the hosts, and fix "total_extent_count" to include
> both accepted and pending extents counting.
>
> Signed-off-by: Fan Ni
> Reviewed-by: Jonathan Cameron
Thanks. Mich
On Wed, 28 May 2025 12:07:23 +0100
Jonathan Cameron wrote:
> Previously these somewhat device like structures were tracked using a list
> in the CXLState in each machine. This is proving restrictive in a few
> cases where we need to iterate through these without being aware of the
for review
with mst +CC so maybe just send a v2 of this (rebased on upstream)
and add
Reviewed-by: Jonathan Cameron
This has been wrong from day 1. For now we only have
two entries (component and device registers).
The wrong size could lead to arbitrary data off the stack being presented
in PCIe config space.
Signed-off-by: Jonathan Cameron
---
include/hw/cxl/cxl_pci.h | 2 +-
1 file changed, 1 insertion
On Thu, 22 May 2025 12:01:35 +0530
Vinayak Holikatti wrote:
> CXL spec 3.2 section 7.6.7.5.2 describes Get Head Info.
>
> Signed-off-by: Vinayak Holikatti
Hi Vinayak,
Some code simplification suggestions below.
> ---
> This patch is generated against Jonathan Cameron'
On Thu, 29 May 2025 06:57:29 +0900
Itaru Kitayama wrote:
> Hi Jonathan,
>
> On Wed, May 28, 2025 at 12:07:21PM +0100, Jonathan Cameron wrote:
> > v14: Simplifications suggeseted by Itaru (and some extra simplifications
> > that became apparent) and gather tags.
&g
Add a single complex case for aarch64 virt machine.
Given existing much more comprehensive tests for x86 cover the
common functionality, a single test should be enough to verify
that the aarch64 part continue to work.
Tested-by: Itaru Kitayama
Signed-off-by: Jonathan Cameron
---
v14: Tags only
On Wed, 28 May 2025 13:31:06 +0100
Jonathan Cameron wrote:
> On Fri, 16 May 2025 19:12:45 +0530
> Arpit Kumar wrote:
>
> > On 12/05/25 05:40PM, Jonathan Cameron wrote:
> > >On Mon, 12 May 2025 09:37:07 -0400
> > >"Michael S. Tsirkin" wrote:
>
On Fri, 16 May 2025 19:12:45 +0530
Arpit Kumar wrote:
> On 12/05/25 05:40PM, Jonathan Cameron wrote:
> >On Mon, 12 May 2025 09:37:07 -0400
> >"Michael S. Tsirkin" wrote:
> >
> >> On Mon, May 12, 2025 at 04:42:41AM -0400, Michael S. Tsirkin wrote:
&
guest software stack.
Note this is TCG only - it is possible to support limited use with KVM but
that needs additional patches not yet ready for upstream. The challenge
is interleave - and the solution is don't interleave if you want to run
with KVM.
Jonathan Cameron (5):
hw/cxl-host: A
To enable these to be found in a fixed order, that order needs
to be known. This will later be used to sort a list of these
structures that address map and ACPI table entries are predictable.
Reviewed-by: Li Zhijian
Reviewed-by: Fan Ni
Signed-off-by: Jonathan Cameron
---
v14: Picked up tags
Code based on i386/pc enablement.
The memory layout places space for 16 host bridge register regions after
the GIC_REDIST2 in the extended memmap.
The CFMWs are placed above the extended memmap.
Only create the CEDT table if cxl=on set for the machine.
Signed-off-by: Jonathan Cameron
describing the CFMWS.
Other aspects don't have this constraint. For those direct iteration
of the underlying hash structures is fine.
Signed-off-by: Jonathan Cameron
---
v14: Drop some unnecessary checks on device type. (Zhijian)
Use explicit pointer types given we know what they are at the c
On arm/virt the memory map is set up before any devices are brought
up. To enable this provide split functions to establish the fw->base
and later to actually map it.
Signed-off-by: Jonathan Cameron
---
v14: Update wrt to changes in previous patch.
Add a do_cfwms_set_memmap_and_update_m
On Fri, 16 May 2025 05:50:59 +
"Zhijian Li (Fujitsu)" wrote:
> On 13/05/2025 19:14, Jonathan Cameron via wrote:
> >
> > +hwaddr cxl_fmws_set_memmap(hwaddr base, hwaddr max_addr)
> > +{
> > +GSList *cfmws_list, *iter;
> >
On Fri, 16 May 2025 05:44:34 +
"Zhijian Li (Fujitsu)" wrote:
> On 13/05/2025 19:14, Jonathan Cameron via wrote:
> > Previously these somewhat device like structures were tracked using a list
> > in the CXLState in each machine. This is proving restrictive in a few
&
to slow
> flags")
> Reported-by: Jonathan Cameron
> Signed-off-by: Richard Henderson
I've run basic tests (the ones that were tripping over this 100% of the time)
and all looks good. Thanks! I'll run some more comprehensive testing this
afternoon
but looking good.
Tes
ould people like
that to be configured? The address_space_init() call is
fairly early but I think we can modify the max_bounce_buffer_size later
potentially directly from machine_set_mem() if the parameter is set.
I'm also interested if anyone has another suggestion for how to solve this
problem more generally.
Thanks,
Jonathan
On Wed, 21 May 2025 16:38:10 +0900
Itaru Kitayama wrote:
> > On May 19, 2025, at 21:54, Jonathan Cameron
> > wrote:
> >
> > On Thu, 15 May 2025 18:04:18 +0900
> > Itaru Kitayama wrote:
> >
> >>> On May 13, 2025, at 20:14, Jonathan Cameron
On Fri, 16 May 2025 11:30:49 +0900
Itaru Kitayama wrote:
> Hi Jonathan,
>
> > On May 13, 2025, at 20:14, Jonathan Cameron
> > wrote:
> >
> > V13:
> > - Make CXL fixed memory windows sysbus devices.
> > IIRC this was requested by Peter in one of th
On Thu, 8 May 2025 14:29:18 +0100
Jonathan Cameron wrote:
> On Tue, 29 Apr 2025 19:43:05 -0700
> Richard Henderson wrote:
>
> > On 4/29/25 14:35, Alistair Francis wrote:
> > > On Sat, Apr 26, 2025 at 3:36 AM Jonathan Cameron via
> > > wrote:
> >
it to go near the front.
Today I'm focused on getting test cases to Richard for the TCG issues but
after that I'll spin a new tree (probably pushed out under a name
that makes it clear there is a known nasty problem though!)
Jonathan
>
> The code was tested with libcxlmi, wh
On Thu, 8 May 2025 00:01:05 +
anisa.su...@gmail.com wrote:
> From: Anisa Su
>
> FM DCD Management command 0x5604 implemented per CXL r3.2 Spec Section
> 7.6.7.6.5
>
> Signed-off-by: Anisa Su
A few really minor things inline.
> ---
> hw/cxl/cxl-mailbox-utils.c | 195 ++
On Thu, 8 May 2025 00:01:03 +
anisa.su...@gmail.com wrote:
> From: Anisa Su
>
> FM DCD Management command 0x5602 implemented per CXL r3.2 Spec Section
> 7.6.7.6.3
>
> Signed-off-by: Anisa Su
Hi Anisa
A few really trivial things inline.
Jonathan
> ---
> hw
ow its usage outside ghes.c
>
> This reverts commit 611f3bdb20f7828b0813aa90d47d1275ef18329b.
>
> Signed-off-by: Mauro Carvalho Chehab
FWIW (which is maybe just that I don't read the commit message
again if you have to do a v10 ;)
Reviewed-by: Jonathan Cameron
> ---
> hw/a
On Thu, 15 May 2025 18:04:18 +0900
Itaru Kitayama wrote:
> > On May 13, 2025, at 20:14, Jonathan Cameron
> > wrote:
> >
> > Add a single complex case for aarch64 virt machine.
> > Given existing much more comprehensive tests for x86 cover the
> > common fu
Add a single complex case for aarch64 virt machine.
Given existing much more comprehensive tests for x86 cover the
common functionality, a single test should be enough to verify
that the aarch64 part continue to work.
Signed-off-by: Jonathan Cameron
---
tests/qtest/cxl-test.c | 59
Code based on i386/pc enablement.
The memory layout places space for 16 host bridge register regions after
the GIC_REDIST2 in the extended memmap.
The CFMWs are placed above the extended memmap.
Only create the CEDT table if cxl=on set for the machine.
Signed-off-by: Jonathan Cameron
describing the CFMWS.
Other aspects don't have this constraint. For those direct iteration
of the underlying hash structures is fine.
Signed-off-by: Jonathan Cameron
---
I think Peter Maydell suggested this a long time back when
the original CXL support series was under review but not 100%
On arm/virt the memory map is set up before any devices are brought
up. To enable this provide split functions to establish the fw->base
and later to actually map it.
Signed-off-by: Jonathan Cameron
---
include/hw/cxl/cxl_host.h | 2 ++
hw/cxl/cxl-host-stubs.c | 2 ++
hw/cxl/cxl-hos
To enable these to be found in a fixed order, that order needs
to be known. This will later be used to sort a list of these
structures that address map and ACPI table entries are predictable.
Signed-off-by: Jonathan Cameron
---
include/hw/cxl/cxl.h | 1 +
hw/cxl/cxl-host.c| 9 ++---
2
flexibility on SBSA-ref is not
currently practical. SBSA-ref CXL support is an excellent thing, just
not much use to me for this work.
Jonathan Cameron (5):
hw/cxl-host: Add an index field to CXLFixedMemoryWindow
hw/cxl: Make the CXL fixed memory windows devices.
hw/cxl-host: Allow split of establ
On Mon, 12 May 2025 09:37:07 -0400
"Michael S. Tsirkin" wrote:
> On Mon, May 12, 2025 at 04:42:41AM -0400, Michael S. Tsirkin wrote:
> > On Wed, Mar 05, 2025 at 09:24:58AM +, Jonathan Cameron wrote:
> > > From: Arpit Kumar
> > >
> > > CXL
On Mon, 12 May 2025 04:42:37 -0400
"Michael S. Tsirkin" wrote:
> On Wed, Mar 05, 2025 at 09:24:58AM +0000, Jonathan Cameron wrote:
> > From: Arpit Kumar
> >
> > CXL spec 3.2 section 8.2.10.5.3 describes Get Log Capabilities.
> > It provides log ca
On Tue, 29 Apr 2025 19:43:05 -0700
Richard Henderson wrote:
> On 4/29/25 14:35, Alistair Francis wrote:
> > On Sat, Apr 26, 2025 at 3:36 AM Jonathan Cameron via
> > wrote:
> >>
> >> On Tue, 22 Apr 2025 12:26:55 -0700
> >> Richard Henderson wrote:
>
On Fri, 2 May 2025 08:57:36 -0700
Fan Ni wrote:
> On Fri, May 02, 2025 at 10:01:55AM +0100, Jonathan Cameron wrote:
> > On Thu, 1 May 2025 20:21:56 +
> > Fan Ni wrote:
> >
> > > On Thu, Apr 24, 2025 at 11:42:59AM +0100, Jonathan Cameron wrote:
> > &g
On Mon, 5 May 2025 16:40:18 +
Anisa Su wrote:
> On Thu, Apr 24, 2025 at 12:19:59PM +0100, Jonathan Cameron wrote:
> > On Mon, 17 Mar 2025 16:31:35 +
> > anisa.su...@gmail.com wrote:
> >
> > > From: Anisa Su
> > >
> > > FM DCD Managem
On Thu, 1 May 2025 20:21:56 +
Fan Ni wrote:
> On Thu, Apr 24, 2025 at 11:42:59AM +0100, Jonathan Cameron wrote:
> > On Mon, 17 Mar 2025 16:31:30 +
> > anisa.su...@gmail.com wrote:
> >
> > > From: Anisa Su
> > >
> > > Add dsmas_flags f
On Tue, 29 Apr 2025 01:11:01 +
"Zhijian Li (Fujitsu)" wrote:
> Hi Jonathan,
>
>
> I apologize for the delayed response; I have just returned from vacation.
>
>
> On 16/04/2025 00:47, Jonathan Cameron wrote:
> > On Mon, 7 Apr 2025 02:59:20 +0
On Tue, 22 Apr 2025 12:26:55 -0700
Richard Henderson wrote:
> Recover two bits from the inline flags.
Hi Richard,
Early days but something (I'm fairly sure in this patch) is tripping up my
favourite
TCG corner case of running code out of MMIO memory (interleaved CXL memory).
Only seeing it o
to take a look through these (v2 probably)
as he's messed with DCD a lot more than me!
Thanks,
Jonathan
> ---
> hw/cxl/cxl-mailbox-utils.c | 94 ++
> 1 file changed, 94 insertions(+)
>
> diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw
On Mon, 17 Mar 2025 16:31:35 +
anisa.su...@gmail.com wrote:
> From: Anisa Su
>
> FM DCD Management command 0x5604 implemented per CXL r3.2 Spec Section
> 7.6.7.6.5
>
> Signed-off-by: Anisa Su
> ---
> hw/cxl/cxl-mailbox-utils.c | 173
> hw/mem/cxl_typ
On Mon, 17 Mar 2025 16:31:34 +
anisa.su...@gmail.com wrote:
> From: Anisa Su
>
> FM DCD Management command 0x5603 implemented per CXL r3.2 Spec Section
> 7.6.7.6.4
> Very similar to previously implemented command 0x4801.
>
> Signed-off-by: Anisa Su
> ---
> hw/cxl/cxl-mailbox-utils.c | 84
On Mon, 17 Mar 2025 16:31:33 +
anisa.su...@gmail.com wrote:
> From: Anisa Su
>
> FM DCD Management command 0x5602 implemented per CXL r3.2 Spec Section
> 7.6.7.6.3
>
> Signed-off-by: Anisa Su
> ---
> hw/cxl/cxl-mailbox-utils.c | 100 +++
> hw/mem/cxl_typ
On Mon, 17 Mar 2025 16:31:32 +
anisa.su...@gmail.com wrote:
> From: Anisa Su
>
> move definition for dynamic_capacity_uuid and enum for DC event types to
Move
> cxl_events.h from cxl_type3.c for shared use in next patch
>
> Signed-off-by: Anisa Su
> ---
> hw/mem/cxl_type3.c | 1
On Mon, 17 Mar 2025 16:31:31 +
anisa.su...@gmail.com wrote:
> From: Anisa Su
>
> FM DCD Management command 0x5601 implemented per CXL r3.2 Spec Section
> 7.6.7.6.2
>
> Signed-off-by: Anisa Su
Hi Anisa,
Just a few trivial things in here.
> ---
> hw/cxl/cxl-mailbox-utils.c | 97 +
On Mon, 17 Mar 2025 16:31:30 +
anisa.su...@gmail.com wrote:
> From: Anisa Su
>
> Add dsmas_flags field to DC Region struct in preparation for next
> command, which returns the dsmas flags in the response.
>
> Signed-off-by: Anisa Su
> ---
> hw/mem/cxl_type3.c | 2 ++
> include/hw
On Mon, 17 Mar 2025 16:31:29 +
anisa.su...@gmail.com wrote:
> From: Anisa Su
>
> FM DCD Management command 0x5600 implemented per CXL 3.2 Spec Section
> 7.6.7.6.1
>
> Signed-off-by: Anisa Su
It's been too long so I'll look over this again as a precursor
to looking at the later patches...
On Mon, 31 Mar 2025 19:38:45 +
Anisa Su wrote:
> On Tue, Mar 18, 2025 at 03:56:24PM +0000, Jonathan Cameron wrote:
> > On Mon, 17 Mar 2025 16:31:29 +
> > anisa.su...@gmail.com wrote:
> >
> > > From: Anisa Su
> > >
> > > FM DCD Manage
On Mon, 17 Mar 2025 16:31:28 +
anisa.su...@gmail.com wrote:
> From: Anisa Su
>
> Add supported_blk_size field to CXLDCRegion struct in preparation for
> next patch. It is needed by command 0x5600 Get DC Region Config.
Hi Anisa,
Sorry it took me so long to your series!
Squash this with patc
gt; From: Yicong Yang
> > >>
> > >> The lastest ACPI spec 6.5 support PPTT revision 3. Update it
> > >> by handy. This is compatible with previous revision.
> > >>
> > >> Signed-off-by: Yicong Yang
> > >> Reviewed-by: Jonat
On Mon, 7 Apr 2025 02:59:20 +
"Zhijian Li (Fujitsu)" wrote:
> Ping
Sorry, I wrote half a reply but then lost it before sending
- was still in my drafts :(
>
> Only if (dsp_count==1 && hdm_for_passthrough==true), the QEMU shouldn't
> implement
> the HDM decodder for the Host-bridge.
HDM f
like this method. It seems simple
> > and straight-forward, avoids any complex networking between the vms and
> > gives us what we want.
> >
> > I'll wait for Jonathan's commentary, but solid prototype (bn_n)b
> >
> > ~Gregory
>
> Hi Jon
request an old machine + the
device that didn't exist for that machine, then migrate to a real old
version of QEMU. Agreed it is possible but I'm not sure we need to
prevent that particular crazy.
Jonathan
>
> Signed-off-by: Shameer Kolothum
> ---
> ToDo: probably need to
On Tue, 25 Mar 2025 15:49:37 +0800
Yuquan Wang wrote:
> > -原始邮件-
> > 发件人: "Jonathan Cameron"
> > 发送时间:2025-03-13 02:10:35 (星期四)
> > 收件人: "Yuquan Wang"
> > 抄送: qemu-devel@nongnu.org, linux-...@vger.kernel.org
> > 主题: Re: [
> +
> typedef struct CXLMCTPMessage {
> /*
> * DSP0236 (MCTP Base) Integrity Check + Message Type
> @@ -200,7 +203,8 @@ static void i2c_mctp_cxl_handle_message(MCTPI2CEndpoint
> *mctp)
> if (!(msg->message_type == MCTP_MT_CXL_TYPE3 &&
&
On Fri, 14 Mar 2025 08:44:05 -0700
Dan Williams wrote:
> Jonathan Cameron wrote:
> > On Wed, 5 Mar 2025 18:35:40 +0800
> > Yuquan Wang wrote:
> >
> > > >
> > > > On Tue, 4 Mar 2025 14:22:48 +0800
> > > > Yuquan Wang wrote:
> >
On Mon, 10 Mar 2025 16:23:35 +
Alireza Sanaee wrote:
> Add cache topology to PPTT table. With this patch, both ACPI PPTT table
> and device tree will represent the same cache topology given users
> input.
>
> Signed-off-by: Alireza Sanaee
> Co-developed-by: Jonathan Cam
On Mon, 10 Mar 2025 16:23:34 +
Alireza Sanaee wrote:
> Prepare to update `build_pptt` function to add cache description
> functionalities, thus add binaries in this patch.
>
> Signed-off-by: Alireza Sanaee
FWIW table will changes so this patch is needed...
Reviewed-by: Jona
e 3 of those soon.
For the Intel ones can I have a pair for the root port and the CXL
type 3 device (so 2 IDs)? We will probably need one shortly for
the type2 emulation test device as well.
Thanks,
Jonathan
>
> Moving them to qemu pci id range is an option too if you prefer that.
> Your choice.
>
> take care,
> Gerd
>
>
7;ll need the kernel side of that as well)
> > 3) Wire it all up.
> > 4) Do the same for a Switch with MLDs behind it so we can poke the fun
> >corners.
>
>
> Hi,Jonathan
>
> Given your previous exploration, I would like to ask the following questions:
>
On Wed, 5 Mar 2025 18:35:40 +0800
Yuquan Wang wrote:
> >
> > On Tue, 4 Mar 2025 14:22:48 +0800
> > Yuquan Wang wrote:
> >
> > > >
> > > > On Thu, Feb 20, 2025 at 04:12:13PM +, Jonathan Cameron wrote:
> > > > >
ch-cci are using valid Hisilicon IDs that are for
emulation of these device only and are registered in our tracker
for these IDs so won't get 'reused'.
In both those cases the driver binds on class code in Linux so an ID
change to resolve this would be fine for Linux - I can't spea
From: Vinayak Holikatti
CXL spec 3.2 section 8.2.10.9.5.3 describes media operations commands.
CXL devices supports media operations Sanitize and Write zero command.
Signed-off-by: Vinayak Holikatti
Signed-off-by: Jonathan Cameron
---
include/hw/cxl/cxl_device.h | 4 +
hw/cxl/cxl-mailbox
f memory zeroing
/ wiping. Support for aborting background operations is needed to
enable testing of a feature that allows us to enable userspace access
to background commands without risking lockout of urgent kernel commands
Thanks,
Jonathan
Arpit Kumar (1):
hw/cxl/cxl-mailbox-utils: Added support
f memory zeroing
/ wiping. Support for aborting background operations is needed to
enable testing of a feature that allows us to enable userspace access
to background commands without risking lockout of urgent kernel commands
Thanks,
Jonathan
Arpit Kumar (1):
hw/cxl/cxl-mailbox-utils: Added support
From: Arpit Kumar
CXL spec 3.2 section 8.2.10.5.3 describes Get Log Capabilities.
It provides log capabilities supported by specified log.
Signed-off-by: Arpit Kumar
Signed-off-by: Jonathan Cameron
---
include/hw/cxl/cxl_device.h | 20
include/hw/cxl/cxl_mailbox.h | 5
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