.
thank you,
---
dan tan
power simulation
phone:+1.7373.099.138
email:dan...@linux.ibm.com
On 2025-02-17 14:12, Stefan Berger wrote:
On 2/16/25 5:11 PM, dan tan wrote:
*** BLURB HERE ***
Version 9 summary:
1/3 tpm/tpm_tis_spi: Support TPM for SPI
- rebased with the master, and
Yes, good point, Philippe!
I will send an update in a few days in case there are additional
changes to be made.
thank you,
---
dan tan
power simulation
phone:+1.7373.099.138
email:dan...@linux.ibm.com
On 2025-02-17 01:31, Philippe Mathieu-Daudé wrote:
Hi,
On 16/2/25 23:11, dan tan wrote
-content/uploads/TCG_PCClientTPMInterfaceSpecification_TIS__1-3_27_03212013.pdf
The SPI registers are specific to the PowerNV platform
architecture
Signed-off-by: dan tan
---
v3:
- removed the function prototypes declaration
- fixed code format to comply with convention
- changed function names
Implement support for TPM via SPI interface. The SPI bus master
is provided by PowerNV SPI device which is an SSI peripheral.
It can uses the tpm_emulator driver backend with the external
swtpm.
Signed-off-by: dan tan
---
v3:
- moved variable tis_addr from TPMStateSPI struct to local
- added
The addition to ppc/Kconfig is for building this into the
qemu-system-ppc64 binary. The enablement requires the
following command line argument:
-device tpm-tis-spi,tpmdev=tpm0,bus=pnv-spi-bus.4
Signed-off-by: dan tan
---
hw/ppc/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw
st);
- beefed up the unit test exercising major supported locality
functionality
dan tan (3):
tpm/tpm_tis_spi: Support TPM for SPI (Serial Peripheral Interface)
tpm/tpm_tis_spi: activation for the PowerNV machines
tests/qtest/tpm: add unit test to tis-spi
docs/specs/tpm.rst
From: dan tan
Register RWMR - Region Weighted Mode Register
for privileged access in Power9 and Power10
It controls what the SPURR register produces.
Specs:
- Power9: https://ibm.ent.box.com/s/tmklq90ze7aj8f4n32er1mu3sy9u8k3k
- Power10: https://files.openpower.foundation/s/EgCy7C43p2NSRfR
/170679876639.188422.11634974895844092362.st...@ltc-boston1.aus.stglabs.ibm.com/
On 1/8/25 02:21, dan tan wrote:
From: dan tan
*** BLURB HERE ***
Version 3 summary:
RWMR (Region Weighted Mode Register) -
- change the register to generic read/write from nop/write
Version 2 summary:
(DAWR1,DAWRX1):
- spec
From: dan tan
Register RWMR - Region Weighted Mode Register
for privileged access in Power9 and Power10
It controls what the SPURR register produces.
Specs:
- Power9: https://ibm.ent.box.com/s/tmklq90ze7aj8f4n32er1mu3sy9u8k3k
- Power10: https://files.openpower.foundation/s/EgCy7C43p2NSRfR
From: dan tan
The handling of the following two registers are added to POWER10 -
- DAWR1 (0x0bd, 189) - Data Address Watchpoint 1
- DAWRX1 (0x0b5, 181) - Data Address Watchpoint Extension 1
Signed-off-by: dan tan
---
ver 3 no change
ver 2 summary:
- spec reference: https
From: dan tan
*** BLURB HERE ***
Version 3 summary:
RWMR (Region Weighted Mode Register) -
- change the register to generic read/write from nop/write
Version 2 summary:
(DAWR1,DAWRX1):
- spec reference: https://files.openpower.foundation/s/EgCy7C43p2NSRfR
: dan tan
---
Ver 2 summary:
- corrected the previous definition as ITV1
- spec reference:
https://ibm.ent.box.com/s/tmklq90ze7aj8f4n32er1mu3sy9u8k3k (Power9)
- it appears that part of the previous upstream submission SPRs
(SPR_POWER_MMCR3, SPR_POWER_SIER2, SPR_POWER_SIER3
The handling of the following two registers are added to POWER10 -
- DAWR1 (0x0bd, 189) - Data Address Watchpoint 1
- DAWRX1 (0x0b5, 181) - Data Address Watchpoint Extension 1
Signed-off-by: dan tan
---
ver 2 summary:
- spec reference: https://files.openpower.foundation/s/EgCy7C43p2NSRfR
From: dan tan
*** BLURB HERE ***
Version 2 summary:
(DAWR1,DAWRX1):
- spec reference: https://files.openpower.foundation/s/EgCy7C43p2NSRfR
- corrected commit message format
- combine DAWR(0/1) handling into a single function
- add DAWR1 & DAWRX
The addition to ppc/Kconfig is for building this into the
qemu-system-ppc64 binary. The enablement requires the
following command line argument:
-device tpm-tis-spi,tpmdev=tpm0,bus=pnv-spi-bus.4
Signed-off-by: dan tan
---
hw/ppc/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw
Implement support for TPM via SPI interface. The SPI bus master
is provided by PowerNV SPI device which is an SSI peripheral.
It can uses the tpm_emulator driver backend with the external
swtpm.
Signed-off-by: dan tan
---
v3:
- moved variable tis_addr from TPMStateSPI struct to local
- added
-content/uploads/TCG_PCClientTPMInterfaceSpecification_TIS__1-3_27_03212013.pdf
The SPI registers are specific to the PowerNV platform
architecture
Signed-off-by: dan tan
---
v3:
- removed the function prototypes declaration
- fixed code format to comply with convention
- changed function names
tation support (tpm.rst);
- beefed up the unit test exercising major supported locality
functionality
dan tan (3):
tpm/tpm_tis_spi: Support TPM for SPI (Serial Peripheral Interface)
tpm/tpm_tis_spi: activation for the PowerNV machines
tests/qtest/tpm: add unit test to tis-spi
docs/s
Implement support for TPM via SPI interface. The SPI bus master
is provided by PowerNV SPI device which is an SSI peripheral.
It can uses the tpm_emulator driver backend with the external
swtpm.
Signed-off-by: dan tan
---
v3:
- moved variable tis_addr from TPMStateSPI struct to local
- added
s to the TPMStateSPI struct;
- fixed code formatting (verified by scripts/checkpatch.pl);
- per requests, make the code more readable by using self-
explanatory #defines and adding comments;
- added some documentation support (tpm.rst);
- beefed up the unit test exercising major suppo
Good point, Stefan!
Let me put it through our CI tests, which, in addition to unit tests,
also does both Linux (rhel-9) and AIX (ver7) boot exercises
thank you,
---
dan tan
power simulation
phone:+1.7373.099.138
email:dan...@linux.ibm.com
On 2024-11-08 09:38, Stefan Berger wrote:
On 11/4
MStateSPI struct;
- fixed code formatting (verified by scripts/checkpatch.pl);
- per requests, make the code more readable by using self-
explanatory #defines and adding comments;
- added some documentation support (tpm.rst);
- beefed up the unit test exercising major suppo
-content/uploads/TCG_PCClientTPMInterfaceSpecification_TIS__1-3_27_03212013.pdf
The SPI registers are specific to the PowerNV platform
architecture
Signed-off-by: dan tan
---
v3:
- removed the function prototypes declaration
- fixed code format to comply with convention
- changed function names
Implement support for TPM via SPI interface. The SPI bus master
is provided by PowerNV SPI device which is an SSI peripheral.
It can uses the tpm_emulator driver backend with the external
swtpm.
Signed-off-by: dan tan
---
v3:
- moved variable tis_addr from TPMStateSPI struct to local
- added
The addition to ppc/Kconfig is for building this into the
qemu-system-ppc64 binary. The enablement requires the
following command line argument:
-device tpm-tis-spi,tpmdev=tpm0,bus=pnv-spi-bus.4
Signed-off-by: dan tan
---
hw/ppc/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw
Hi Stefan,
What's the best way to catch these in my own local testing without
submitting it to Travis CI?
thank you,
---
dan tan
power simulation
phone:+1.7373.099.138
email:dan...@linux.ibm.com
On 2024-11-04 09:20, Stefan Berger wrote:
On 11/4/24 1:43 AM, dan tan wrote:
Add qtest
On 2024-11-04 09:14, Stefan Berger wrote:
On 11/4/24 1:43 AM, dan tan wrote:
Implement support for TPM via SPI interface. The SPI bus master
is provided by PowerNV SPI device which is an SSI peripheral.
It can uses the tpm_emulator driver backend with the external
swtpm.
Although the
umentation support (tpm.rst);
- beefed up the unit test exercising major supported locality
functionality
dan tan (3):
tpm/tpm_tis_spi: Support TPM for SPI (Serial Peripheral Interface)
tpm/tpm_tis_spi: activation for the PowerNV machines
tests/qtest/tpm: add unit test to tis-s
supported on the
PowerNV platform, thus, is big endian specific.
Signed-off-by: dan tan
---
v3:
- moved variable tis_addr from TPMStateSPI struct to local
- added the VM suspend/resume support:
- added vmstate_tpm_tis_spi declaration
- added tpm_tis_spi_pre_save() function
- fixed trace formatting
-content/uploads/TCG_PCClientTPMInterfaceSpecification_TIS__1-3_27_03212013.pdf
The SPI registers are specific to the PowerNV platform
architecture
Signed-off-by: dan tan
---
v3:
- removed the function prototypes declaration
- fixed code format to comply with convention
- changed function names
The addition to ppc/Kconfig is for building this into the
qemu-system-ppc64 binary. The enablement requires the
following command line argument:
-device tpm-tis-spi,tpmdev=tpm0,bus=pnv-spi-bus.4
Signed-off-by: dan tan
---
hw/ppc/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw
On 2024-11-02 09:19, Stefan Berger wrote:
On 11/1/24 4:27 PM, dan tan wrote:
Implement support for TPM via SPI interface. The SPI bus master
is provided by PowerNV SPI device which is an SSI peripheral.
It can uses the tpm_emulator driver backend with the external
swtpm.
Although the
The addition to ppc/Kconfig is for building this into the
qemu-system-ppc64 binary. The enablement requires the
following command line argument:
-device tpm-tis-spi,tpmdev=tpm0,bus=pnv-spi-bus.4
Signed-off-by: dan tan
---
hw/ppc/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw
self-
explanatory #defines and adding comments;
- added some documentation support (tpm.rst);
- beefed up the unit test exercising major supported locality
functionality
dan tan (3):
tpm/tpm_tis_spi: Support TPM for SPI (Serial Peripheral Interface)
tpm/tpm_tis_spi: activation fo
- changed function names and variable names to be the same
as the tpm-tis-i2c test.
- change hard coded numbers to #define's with meaningful
names that are identifiable with spec documentation
Signed-off-by: dan tan
---
tests/qtest/tpm-tis-spi-pnv-test.c
formatting string
Signed-off-by: dan tan
---
docs/specs/tpm.rst | 15 ++
include/sysemu/tpm.h | 3 +
hw/tpm/tpm_tis_spi.c | 360 +++
hw/tpm/Kconfig | 6 +
hw/tpm/meson.build | 1 +
hw/tpm/trace-events | 7 +
6 files changed, 392
igned-off-by: dan tan
---
tests/qtest/tpm-tis-spi-pnv-test.c | 220 +++--
tests/qtest/meson.build| 1 +
2 files changed, 116 insertions(+), 105 deletions(-)
diff --git a/tests/qtest/tpm-tis-spi-pnv-test.c
b/tests/qtest/tpm-tis-spi-pnv-test.c
index a3675
The addition to ppc/Kconfig is for building this into the
qemu-system-ppc64 binary. The enablement requires the
following command line argument:
-device tpm-tis-spi,tpmdev=tpm0,bus=pnv-spi-bus.4
Signed-off-by: dan tan
---
hw/ppc/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw
- moved variable tis_addr from TPMStateSPI struct to local
- added the VM suspend/resume support:
- added vmstate_tpm_tis_spi declaration
- added tpm_tis_spi_pre_save() function
- fixed trace formatting string
Signed-off-by: dan tan
---
hw/tpm/tpm_tis_spi.c | 50
://trustedcomputinggroup.org/wp-content/uploads/TCG_PCClientTPMInterfaceSpecification_TIS__1-3_27_03212013.pdf
The SPI registers are specific to the PowerNV platform
architecture
Signed-off-by: dan tan
---
hw/tpm/tpm_tis_spi.c | 2 +-
tests/qtest/tpm-tis-spi-pnv-test.c | 700
supported on the
PowerNV platform, thus, is big endian specific.
Signed-off-by: dan tan
---
docs/specs/tpm.rst | 15 ++
include/sysemu/tpm.h | 3 +
hw/tpm/tpm_tis_spi.c | 328 +++
hw/tpm/Kconfig | 6 +
hw/tpm/meson.build | 1 +
hw/tpm/trace-events
dding comments;
- added some documentation support (tpm.rst);
- beefed up the unit test exercising major supported locality
functionality
dan tan (5):
tpm/tpm_tis_spi: Support TPM for SPI (Serial Peripheral Interface)
tpm/tpm_tis_spi: activation for the PowerNV machines
tests/qtest/tpm
The addition to ppc/Kconfig is for building this into the
qemu-system-ppc64 binary. The enablement requires the
following command line argument:
-device tpm-tis-spi,tpmdev=tpm0,bus=pnv-spi-bus.4
Signed-off-by: dan tan
---
hw/ppc/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw
up the unit test exercising major supported locality
functionality
Tests: 'make check' and 'make check-avocado'
dan tan (3):
tpm/tpm_tis_spi: Support TPM for SPI (Serial Peripheral Interface)
tpm/tpm_tis_spi: activation for the PowerNV machines
tests/qtest/tpm: add
supported on the
PowerNV platform, thus, is big endian specific.
Signed-off-by: dan tan
---
docs/specs/tpm.rst | 15 ++
include/sysemu/tpm.h | 3 +
hw/tpm/tpm_tis_spi.c | 328 +++
hw/tpm/Kconfig | 6 +
hw/tpm/meson.build | 1 +
hw/tpm/trace-events
://trustedcomputinggroup.org/wp-content/uploads/TCG_PCClientTPMInterfaceSpecification_TIS__1-3_27_03212013.pdf
The SPI registers are specific to the PowerNV platform
architecture
Signed-off-by: dan tan
---
tests/qtest/tpm-tis-spi-pnv-test.c | 700 +
tests/qtest/meson.build| 3
Hi Stefan,
Thank you for the review comments! Please see my response below.
thank you,
---
dan tan
power simulation
phone:+1.7373.099.138
email:dan...@linux.ibm.com
On 2024-09-12 13:02, Stefan Berger wrote:
On 9/12/24 12:09 PM, dan tan wrote:
From: dan tan
SPI interface to TPM TIS
Hi Cédric,
Thank you for the review comments. Please see my response below.
thank you,
---
dan tan
power simulation
phone:+1.7373.099.138
email:dan...@linux.ibm.com
On 2024-09-12 12:20, Cédric Le Goater wrote:
Hello Dan,
On 9/12/24 18:09, dan tan wrote:
From: dan tan
SPI interface to TPM
From: dan tan
SPI interface to TPM TIS implementation via swtpm
Signed-off-by: dan tan
---
include/sysemu/tpm.h | 3 +
hw/tpm/tpm_tis_spi.c | 347 +
tests/qtest/pnv-tpm-tis-spi-test.c | 223 ++
hw/ppc/Kconfig
On Thu, 18 Jan 2024 12:27:12 +1000, Nicholas Piggin wrote:
> On Thu Jan 18, 2024 at 8:34 AM AEST, dan tan wrote:
>>The handling of the following two registers are added -
>>DAWR1 (0x0bd, 189) - Data Address Watchpoint 1
>>DAWRX1 (0x0b5
Control Register 3
Signed-off-by: dan tan
---
target/ppc/cpu.h | 4
target/ppc/cpu_init.c | 17 +
2 files changed, 21 insertions(+)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index f8101ff..de0af02 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1933,6
The handling of the following two registers are added -
DAWR1 (0x0bd, 189) - Data Address Watchpoint 1
DAWRX1 (0x0b5, 181) - Data Address Watchpoint Extension 1
Signed-off-by: dan tan
---
target/ppc/cpu.c | 51
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