[PATCH 5/6] target/loongarch: Only flush one TLB entry in helper_invtlb_page_asid_or_g

With function helper_invtlb_page_asid_or_g(), one TLB entry in LoongArch emulated TLB is invalidated. Also invalidate_tlb_entry() can be called so that only one QEMU TLB entry will be flushed. Signed-off-by: Bibo Mao --- target/loongarch/tcg/tlb_helper.c | 2 +- 1 file changed, 1 insertion

[PATCH 3/6] target/loongarch: Use loongarch_tlb_search_cb in helper_invtlb_page_asid_or_g

With function helper_invtlb_page_asid_or_g(), currently it is to search TLB entry one by one. Instead STLB can be searched at first with hash method, and then MTLB. Here common API loongarch_tlb_search_cb() is used in function helper_invtlb_page_asid_or_g(). Signed-off-by: Bibo Mao --- target

[PATCH 6/6] target/loongarch: Only flush one TLB entry in helper_invtlb_page_asid

With function helper_invtlb_page_asid(), one TLB entry in LoongArch emulated TLB is invalidated if found. Also invalidate_tlb_entry() can be called so that only one QEMU TLB entry will be flushed. Signed-off-by: Bibo Mao --- target/loongarch/tcg/tlb_helper.c | 8 ++-- 1 file changed, 6

[PATCH 1/6] target/loongarch: Add tlb search callback in loongarch_tlb_search()

With function loongarch_tlb_search(), it is to search TLB entry with speficied virtual address, the difference is selection with asid and global bit. Here add callback with selection with asid and global bit. Signed-off-by: Bibo Mao --- target/loongarch/tcg/tlb_helper.c | 19

[PATCH 2/6] target/loongarch: Add common API loongarch_tlb_search_cb()

Common API loongarch_tlb_search_cb() is added here to search TLB entry with specified address. Signed-off-by: Bibo Mao --- target/loongarch/tcg/tlb_helper.c | 19 ++- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/target/loongarch/tcg/tlb_helper.c b/target

[PATCH 0/6] target/loongarch: MMU enhancement about TLB search

. Also there is optimization with qemu TLB flush, invalidate_tlb_entry() is used to flush one TLB entry rather than flush all TLB entries. This patchset is based on patch sent at https://lore.kernel.org/qemu-devel/20250730030202.3425934-1-maob...@loongson.cn/ Bibo Mao (6): target/loongarch

[PATCH 4/6] target/loongarch: Use loongarch_tlb_search_cb in helper_invtlb_page_asid

With function helper_invtlb_page_asid(), currently it is to search TLB entry one by one. Instead STLB can be searched at first with hash method, and then MTLB. Here common API loongarch_tlb_search_cb() is used in function helper_invtlb_page_asid() Signed-off-by: Bibo Mao --- target/loongarch

Re: [PATCH] hw/intc/loongarch_pch_pic: Fix ubsan warning and endianness issue

RY ... PCH_PIC_ROUTE_ENTRY_END: -ptemp = (uint64_t *)(s->route_entry + addr - PCH_PIC_ROUTE_ENTRY); -*ptemp = (*ptemp & ~mask) | data; +ptemp = (uint64_t *)&s->route_entry[addr - PCH_PIC_ROUTE_ENTRY]; +stq_le_p(ptemp, (ldq_le_p(ptemp) & ~mask) | data); break; default: qemu_log_mask(LOG_GUEST_ERROR, Reviewed-by: Bibo Mao

[PATCH v4 18/19] target/loongarch: Reduce TLB flush with helper_tlbwr

skipped if both are the same or newly added. Signed-off-by: Bibo Mao --- target/loongarch/tcg/tlb_helper.c | 33 ++- 1 file changed, 28 insertions(+), 5 deletions(-) diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c index 888a008944

[PATCH v4 19/19] target/loongarch: Update TLB index selection method

be selected secondly 3. random method is used by last. Signed-off-by: Bibo Mao --- target/loongarch/tcg/tlb_helper.c | 49 ++- 1 file changed, 42 insertions(+), 7 deletions(-) diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c index

[PATCH v4 17/19] target/loongarch: Add parameter tlb pointer with fill_tlb_entry

With function fill_tlb_entry(), it will update LoongArch emulated TLB information. Here parameter tlb pointer is added so that TLB entry will be updated based on relative TLB CSR registers. Signed-off-by: Bibo Mao Reviewed-by: Richard Henderson --- target/loongarch/tcg/tlb_helper.c | 7

[PATCH v4 16/19] target/loongarch: Use mmu idx bitmap method when flush tlb

added to flush tlb. Signed-off-by: Bibo Mao --- target/loongarch/tcg/tlb_helper.c | 13 +++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c index cf661aaeff..da2618ec62 100644 --- a/target/loongarch/tcg

[PATCH v4 15/19] target/loongarch: Use correct address when flush tlb

With tlb_flush_range_by_mmuidx(), the virtual address is 64 bit. However on LoongArch TLB emulation system, virtual address is 48 bit. It is necessary to signed-extend 48 bit address to 64 bit when flush tlb, also fix address calculation issue with odd page. Signed-off-by: Bibo Mao --- target

[PATCH v4 14/19] target/loongarch: Track user space address accessed in kernel mode

. Here field KM is added in LoongArch TLB entry to track whether the lo0/lo1 pte entry is accessed in kernel mode. If set, when LoongArch TLB is flushed, need flush QEMU TLB with mmu idx MMU_KERNEL_IDX. Signed-off-by: Bibo Mao --- target/loongarch/cpu-mmu.h| 2 ++ target/loongarch/cpu.h

[PATCH v4 13/19] target/loongarch: Use MMUContext in get_physical_address()

With function get_physical_address(), parameter MMUContext is added and remove parameter address, prot and address. Signed-off-by: Bibo Mao --- target/loongarch/cpu-mmu.h| 3 +-- target/loongarch/cpu_helper.c | 32 --- target/loongarch/tcg/tlb_helper.c

[PATCH v4 07/19] target/loongarch: Use MMUAccessType in loongarch_map_tlb_entry()

Enum type MMUAccessType is used in function loongarch_map_tlb_entry() rather than int type, and keep consistent with its caller function. Signed-off-by: Bibo Mao --- target/loongarch/tcg/tlb_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/loongarch/tcg

[PATCH v4 10/19] target/loongarch: Use MMUConext in loongarch_map_tlb_entry()

With function loongarch_map_tlb_entry(), parameter MMUConext is added and remove parameter physical, prot and address. Signed-off-by: Bibo Mao --- target/loongarch/tcg/tlb_helper.c | 33 +++ 1 file changed, 16 insertions(+), 17 deletions(-) diff --git a/target

[PATCH v4 08/19] target/loongarch: Add common function loongarch_check_pte()

Common function loongarch_check_pte() is to check tlb entry, return the physical address and access priviledge if found. Also it can be used with page table entry, which is used in page table walker. Signed-off-by: Bibo Mao --- target/loongarch/cpu-mmu.h| 10 + target/loongarch

[PATCH v4 12/19] target/loongarch: Use MMUContext in loongarch_map_address()

With function loongarch_map_address(), parameter MMUContext is added and remove parameter address, prot and address. Signed-off-by: Bibo Mao --- target/loongarch/cpu_helper.c | 32 ++-- 1 file changed, 14 insertions(+), 18 deletions(-) diff --git a/target/loongarch

[PATCH v4 02/19] target/loongarch: Define function loongarch_cpu_post_init as static

-by: Bibo Mao Reviewed-by: Richard Henderson --- target/loongarch/cpu.c | 180 - target/loongarch/cpu.h | 2 - 2 files changed, 90 insertions(+), 92 deletions(-) diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index abad84c054..b96429ffb1

[PATCH v4 04/19] target/loongarch: Add header file cpu-mmu.h

New header file cpu-mmu.h is added and move mmu relative function declaration to this file. Signed-off-by: Bibo Mao Reviewed-by: Richard Henderson --- target/loongarch/cpu-mmu.h| 30 ++ target/loongarch/cpu.c| 1 + target/loongarch/cpu_helper.c

[PATCH v4 00/19] target/loongarch: Enhancement about tcg mmu

fine-grained tlb flush method 3. Fix some issues in function invalidate_tlb_entry() to flush tlb, such as bitmap method with mmu idx, page size and address calculation --- --- Bibo Mao (19): target/loongarch: Move some function definition to kvm directory target/loongarch: Define

[PATCH v4 01/19] target/loongarch: Move some function definition to kvm directory

Move function definition specified with kvm to the corresponding directory. Also remove header file "cpu.h" including outside of macro QEMU_KVM_LOONGARCH_H. Signed-off-by: Bibo Mao Reviewed-by: Richard Henderson --- hw/loongarch/virt.c | 1 + target/loong

[PATCH v4 05/19] target/loongarch: Add enum type TLBRet definition

There is mixed usage between enum variable TLBRET_xxx and int type, here add enum type TLBRet definition and replace int type variable with enum type TLBRet in some functions. Signed-off-by: Bibo Mao --- target/loongarch/cpu-mmu.h | 27 ++- target/loongarch

[PATCH v4 11/19] target/loongarch: Use MMUContext in loongarch_get_addr_from_tlb

With function loongarch_get_addr_from_tlb(), parameter MMUContext is added and remove parameter physical, prot and address. Signed-off-by: Bibo Mao --- target/loongarch/cpu_helper.c| 7 +-- target/loongarch/tcg/tcg_loongarch.h | 4 ++-- target/loongarch/tcg/tlb_helper.c| 18

[PATCH v4 09/19] target/loongarch: Use loongarch_check_pte in loongarch_page_table_walker

Function loongarch_check_pte() can get physical address and access priviledge, it works on both TLB entry and pte entry. It can be used in function loongarch_page_table_walker() also. Signed-off-by: Bibo Mao Reviewed-by: Richard Henderson --- target/loongarch/cpu_helper.c | 42

[PATCH v4 06/19] target/loongarch: Use vaddr in get_physical_address()

Replace target_ulong type with vaddr in function get_physical_address() and the same with its calling functions. Signed-off-by: Bibo Mao --- target/loongarch/cpu-mmu.h| 2 +- target/loongarch/cpu_helper.c | 9 - target/loongarch/tcg/tlb_helper.c | 11 ++- 3 files

[PATCH v4 03/19] target/loongarch: Set page size in TLB entry with STLB

entries, even with STLB. It is convenient with TLB maintainance operation. Signed-off-by: Bibo Mao --- target/loongarch/tcg/tlb_helper.c | 41 --- 1 file changed, 10 insertions(+), 31 deletions(-) diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg

Re: [PATCH v3 13/17] target/loongarch: Use correct address when flush tlb

On 2025/7/28 下午1:09, Richard Henderson wrote: On 7/27/25 17:22, Bibo Mao wrote: +static inline target_ulong __vaddr(target_ulong addr) +{ +    target_ulong high; + +    high = -(addr >> (TARGET_VIRT_ADDR_SPACE_BITS - 1)); +    return addr + (high << TARGET_VIRT_ADDR_SPACE_BITS)

Re: [PATCH] hw/intc/loongarch_ipi: Fix start fail with smp cpu < smp maxcpus on KVM

amp;core->buf[2], write); -attr = (cpu << 16) | CORE_BUF_30; +attr = (cpu_index << 16) | CORE_BUF_30; kvm_ipi_access_reg(fd, attr, &core->buf[4], write); - attr = (cpu << 16) | CORE_BUF_38; +attr = (cpu_index << 16) | CORE_BUF_38; kvm_ipi_access_reg(fd, attr, &core->buf[6], write); } } Reviewed-by: Bibo Mao

Re: [PATCH v3 13/17] target/loongarch: Use correct address when flush tlb

On 2025/7/26 上午9:45, Richard Henderson wrote: On 7/24/25 15:37, Bibo Mao wrote: With tlb_flush_range_by_mmuidx(), the virtual address is 64 bit. However on LoongArch TLB emulation system, virtual address is 48 bit. It is necessary to convert 48 bit address to 64 bit when flush tlb, also fix

Re: [PATCH v3 05/17] target/loongarch: Add common function loongarch_check_pte()

On 2025/7/26 上午9:19, Richard Henderson wrote: On 7/24/25 15:37, Bibo Mao wrote: Common function loongarch_check_pte() is to check tlb entry, return the physical address and access priviledge. Also it can be used with page table entry, which is used in page table walker. Signed-off-by: Bibo

Re: [PATCH v3 07/17] target/loongarch: Add parameter mmu_context with loongarch_page_table_walker

On 2025/7/26 上午9:31, Richard Henderson wrote: On 7/24/25 15:37, Bibo Mao wrote: @@ -191,8 +187,7 @@ static int loongarch_map_address(CPULoongArchState *env, hwaddr *physical,    * legal mapping, even if the mapping is not yet in TLB. return 0 if    * there is a valid map

Re: [PATCH v3 04/17] target/loongarch: Add header file cpu-mmu.h

On 2025/7/26 上午9:16, Richard Henderson wrote: On 7/24/25 15:37, Bibo Mao wrote: +enum { +    TLBRET_MATCH = 0, +    TLBRET_BADADDR = 1, +    TLBRET_NOMATCH = 2, +    TLBRET_INVALID = 3, +    TLBRET_DIRTY = 4, +    TLBRET_RI = 5, +    TLBRET_XI = 6, +    TLBRET_PE = 7, +}; For a follow-up

Re: [PATCH v6] target/loongarch: Guard 64-bit-only insn translation with TRANS64 macro

*ctx, arg_##NAME * a) \ +{ return avail_64(ctx) && avail_##AVAIL(ctx) && FUNC(ctx, a, __VA_ARGS__); } + #define avail_ALL(C) true #define avail_64(C)(FIELD_EX32((C)->cpucfg1, CPUCFG1, ARCH) == \ CPUCFG1_ARCH_LA64) Reviewed-by: Bibo Mao

Re: [PATCH v5] target/loongarch: Guard 64-bit-only insn translation with TRANS64 macro

hardware with LSX/LASX comes out. BTW do you think when the 32-bit hardware with LSX/LASX will come out? one year later or two years... Regards Bibo Mao On 2025/7/24 下午3:20, WANG Rui wrote: This patch replaces uses of the generic TRANS macro with TRANS64 for instructions that are only valid when

[PATCH v3 17/17] target/loongarch: Update TLB index selection method

other ASID can be selected secondly 3. random method is used by last. Signed-off-by: Bibo Mao --- target/loongarch/tcg/tlb_helper.c | 50 ++- 1 file changed, 42 insertions(+), 8 deletions(-) diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg

[PATCH v3 16/17] target/loongarch: Reduce TLB flush with helper_tlbwr

skipped if both are the same or newly added. Signed-off-by: Bibo Mao --- target/loongarch/tcg/tlb_helper.c | 36 ++- 1 file changed, 31 insertions(+), 5 deletions(-) diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c index 1ed2471e0a

[PATCH v3 15/17] target/loongarch: Add parameter tlb pointer with fill_tlb_entry

With function fill_tlb_entry(), it will update LoongArch emulated TLB information. Here parameter tlb pointer is added so that TLB entry will be updated based on relative TLB CSR registers. Signed-off-by: Bibo Mao --- target/loongarch/tcg/tlb_helper.c | 7 +++ 1 file changed, 3 insertions

[PATCH v3 00/17] target/loongarch: Enhancement about tcg mmu

calculation --- Bibo Mao (17): target/loongarch: Move some function definition to kvm directory target/loongarch: Define function loongarch_cpu_post_init as static target/loongarch: Set page size in TLB misc with STLB target/loongarch: Add header file cpu-mmu.h target/loongarch: Add common

[PATCH v3 06/17] target/loongarch: Use loongarch_check_pte() with page table walking

Function loongarch_check_pte() can get physical address and access priviledge, it works on both TLB entry and pte entry. It can be used at page table walking. Signed-off-by: Bibo Mao --- target/loongarch/cpu_helper.c | 38 +-- 1 file changed, 14 insertions(+), 24

[PATCH v3 02/17] target/loongarch: Define function loongarch_cpu_post_init as static

-by: Bibo Mao --- target/loongarch/cpu.c | 180 - target/loongarch/cpu.h | 2 - 2 files changed, 90 insertions(+), 92 deletions(-) diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index abad84c054..b96429ffb1 100644 --- a/target/loongarch

[PATCH v3 12/17] target/loongarch: Track user mode address accessed in kernel mode

. Here field KM is added in TLB MISC to track whether the lo0/lo1 pte entry is accessed in kernel mode. If set, when LoongArch TLB is flushed, need flush QEMU TLB with mmu idx MMU_KERNEL_IDX. Signed-off-by: Bibo Mao --- target/loongarch/cpu-mmu.h| 2 ++ target/loongarch/cpu.h

[PATCH v3 13/17] target/loongarch: Use correct address when flush tlb

With tlb_flush_range_by_mmuidx(), the virtual address is 64 bit. However on LoongArch TLB emulation system, virtual address is 48 bit. It is necessary to convert 48 bit address to 64 bit when flush tlb, also fix address calculation issue with odd page. Signed-off-by: Bibo Mao --- target

[PATCH v3 04/17] target/loongarch: Add header file cpu-mmu.h

New header file cpu-mmu.h is added and move mmu relative function declaration to this file. Signed-off-by: Bibo Mao --- target/loongarch/cpu-mmu.h| 30 ++ target/loongarch/cpu.c| 1 + target/loongarch/cpu_helper.c | 1 + target/loongarch

[PATCH v3 14/17] target/loongarch: Use mmu idx bitmap method when flush tlb

should be added to flush tlb. Signed-off-by: Bibo Mao --- target/loongarch/tcg/tlb_helper.c | 19 +-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c index 61cc19610e..d18b382e56 100644 --- a/target

[PATCH v3 08/17] target/loongarch: Add parameter mmu_context with loongarch_map_tlb_entry

With function loongarch_map_tlb_entry(), parameter mmu_context is added and remove parameter physical and prot. Signed-off-by: Bibo Mao --- target/loongarch/tcg/tlb_helper.c | 31 +++ 1 file changed, 15 insertions(+), 16 deletions(-) diff --git a/target/loongarch

[PATCH v3 09/17] target/loongarch: Add parameter mmu_context with loongarch_get_addr_from_tlb

With function loongarch_get_addr_from_tlb(), parameter mmu_context is added and remove parameter physical and prot. Signed-off-by: Bibo Mao --- target/loongarch/cpu_helper.c| 7 +-- target/loongarch/tcg/tcg_loongarch.h | 4 ++-- target/loongarch/tcg/tlb_helper.c| 16

[PATCH v3 07/17] target/loongarch: Add parameter mmu_context with loongarch_page_table_walker

With function loongarch_page_table_walker(), some output parameters such as physical address and prot can be moved to structure mmu_context. Signed-off-by: Bibo Mao --- target/loongarch/cpu_helper.c | 27 +++ 1 file changed, 11 insertions(+), 16 deletions(-) diff --git

[PATCH v3 11/17] target/loongarch: Add parameter mmu_context with get_physical_address

With function get_physical_address(), parameter mmu_context is added and remove parameter address, prot and address. Signed-off-by: Bibo Mao --- target/loongarch/cpu-mmu.h| 3 +-- target/loongarch/cpu_helper.c | 31 --- target/loongarch/tcg/tlb_helper.c

[PATCH v3 05/17] target/loongarch: Add common function loongarch_check_pte()

Common function loongarch_check_pte() is to check tlb entry, return the physical address and access priviledge. Also it can be used with page table entry, which is used in page table walker. Signed-off-by: Bibo Mao --- target/loongarch/cpu-mmu.h| 10 + target/loongarch/cpu_helper.c

[PATCH v3 01/17] target/loongarch: Move some function definition to kvm directory

Move function definition specified with kvm to the corresponding directory. Also remove header file "cpu.h" including outside of macro QEMU_KVM_LOONGARCH_H. Signed-off-by: Bibo Mao --- hw/loongarch/virt.c | 1 + target/loongarch/cpu.h | 9 ---

[PATCH v3 03/17] target/loongarch: Set page size in TLB misc with STLB

entries, even with STLB, it is convenient with TLB maintainance operation. Signed-off-by: Bibo Mao --- target/loongarch/tcg/tlb_helper.c | 41 --- 1 file changed, 10 insertions(+), 31 deletions(-) diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg

[PATCH v3 10/17] target/loongarch: Add parameter mmu_context with loongarch_map_address

With function loongarch_map_address(), parameter mmu_context is added and remove parameter address, prot and address. Signed-off-by: Bibo Mao --- target/loongarch/cpu_helper.c | 24 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/target/loongarch

Re: [PATCH 1/1] hw/intc/loongarch_ipi: use physical CPU ID for kvm_ipi_access_regs

e since cpu is used in loop sentence already? for (cpu = 0; cpu < ipi->num_cpu; cpu++) Here modification with cpu will change loop sentence flow. Or direct use attr = (core->cpu->cpu_index << 16) | CORE_STATUS_OFF; Regards Bibo Mao + attr = (cpu << 16) | CO

[PATCH v2 4/9] target/loongarch: Add header file cpu-mmu.h

New header file cpu-mmu.h is added and move mmu relative function declaration to this file. Signed-off-by: Bibo Mao --- target/loongarch/cpu-mmu.h| 30 ++ target/loongarch/cpu.c| 1 + target/loongarch/cpu_helper.c | 1 + target/loongarch

[PATCH v2 6/9] target/loongarch: Use loongarch_check_pte() with page table walking

Function loongarch_check_pte() can get physical address and access priviledge, it works on both TLB entry and pte entry. It can be used at page table walking. Signed-off-by: Bibo Mao --- target/loongarch/cpu_helper.c | 35 ++- 1 file changed, 10 insertions(+), 25

[PATCH v2 8/9] target/loongarch: Use correct page size when flush tlb

On LoongArch system, there are two pages with one TLB entry. If the whole TLB entry is flushed, two pages will be flushed. Otherwise if tlb is flushed one by one, page size is one page at a time. Also virtual address of odd page is fixed here. Signed-off-by: Bibo Mao --- target/loongarch/tcg

[PATCH v2 9/9] target/loongarch: Use fine-grained tlb flush method

Qemu TCG provides some tlb flushing API, tlb can be flushed with specified mmu idx and virtual address. Here fine-grained tlb flush method is used. Signed-off-by: Bibo Mao --- target/loongarch/tcg/tlb_helper.c | 19 +++ 1 file changed, 15 insertions(+), 4 deletions(-) diff

[PATCH v2 7/9] target/loongarch: Use mmu idx bitmap method when flush tlb

With API tlb_flush_range_by_mmuidx(), bitmap method of mmu idx should be used rather than itself. Also mmu idx comes from page table entry information rather current running mode. With page table entry, global bit for MMU_KERNEL_IDX, otherwise it is MMU_USER_IDX. Signed-off-by: Bibo Mao

[PATCH v2 2/9] target/loongarch: Define function loongarch_cpu_post_init as static

-by: Bibo Mao --- target/loongarch/cpu.c | 180 - target/loongarch/cpu.h | 2 - 2 files changed, 90 insertions(+), 92 deletions(-) diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index abad84c054..b96429ffb1 100644 --- a/target/loongarch

[PATCH v2 0/9] target/loongarch: Enhancement about tcg mmu

bitmap method with mmu idx, page size and address calculation --- Bibo Mao (9): target/loongarch: Move some function definition to kvm directory target/loongarch: Define function loongarch_cpu_post_init as static target/loongarch: Set page size in TLB misc with STLB target/loongarch: Add

[PATCH v2 1/9] target/loongarch: Move some function definition to kvm directory

Move function definition specified with kvm to the corresponding directory. Also remove header file "cpu.h" including outside of macro QEMU_KVM_LOONGARCH_H. Signed-off-by: Bibo Mao --- hw/loongarch/virt.c | 1 + target/loongarch/cpu.h | 9 ---

[PATCH v2 3/9] target/loongarch: Set page size in TLB misc with STLB

entries, even with STLB, it is convenient with TLB maintainance operation. Signed-off-by: Bibo Mao --- target/loongarch/tcg/tlb_helper.c | 41 --- 1 file changed, 10 insertions(+), 31 deletions(-) diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg

[PATCH v2 5/9] target/loongarch: Add common function loongarch_check_pte()

Common function loongarch_check_pte() is to check tlb entry, return the physical address and access priviledge. Also it can be used with page table entry, which is used in page table walker. Signed-off-by: Bibo Mao --- target/loongarch/cpu-mmu.h| 8 target/loongarch/cpu_helper.c

Re: [PATCH v5 02/11] hw/loongarch: add virt feature avecintc support

l be better if tcg_enabled() is used here, since CONFIG_TCG and CONFIG_KVM is enabled by default. It should be supported in KVM mode now. It is suggested in V4 review process :) Regards Bibo Mao +object_class_property_add(oc, "avecintc", "OnOffAuto", +

Re: [PATCH v5 09/11] target/loongarch: CPU enable msg interrupts.

inal sentence work? env->CSR_ESTAT = deposit64(env->CSR_ESTAT, irq, 1, level != 0); This piece of code is a little strange. Regards Bibo Mao +} else { +env->CSR_ESTAT = deposit64(env->CSR_ESTAT, irq, 1, level != 0); +} if (FIELD_EX64

Re: [PATCH v5 07/11] hw/loongarch: Implement avec controller imput and output pins

range to declare new variable between sentences, I think it should be put in the beginning of function. Regards Bibo Mao +for (int cpu = 0; cpu < ms->smp.cpus; cpu++) { +cpu_state = qemu_get_cpu(cpu); +cpudev = DEVICE(cpu_state); +

Re: [PATCH v5 08/11] hw/loongarch: Implement avec set irq

GARCH_AVEC(opaque); +uint64_t msg_addr = addr + VIRT_AVEC_BASE; +cpu_num = FIELD_EX64(msg_addr, MSG_ADDR, CPU_NUM); Here is physical cpuid rather than logic cpu index. We need convert physical cpuid to logic cpu index. Regards Bibo Mao +irq_num = FIELD_EX64(msg_addr, MSG_ADDR, IRQ_NUM

Re: [PATCH v5 05/11] target/loongarch: add msg interrupt CSR registers

VMSTATE_UINT64_ARRAY(env.CSR_MSGIS, LoongArchCPU, 4), ditto, it will be better if there is macro replaced with 4. Regards Bibo Mao +VMSTATE_UINT64(env.CSR_MSGIR, LoongArchCPU), +VMSTATE_UINT64(env.CSR_MSGIE, LoongArchCPU), +VMSTATE_END_OF_LIST() +}, +}; + static co

[PATCH] target/loongarch: Fix valid virtual address checking

val; addr = malloc(100); *(int *)addr = 1; addr1 = 0xULL + addr; val = *(int *)addr1; printf("val %d \n", val); } Cc: qemu-sta...@nongnu.org Signed-off-by: Bibo Mao --- target/loongarch/cpu_helper.c | 4 ++-- 1 file changed, 2

[PULL v2 0/4] loongarch-to-apply queue

The following changes since commit df6fe2abf2e990f767ce755d426bc439c7bba336: Merge tag 'pull-target-arm-20250704' of https://gitlab.com/pm215/qemu into staging (2025-07-07 09:22:41 -0400) are available in the Git repository at: https://github.com/bibo-mao/qemu.git tags/pull

[PULL v2 4/4] target/loongarch: Remove unnecessary page size validity checking

unnecessary in tlb entry fill path. Signed-off-by: Bibo Mao Reviewed-by: Song Gao --- target/loongarch/tcg/tlb_helper.c | 27 ++- 1 file changed, 10 insertions(+), 17 deletions(-) diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c index

[PULL v2 1/4] hw/intc/loongarch_extioi: Move unrealize function to common code

Memory about LoongArchExtIOICommonState::cpu is allocated in common code, it had better be freed in common code also. Signed-off-by: Bibo Mao Reviewed-by: Song Gao --- hw/intc/loongarch_extioi.c| 9 - hw/intc/loongarch_extioi_common.c | 9 + include/hw

[PULL v2 3/4] target/loongarch: Fix CSR STLBPS register write emulation

Function helper_csrwr_stlbps() is emulation with CSR STLBPS register write operation. However there is only parameter checking action, and no register updating action. Here update value of CSR_STLBPS when parameter passes to check. Signed-off-by: Bibo Mao Reviewed-by: Song Gao --- target

[PULL v2 2/4] target/loongarch: Correct spelling in helper_csrwr_pwcl()

There is small typo issue in function helper_csrwr_pwcl(), this patch corrects this issue. Signed-off-by: Bibo Mao Reviewed-by: Song Gao --- target/loongarch/tcg/csr_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/loongarch/tcg/csr_helper.c b/target

Re: [PULL 0/4] loongarch-to-apply queue

On 2025/7/10 下午8:43, Stefan Hajnoczi wrote: On Thu, Jul 10, 2025 at 5:34 AM Bibo Mao wrote: The following changes since commit df6fe2abf2e990f767ce755d426bc439c7bba336: Merge tag 'pull-target-arm-20250704' of https://gitlab.com/pm215/qemu into staging (2025-07-07 09:22:41 -

[PULL 3/4] target/loongarch: Fix CSR STLBPS register write emulation

Function helper_csrwr_stlbps() is emulation with CSR STLBPS register write operation. However there is only parameter checking action, and no register updating action. Here update value of CSR_STLBPS when parameter passes to check. Signed-off-by: Bibo Mao Reviewed-by: Song Gao --- target

[PULL 0/4] loongarch-to-apply queue

The following changes since commit df6fe2abf2e990f767ce755d426bc439c7bba336: Merge tag 'pull-target-arm-20250704' of https://gitlab.com/pm215/qemu into staging (2025-07-07 09:22:41 -0400) are available in the Git repository at: https://github.com/bibo-mao/qemu.git tags/pull

[PULL 4/4] target/loongarch: Remove unnecessary page size validity checking

unnecessary in tlb entry fill path. Signed-off-by: Bibo Mao Reviewed-by: Song Gao --- target/loongarch/tcg/tlb_helper.c | 24 1 file changed, 8 insertions(+), 16 deletions(-) diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c index dc48b0f4d2

[PULL 1/4] hw/intc/loongarch_extioi: Move unrealize function to common code

Memory about LoongArchExtIOICommonState::cpu is allocated in common code, it had better be freed in common code also. Signed-off-by: Bibo Mao Reviewed-by: Song Gao --- hw/intc/loongarch_extioi.c| 9 - hw/intc/loongarch_extioi_common.c | 9 + include/hw

[PULL 2/4] target/loongarch: Correct spelling in helper_csrwr_pwcl()

There is small typo issue in function helper_csrwr_pwcl(), this patch corrects this issue. Signed-off-by: Bibo Mao Reviewed-by: Song Gao --- target/loongarch/tcg/csr_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/loongarch/tcg/csr_helper.c b/target

Re: [PATCH v4 10/11] target/loongarch:Implement csrrd CSR_MSGIR register

irq = -1; How about irq = BIT(31), the other bits keeps zero except bit 31? Regards Bibo Mao +} + +return irq; +} + target_ulong helper_csrwr_estat(CPULoongArchState *env, target_ulong val) { int64_t old_v = env->CSR_ESTAT; diff --git a/target/loongarch/tcg/helper.h b/targe

Re: [PATCH v4 09/11] target/loongarch: CPU enable msg interrupts.

+} + if (kvm_enabled()) { kvm_loongarch_set_interrupt(cpu, irq, level); } else if (tcg_enabled()) { modification estat should be put here. Regards Bibo Mao

Re: [PATCH v4 08/11] hw/loongarch: Implement avec set irq

num / 64]); +qemu_set_irq(s->cpu[cpu_num].parent_irq, 1); +} +qemu_set_irq(s->cpu[cpu_num].parent_irq, level); There is double function call with qemu_set_irq(). Regards Bibo Mao +} + static void loongarch_avec_mem_write(void *opaque, hwaddr addr,

Re: [PATCH v4 03/11] hw/loongarch: add misc register supoort avecintc

be renamed as virt_has_avecintc()? Regards Bibo Mao +ret |= BIT(IOCSRF_AVEC); +} if (kvm_enabled()) { ret |= BIT(IOCSRF_VM); } @@ -624,6 +631,10 @@ static MemTxResult virt_iocsr_misc_read(void *opaque, hwaddr addr, if (

Re: [PATCH v4 02/11] hw/loongarch: add virt feature avecintc support

re & BIT(IOCSRF_AVEC))) { +return false; +} There had better be one empty line, however it is up to you since I am not good at coding style. Regards Bibo Mao +return true; +} + static inline bool virt_is_veiointc_enabled(LoongArchVirtMachineState *lvms) { if (lvms->veiointc == ON_OFF_AUTO_OFF) {

Re: [PATCH v4 01/11] target/loongarch: move some machine dfine to virt.h

e, %s/dfine/define/ "move some machine dfine to virt.h" otherwise look good to me. Reviewed-by: Bibo Mao

[PATCH 2/6] target/loongarch: Define function loongarch_cpu_post_init as static

-by: Bibo Mao --- target/loongarch/cpu.c | 180 - target/loongarch/cpu.h | 2 - 2 files changed, 90 insertions(+), 92 deletions(-) diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index abad84c054..b96429ffb1 100644 --- a/target/loongarch

[PATCH 3/6] target/loongarch: Set page size in TLB misc with STLB

entries, even with STLB, it is convenient with TLB maintainance operation. Signed-off-by: Bibo Mao --- target/loongarch/tcg/tlb_helper.c | 41 --- 1 file changed, 10 insertions(+), 31 deletions(-) diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg

[PATCH 4/6] target/loongarch: Add header file cpu-mmu.h

New header file cpu-mmu.h is added and move mmu relative function declaration to this file. Signed-off-by: Bibo Mao --- target/loongarch/cpu-mmu.h| 30 ++ target/loongarch/cpu.c| 1 + target/loongarch/cpu_helper.c | 1 + target/loongarch

[PATCH 6/6] target/loongarch: Use loongarch_check_pte() with page table walking

Function loongarch_check_pte() can get physical address and access priviledge, it works on both TLB entry and pte entry. It can be used at page table walking. Signed-off-by: Bibo Mao --- target/loongarch/cpu_helper.c | 35 ++- 1 file changed, 10 insertions(+), 25

[PATCH 0/6] target/loongarch: Enhancement about tcg mmu

table walk emluation in future. Bibo Mao (6): target/loongarch: Move some function definition to kvm directory target/loongarch: Define function loongarch_cpu_post_init as static target/loongarch: Set page size in TLB misc with STLB target/loongarch: Add header file cpu-mmu.h target

[PATCH 5/6] target/loongarch: Add common function loongarch_check_pte()

Common function loongarch_check_pte() is to check tlb entry, return the physical address and access priviledge. Also it can be used with page table entry, which is used in page table walker. Signed-off-by: Bibo Mao --- target/loongarch/cpu-mmu.h| 9 + target/loongarch/cpu_helper.c

[PATCH 1/6] target/loongarch: Move some function definition to kvm directory

Move function definition specified with kvm to the corresponding directory. Also remove header file "cpu.h" including outside of macro QEMU_KVM_LOONGARCH_H. Signed-off-by: Bibo Mao --- hw/loongarch/virt.c | 1 + target/loongarch/cpu.h | 9 ---

[PATCH 4/6] target/loongarch: Add header file cpu-mmu.h

New header file cpu-mmu.h is added and move mmu relative function declaration to this file. Signed-off-by: Bibo Mao --- target/loongarch/cpu-mmu.h| 30 ++ target/loongarch/cpu.c| 1 + target/loongarch/cpu_helper.c | 1 + target/loongarch

[PATCH 0/6] target/loongarch: Enhancement about tcg mmu

table walk emluation in future. Bibo Mao (6): target/loongarch: Move some function definition to kvm directory target/loongarch: Define function loongarch_cpu_post_init as static target/loongarch: Set page size in TLB misc with STLB target/loongarch: Add header file cpu-mmu.h target

Re: [PATCH V1 1/2] hw/rtc: Fixed loongson rtc emulation errors

On 2025/7/7 下午2:36, lixianglai wrote: Hi Bibo Mao: On 2025/6/13 上午9:31, Xianglai Li wrote: The expire time is sent to the timer only when the expire Time is greater than 0 or greater than now. Otherwise, the timer will trigger interruption continuously. Timer interrupts are sent using

Re: [PATCH v3 7/9] hw/loongarch: Implement avec set irq

On 2025/7/2 下午3:21, gaosong wrote: 在 2025/7/2 上午11:15, Bibo Mao 写道: On 2025/6/27 上午11:01, Song Gao wrote: Implement avec set irq and update CSR_MSIS and CSR_MSGIR. Signed-off-by: Song Gao ---   hw/intc/loongarch_avec.c | 44 ++--   1 file changed, 42

Re: [PATCH v3 2/9] hw/loongarch: add virt feature avecintc support

On 2025/7/2 下午3:10, gaosong wrote: 在 2025/7/2 上午10:03, Bibo Mao 写道: On 2025/6/27 上午11:01, Song Gao wrote: LoongArchVirtMachinState adds avecintc features, and it use to check whether virt machine support advance interrupt controller and default set avecintc = ON_OFF_AUTO_ON

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