This patch adds set/get msgint CSRs and check msgint feature.
Signed-off-by: Song Gao
---
RFC: this patch need update linux-headers and
the linux kernel kvm support avec(not merged).
linux-headers/asm-loongarch/kvm.h | 1 +
target/loongarch/cpu.h| 1 +
target/loongarch/kvm/kvm.c
From: Huacai Chen
Signed-off-by: Huacai Chen
Reviewed-by:
Message-ID: <20250923143542.2391576-2-chenhua...@kernel.org>
Signed-off-by: Song Gao
---
tests/qtest/bios-tables-test-allowed-diff.h | 4
1 file changed, 4 insertions(+)
diff --git a/tests/qtest/bios-tables-test-allowed-
: <20250929035338.2320419-2-maob...@loongson.cn>
Signed-off-by: Song Gao
---
target/loongarch/cpu.c | 262 +-
target/loongarch/internals.h | 2 +
target/loongarch/tcg/meson.build | 1 +
target/loongarch/tcg/tcg_cpu.c | 266 +++
The following changes since commit 37ad0e48e9fd58b170abbf31c18a994346f62ed7:
Merge tag 'pull-10.2-maintainer-071025-1' of https://gitlab.com/stsquad/qemu
into staging (2025-10-07 08:46:28 -0700)
are available in the Git repository at:
https://github.com/gaosong715/qemu.git tags/pull-loongar
aob...@loongson.cn>
Signed-off-by: Song Gao
---
target/loongarch/cpu.c | 56 --
target/loongarch/tcg/tcg_cpu.c | 56 ++
2 files changed, 56 insertions(+), 56 deletions(-)
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
Add Loongarch direct interrupt controller device base Definition.
Signed-off-by: Song Gao
Reviewed-by: Bibo Mao
Message-ID: <20250916122109.749813-5-gaos...@loongson.cn>
---
hw/intc/Kconfig | 3 ++
hw/intc/loongarch_dintc.c | 68 +
the DINTC use [2fe0-2ff0) Memory.
Signed-off-by: Song Gao
Reviewed-by: Bibo Mao
Message-ID: <20250916122109.749813-7-gaos...@loongson.cn>
---
hw/intc/loongarch_dintc.c | 24 +++
hw/loongarch/virt.c | 38 ++-
incl
include CSR_MSGIS0-3, CSR_MSGIR and CSR_MSGIE.
Reviewed-by: Bibo Mao
Signed-off-by: Song Gao
Message-ID: <20250916122109.749813-6-gaos...@loongson.cn>
---
target/loongarch/cpu-csr.h | 3 +++
target/loongarch/cpu.h | 11 +++
target/loongarch/machine.
Implement th DINTC realize and unrealize.
Signed-off-by: Song Gao
Reviewed-by: Bibo Mao
Message-ID: <20250916122109.749813-8-gaos...@loongson.cn>
---
hw/intc/loongarch_dintc.c | 23 ++-
target/loongarch/cpu.h| 3 ++-
2 files changed, 24 insertions(+), 2 del
dintc feature bit.
Msgint feature is added in LoongArchCPU, and it is used to check
whether th cpu supports the Message-Interrupts and by default set
mesgint with ON_OFF_AUTO_AUTO.
Signed-off-by: Song Gao
Reviewed-by: Bibo Mao
Message-ID: <20250916122109.749813-3-gaos...@loongson.cn>
-
when cpu added, connect dintc irq to cpu INT_DMSI irq pin.
Reviewed-by: Bibo Mao
Signed-off-by: Song Gao
Message-ID: <20250916122109.749813-12-gaos...@loongson.cn>
---
hw/intc/loongarch_dintc.c | 71 +++
hw/loongarch/virt.c | 11 ++
2 files c
Add feature register and misc register for dmsi feature checking and
setting
Signed-off-by: Song Gao
Reviewed-by: Bibo Mao
Message-ID: <20250916122109.749813-4-gaos...@loongson.cn>
---
hw/loongarch/virt.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/hw/loongarch/virt.
implement the read-clear feature for CSR_MSGIR register.
Reviewed-by: Bibo Mao
Signed-off-by: Song Gao
Message-ID: <20250916122109.749813-11-gaos...@loongson.cn>
---
target/loongarch/csr.c| 5 +
target/loongarch/tcg/csr_helper.c
n64 errors.
--------
Song Gao (11):
target/loongarch: move some machine define to virt.h
hw/loongarch: add virt feature dmsi support
hw/loongarch: add misc register support dmsi
loongarch: add a direct interrupt controller device
Add CSR_ESTAT.bit15 and CSR_ECFG.bit15 for DINTC irq.
Reviewed-by: Bibo Mao
Signed-off-by: Song Gao
Message-ID: <20250916122109.749813-10-gaos...@loongson.cn>
---
target/loongarch/cpu-csr.h | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/loongarch/cpu-c
move some machine define to virt.h
Signed-off-by: Song Gao
Reviewed-by: Bibo Mao
Message-ID: <20250916122109.749813-2-gaos...@loongson.cn>
---
include/hw/loongarch/virt.h | 19 +++
target/loongarch/cpu.h | 21 -
2 files changed, 19 insertions(
Implement dintc set irq and update CSR_MSGIS.
Reviewed-by: Bibo Mao
Signed-off-by: Song Gao
Message-ID: <20250916122109.749813-9-gaos...@loongson.cn>
---
hw/intc/loongarch_dintc.c | 32 ++--
1 file changed, 30 insertions(+), 2 deletions(-)
diff --git a/h
when cpu added, connect dintc irq to cpu INT_DMSI irq pin.
Reviewed-by: Bibo Mao
Signed-off-by: Song Gao
Message-ID: <20250916122109.749813-12-gaos...@loongson.cn>
---
hw/intc/loongarch_dintc.c | 71 +++
hw/loongarch/virt.c | 11 ++
2 files c
move some machine define to virt.h
Signed-off-by: Song Gao
Reviewed-by: Bibo Mao
Message-ID: <20250916122109.749813-2-gaos...@loongson.cn>
---
include/hw/loongarch/virt.h | 19 +++
target/loongarch/cpu.h | 21 -
2 files changed, 19 insertions(
Add CSR_ESTAT.bit15 and CSR_ECFG.bit15 for DINTC irq.
Reviewed-by: Bibo Mao
Signed-off-by: Song Gao
Message-ID: <20250916122109.749813-10-gaos...@loongson.cn>
---
target/loongarch/cpu-csr.h | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/loongarch/cpu-c
Add feature register and misc register for dmsi feature checking and
setting
Signed-off-by: Song Gao
Reviewed-by: Bibo Mao
Message-ID: <20250916122109.749813-4-gaos...@loongson.cn>
---
hw/loongarch/virt.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/hw/loongarch/virt.
implement the read-clear feature for CSR_MSGIR register.
Reviewed-by: Bibo Mao
Signed-off-by: Song Gao
Message-ID: <20250916122109.749813-11-gaos...@loongson.cn>
---
target/loongarch/csr.c| 5 +
target/loongarch/tcg/csr_helper.c
dintc feature bit.
Msgint feature is added in LoongArchCPU, and it is used to check
whether th cpu supports the Message-Interrupts and by default set
mesgint with ON_OFF_AUTO_AUTO.
Signed-off-by: Song Gao
Reviewed-by: Bibo Mao
Message-ID: <20250916122109.749813-3-gaos...@loongson.cn>
-
h-20250925
--------
Song Gao (11):
target/loongarch: move some machine define to virt.h
hw/loongarch: add virt feature dmsi support
hw/loongarch: add misc register support dmsi
loongarch: add a direct interrupt controller device
target/loongarch: add msg interrupt CSR
Add Loongarch direct interrupt controller device base Definition.
Signed-off-by: Song Gao
Reviewed-by: Bibo Mao
Message-ID: <20250916122109.749813-5-gaos...@loongson.cn>
---
hw/intc/Kconfig | 3 ++
hw/intc/loongarch_dintc.c | 68 +
Implement th DINTC realize and unrealize.
Signed-off-by: Song Gao
Reviewed-by: Bibo Mao
Message-ID: <20250916122109.749813-8-gaos...@loongson.cn>
---
hw/intc/loongarch_dintc.c | 23 ++-
target/loongarch/cpu.h| 3 ++-
2 files changed, 24 insertions(+), 2 del
Add CSR_ESTAT.bit15 and CSR_ECFG.bit15 for AVEC irq.
Reviewed-by: Bibo Mao
Signed-off-by: Song Gao
---
target/loongarch/cpu-csr.h | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/loongarch/cpu-csr.h b/target/loongarch/cpu-csr.h
index 4792677086..f296eb8d06
Implement dintc set irq and update CSR_MSGIS.
Reviewed-by: Bibo Mao
Signed-off-by: Song Gao
---
hw/intc/loongarch_dintc.c | 32 ++--
1 file changed, 30 insertions(+), 2 deletions(-)
diff --git a/hw/intc/loongarch_dintc.c b/hw/intc/loongarch_dintc.c
index 598c666ec6
ix patch7 get wrong cpu_num and irq_num;
5: Add vmstate_msg for messag-interrupt registers migrate;
6: Update test scripts use '-bios', because kernel use avec need acpi
support. the bios is qemu/pc_bios/edk2-loongarch64-code.fd.bz2.
Thanks.
Song Gao
Song Gao (11):
target/loongarch:
The following changes since commit f0007b7f03e2d7fc33e71c3a582f2364c51a226b:
Merge tag 'pull-target-arm-20250916' of https://gitlab.com/pm215/qemu into
staging (2025-09-17 11:10:55 -0700)
are available in the Git repository at:
https://github.com/gaosong715/qemu.git tags/pull-loongarch-2025
their reset interface registered. And remove
reset interface with CPU unplug callback.
Signed-off-by: Bibo Mao
Reviewed-by: Igor Mammedov
Tested-by: Song Gao
Message-ID: <20250906070200.3749326-4-maob...@loongson.cn>
Signed-off-by: Song Gao
---
hw/loongarch/boot.c | 13 ---
From: Bibo Mao
With BSP core, it boots from aux boot code and loads data into register
A0-A2 and PC. Pre-boot setting is not unnecessary and can be removed.
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
Message-ID: <20250906070200.3749326-3-maob...@loongson.cn>
Signed-off-by: So
. With BSP core, load data to register A0-A2 and PC.
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
Message-ID: <20250906070200.3749326-2-maob...@loongson.cn>
Signed-off-by: Song Gao
---
hw/loongarch/boot.c | 36 ++--
1 file changed, 34 insertions(+), 2 del
Implement th DINTC realize and unrealize.
Signed-off-by: Song Gao
---
hw/intc/loongarch_dintc.c | 23 ++-
target/loongarch/cpu.h| 3 ++-
2 files changed, 24 insertions(+), 2 deletions(-)
diff --git a/hw/intc/loongarch_dintc.c b/hw/intc/loongarch_dintc.c
index
dintc feature bit.
Msgint feature is added in LoongArchCPU, and it is used to check
whether th cpu supports the Message-Interrupts and by default set
mesgint with ON_OFF_AUTO_AUTO.
Signed-off-by: Song Gao
Reviewed-by: Bibo Mao
---
hw/loongarch/virt.c | 50
move some machine define to virt.h
Signed-off-by: Song Gao
Reviewed-by: Bibo Mao
---
include/hw/loongarch/virt.h | 19 +++
target/loongarch/cpu.h | 21 -
2 files changed, 19 insertions(+), 21 deletions(-)
diff --git a/include/hw/loongarch/virt.h b
the DINTC use [2fe0-2ff0) Memory.
Signed-off-by: Song Gao
Reviewed-by: Bibo Mao
---
hw/intc/loongarch_dintc.c | 24 +++
hw/loongarch/virt.c | 38 ++-
include/hw/intc/loongarch_dintc.h | 1 +
include/hw/loongarch/virt.h
Add Loongarch direct interrupt controller device base Definition.
Signed-off-by: Song Gao
Reviewed-by: Bibo Mao
---
hw/intc/Kconfig | 3 ++
hw/intc/loongarch_dintc.c | 68 +++
hw/intc/meson.build | 1 +
hw/loongarch/Kconfig
Add CSR_ESTAT.bit15 and CSR_ECFG.bit15 for DINTC irq.
Reviewed-by: Bibo Mao
Signed-off-by: Song Gao
---
target/loongarch/cpu-csr.h | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/loongarch/cpu-csr.h b/target/loongarch/cpu-csr.h
index 4792677086..f296eb8d06
implement the read-clear feature for CSR_MSGIR register.
Reviewed-by: Bibo Mao
Signed-off-by: Song Gao
---
target/loongarch/csr.c| 5 +
target/loongarch/tcg/csr_helper.c | 21 +++
target/loongarch/tcg/helper.h | 1
include CSR_MSGIS0-3, CSR_MSGIR and CSR_MSGIE.
Reviewed-by: Bibo Mao
Signed-off-by: Song Gao
---
target/loongarch/cpu-csr.h | 3 +++
target/loongarch/cpu.h | 11 +++
target/loongarch/machine.c | 25 +++--
3 files changed, 37 insertions(+), 2 deletions(-)
diff
Add feature register and misc register for dmsi feature checking and
setting
Signed-off-by: Song Gao
Reviewed-by: Bibo Mao
---
hw/loongarch/virt.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index 2f64089eac..cc23e98b3a 100644
when cpu added, connect dintc irq to cpu INT_DMSI irq pin.
Reviewed-by: Bibo Mao
Signed-off-by: Song Gao
---
hw/intc/loongarch_dintc.c | 71 +++
hw/loongarch/virt.c | 9 +
2 files changed, 80 insertions(+)
diff --git a/hw/intc/loongarch_dintc.c b
CSR_MSGIR register
2: Fix some code style;
3: Merge patch8 and patch9 into one patch8;
4: Fix patch7 get wrong cpu_num and irq_num;
5: Add vmstate_msg for messag-interrupt registers migrate;
6: Update test scripts use '-bios', because kernel use avec need acpi
support. the bi
the AVEC controller use [2fe0-2ff00) Memory.
Signed-off-by: Song Gao
Reviewed-by: Bibo Mao
---
hw/intc/loongarch_avec.c | 24
hw/loongarch/virt.c | 39 +++-
include/hw/intc/loongarch_avec.h | 1 +
include/hw
when cpu added, connect avec irq to cpu INT_AVEC irq pin.
Reviewed-by: Bibo Mao
Signed-off-by: Song Gao
---
hw/intc/loongarch_avec.c | 71
hw/loongarch/virt.c | 11 +++
2 files changed, 82 insertions(+)
diff --git a/hw/intc/loongarch_avec.c b
default avec feature bit.
Msegint feature is added in LoongArchCPU, and it is used to check
whether th cpu supports the Message-Interrupts and by default set
mesgint with ON_OFF_AUTO_AUTO.
Signed-off-by: Song Gao
Reviewed-by: Bibo Mao
---
hw/loongarch/virt.c | 32
implement the read-clear feature for CSR_MSGIR register.
Reviewed-by: Bibo Mao
Signed-off-by: Song Gao
---
target/loongarch/csr.c| 5 +
target/loongarch/tcg/csr_helper.c | 21 +++
target/loongarch/tcg/helper.h | 1
Add Loongarch advance interrupt controller device base Definition.
Signed-off-by: Song Gao
Reviewed-by: Bibo Mao
---
hw/intc/Kconfig | 3 ++
hw/intc/loongarch_avec.c | 68
hw/intc/meson.build | 1 +
hw/loongarch/Kconfig
Add feature register and misc register for avecintc feature checking and
setting
Signed-off-by: Song Gao
Reviewed-by: Bibo Mao
---
hw/loongarch/virt.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index 37c38ae63f..0883f3a272 100644
move some machine define to virt.h
Signed-off-by: Song Gao
Reviewed-by: Bibo Mao
---
include/hw/loongarch/virt.h | 19 +++
target/loongarch/cpu.h | 21 -
2 files changed, 19 insertions(+), 21 deletions(-)
diff --git a/include/hw/loongarch/virt.h b
Implement avec set irq and update CSR_MSGIS.
Signed-off-by: Song Gao
---
hw/intc/loongarch_avec.c | 32 ++--
1 file changed, 30 insertions(+), 2 deletions(-)
diff --git a/hw/intc/loongarch_avec.c b/hw/intc/loongarch_avec.c
index 1f9f376898..0c90579de2 100644
--- a
include CSR_MSGIS0-3, CSR_MSGIR and CSR_MSGIE.
Signed-off-by: Song Gao
---
target/loongarch/cpu-csr.h | 3 +++
target/loongarch/cpu.h | 11 +++
target/loongarch/machine.c | 25 +++--
3 files changed, 37 insertions(+), 2 deletions(-)
diff --git a/target
the AVEC controller supports 256*256 irqs input, all the irqs connect CPU
INT_AVEC irq
Signed-off-by: Song Gao
---
hw/intc/loongarch_avec.c | 20
target/loongarch/cpu.h | 3 ++-
2 files changed, 22 insertions(+), 1 deletion(-)
diff --git a/hw/intc/loongarch_avec.c b/hw
the AVEC controller supports 256*256 irqs input, all the irqs connect CPU
INT_AVEC irq
Signed-off-by: Song Gao
---
hw/intc/loongarch_avec.c | 20
hw/loongarch/virt.c | 10 +-
target/loongarch/cpu.h | 3 ++-
3 files changed, 31 insertions(+), 2 deletions
implement the read-clear feature for CSR_MSGIR register.
Signed-off-by: Song Gao
---
target/loongarch/csr.c| 5 +
target/loongarch/tcg/csr_helper.c | 21 +++
target/loongarch/tcg/helper.h | 1 +
.../tcg/insn_trans
move some machine define to virt.h
Signed-off-by: Song Gao
Reviewed-by: Bibo Mao
---
include/hw/loongarch/virt.h | 19 +++
target/loongarch/cpu.h | 21 -
2 files changed, 19 insertions(+), 21 deletions(-)
diff --git a/include/hw/loongarch/virt.h b
7;-bios', because kernel use avec need acpi
support. the bios is qemu/pc_bios/edk2-loongarch64-code.fd.bz2.
Thanks.
Song Gao
Song Gao (11):
target/loongarch: move some machine define to virt.h
hw/loongarch: add virt feature avecintc support
hw/loongarch: add misc register supoort avecintc
Add feature register and misc register for avecintc feature checking and
setting
Signed-off-by: Song Gao
---
hw/loongarch/virt.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index 1a2aa92c25..124f96af03 100644
--- a/hw/loongarch
when cpu added, connect avec irq to cpu INT_AVEC irq pin.
Signed-off-by: Song Gao
---
hw/intc/loongarch_avec.c | 71
hw/loongarch/virt.c | 11 +++
2 files changed, 82 insertions(+)
diff --git a/hw/intc/loongarch_avec.c b/hw/intc
Implement avec set irq and update CSR_MSIS.
Signed-off-by: Song Gao
---
hw/intc/loongarch_avec.c | 58 ++--
include/hw/intc/loongarch_avec.h | 3 ++
2 files changed, 59 insertions(+), 2 deletions(-)
diff --git a/hw/intc/loongarch_avec.c b/hw/intc
the AVEC controller use [2fe0-2ff00) Memory.
Signed-off-by: Song Gao
---
hw/intc/loongarch_avec.c | 24
hw/loongarch/virt.c | 39 +++-
include/hw/intc/loongarch_avec.h | 1 +
include/hw/loongarch/virt.h | 1
include CSR_MSGIS0-3, CSR_MSGIR and CSR_MSGIE.
Signed-off-by: Song Gao
---
target/loongarch/cpu-csr.h | 3 +++
target/loongarch/cpu.h | 11 +++
target/loongarch/machine.c | 27 +--
3 files changed, 39 insertions(+), 2 deletions(-)
diff --git a/target
default avec feature bit.
Signed-off-by: Song Gao
---
hw/loongarch/virt.c | 30 ++
include/hw/loongarch/virt.h | 14 ++
2 files changed, 44 insertions(+)
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index b15ada2078..1a2aa92c25 100644
--- a
Add Loongarch advance interrupt controller device base Definition.
Signed-off-by: Song Gao
---
hw/intc/Kconfig | 3 ++
hw/intc/loongarch_avec.c | 68
hw/intc/meson.build | 1 +
hw/loongarch/Kconfig | 1
Add CSR_ESTAT.bit15 and CSR_ECFG.bit15 for AVEC irq.
Signed-off-by: Song Gao
---
target/loongarch/cpu-csr.h | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/loongarch/cpu-csr.h b/target/loongarch/cpu-csr.h
index 4792677086..6ec13d13d1 100644
--- a/target
.
Signed-off-by: WANG Rui
Reviewed-by: Bibo Mao
Reviewed-by: Song Gao
Signed-off-by: Song Gao
---
.../tcg/insn_trans/trans_atomic.c.inc | 36 +--
.../tcg/insn_trans/trans_extra.c.inc | 8 +++--
.../tcg/insn_trans/trans_farith.c.inc | 8 ++---
.../loongarch
The following changes since commit ca18b336e12c8433177a3cd639c5bf757952adaa:
Merge tag 'pull-lu-20250828' of https://gitlab.com/rth7680/qemu into staging
(2025-08-28 09:24:36 +1000)
are available in the Git repository at:
https://github.com/gaosong715/qemu.git tags/pull-loongarch-20250828
nter to write values into an array of 8-bit values.
Thus rework the code to use the stq_le_p / ldq_le_p helpers here
and make sure that we do not create pointers with undefined behavior
by accident.
Signed-off-by: Thomas Huth
Reviewed-by: Bibo Mao
Reviewed-by: Philippe Mathieu-Daudé
Tested-b
vr0, 3328
ret
```
Reported-by: Zhou Qiankang
Signed-off-by: WANG Rui
Reviewed-by: Song Gao
Message-ID: <20250804132212.4816-1-wang...@loongson.cn>
Signed-off-by: Song Gao
---
target/loongarch/tcg/insn_trans/trans_vec.c.inc | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
d
The following changes since commit cd21ee5b27b22ae66c103d36516aa5077881aa3d:
Merge tag 'ui-pull-request' of https://gitlab.com/marcandre.lureau/qemu into
staging (2025-08-07 11:02:50 -0400)
are available in the Git repository at:
https://github.com/gaosong715/qemu.git tags/pull-loongarch-20
, *addr1;
int val;
addr = malloc(100);
*(int *)addr = 1;
addr1 = 0xULL + addr;
val = *(int *)addr1;
printf("val %d \n", val);
}
Cc: qemu-sta...@nongnu.org
Signed-off-by: Bibo Mao
Acked-by: Song Gao
Reviewed-by: Song Gao
0731-for-10.1
Bibo Mao (1):
target/loongarch: Fix valid virtual address checking
Song Gao (1):
hw/intc/loongarch_ipi: Fix start fail with smp cpu < smp maxcpus on KVM
hw/intc/loongarch_ipi_kvm.c | 27 ---
:
qemu-system-loongarch64: KVM_SET_DEVICE_ATTR failed: Group 1073741825 attr
0x0001: Invalid argument
Signed-off-by: Song Gao
Reviewed-by: Bibo Mao
Message-ID: <20250725081213.3867592-1-gaos...@loongson.cn>
---
hw/intc/loongarch_ipi_kvm.c | 27 ---
:
qemu-system-loongarch64: KVM_SET_DEVICE_ATTR failed: Group 1073741825 attr
0x0001: Invalid argument
Signed-off-by: Song Gao
---
hw/intc/loongarch_ipi_kvm.c | 27 ---
1 file changed, 16 insertions(+), 11 deletions(-)
diff --git a/hw/intc/loongarch_ipi_kv
QEMU reboot after inserting no-configuous cpus may start failed
becaue the vcpu context may not have created on KVM, On QEMU side use logical
CPU ID
for kvm_ipi_access_regs and do some check. On KVM use kvm_get_vcpu_by_id() get
vcpu.
Signed-off-by: Song Gao
---
hw/intc/loongarch_ipi_kvm.c
QEMU reboot after inserting no-configuous cpus may start failed
becaue the vcpu context may not have created on KVM, On QEMU side use physical
CPU ID
for kvm_ipi_access_regs and do some check. On KVM use kvm_get_vcpu_by_cpuid get
vcpu.
Signed-off-by: Song Gao
---
hw/intc/loongarch_ipi_kvm.c
when loongarch cpu set irq is INT_AVEC, we need set CSR_ESTAT.MSGINT bit.
Signed-off-by: Song Gao
---
target/loongarch/cpu-csr.h | 6 --
target/loongarch/cpu.c | 10 +-
2 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/target/loongarch/cpu-csr.h b/target/loongarch
Implement avec set irq and update CSR_MSIS.
Signed-off-by: Song Gao
---
hw/intc/loongarch_avec.c | 34 --
1 file changed, 32 insertions(+), 2 deletions(-)
diff --git a/hw/intc/loongarch_avec.c b/hw/intc/loongarch_avec.c
index 1f9f376898..af6c75c4a9 100644
--- a
implement the read-clear feature for CSR_MSGIR register.
Signed-off-by: Song Gao
---
target/loongarch/csr.c| 5 +
target/loongarch/tcg/csr_helper.c | 21 +++
target/loongarch/tcg/helper.h | 1 +
.../tcg/insn_trans
the AVEC controller use [2fe0-2ff00) Memory.
Signed-off-by: Song Gao
---
hw/intc/loongarch_avec.c | 24
hw/loongarch/virt.c | 39 +++-
include/hw/intc/loongarch_avec.h | 1 +
include/hw/loongarch/virt.h | 1
when cpu added, connect avec irq to cpu INT_AVEC irq pin.
Signed-off-by: Song Gao
---
hw/intc/loongarch_avec.c | 71
hw/loongarch/virt.c | 11 +++
2 files changed, 82 insertions(+)
diff --git a/hw/intc/loongarch_avec.c b/hw/intc
include CSR_MSGIS0-3, CSR_MSGIR and CSR_MSGIE.
Signed-off-by: Song Gao
---
target/loongarch/cpu-csr.h | 3 +++
target/loongarch/cpu.h | 10 ++
target/loongarch/machine.c | 27 +--
3 files changed, 38 insertions(+), 2 deletions(-)
diff --git a/target
move some machine define to virt.h
Signed-off-by: Song Gao
Reviewed-by: Bibo Mao
---
include/hw/loongarch/virt.h | 19 +++
target/loongarch/cpu.h | 21 -
2 files changed, 19 insertions(+), 21 deletions(-)
diff --git a/include/hw/loongarch/virt.h b
into one patch8;
4: Fix patch7 get wrong cpu_num and irq_num;
5: Add vmstate_msg for messag-interrupt registers migrate;
6: Update test scripts use '-bios', because kernel use avec need acpi
support. the bios is qemu/pc_bios/edk2-loongarch64-code.fd.bz2.
Thanks.
Song Gao
Song G
Add Loongarch advance interrupt controller device base Definition.
Signed-off-by: Song Gao
---
hw/intc/Kconfig | 3 ++
hw/intc/loongarch_avec.c | 68
hw/intc/meson.build | 1 +
hw/loongarch/Kconfig | 1
the AVEC controller supports 256*256 irqs input, all the irqs connect CPU
INT_AVEC irq
Signed-off-by: Song Gao
---
hw/intc/loongarch_avec.c | 20
hw/loongarch/virt.c | 11 +--
target/loongarch/cpu.h | 3 ++-
3 files changed, 31 insertions(+), 3 deletions
default avec feature bit.
Signed-off-by: Song Gao
---
hw/loongarch/virt.c | 30 ++
include/hw/loongarch/virt.h | 14 ++
2 files changed, 44 insertions(+)
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index b15ada2078..112cf9a9db 100644
--- a
Add feature register and misc register for avecintc feature checking and
setting
Signed-off-by: Song Gao
---
hw/loongarch/virt.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index 112cf9a9db..0d05404eb5 100644
--- a/hw/loongarch
the AVEC controller supports 256*256 irqs input, all the irqs connect CPU
INT_AVEC irq
Signed-off-by: Song Gao
---
hw/intc/loongarch_avec.c | 20
hw/loongarch/virt.c | 11 +--
target/loongarch/cpu.h | 3 ++-
3 files changed, 31 insertions(+), 3 deletions
include CSR_MSGIS0-3, CSR_MSGIR and CSR_MSGIE.
Signed-off-by: Song Gao
---
target/loongarch/cpu-csr.h | 3 +++
target/loongarch/cpu.h | 10 ++
target/loongarch/machine.c | 27 +--
3 files changed, 38 insertions(+), 2 deletions(-)
diff --git a/target
Add write misc avecintc status bit and read avecintc feature and status bit.
Signed-off-by: Song Gao
---
hw/loongarch/virt.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index 112cf9a9db..26db1bbd68 100644
--- a/hw/loongarch/virt.c
-off-by: Song Gao
---
hw/loongarch/virt.c | 30 ++
include/hw/loongarch/virt.h | 13 +
2 files changed, 43 insertions(+)
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index b15ada2078..112cf9a9db 100644
--- a/hw/loongarch/virt.c
+++ b/hw
Add Loongarch advance interrupt controller device base Definition.
Signed-off-by: Song Gao
---
hw/intc/Kconfig | 3 ++
hw/intc/loongarch_avec.c | 68
hw/intc/meson.build | 1 +
hw/loongarch/Kconfig | 1
implement the read-clear feature for CSR_MSGIR register.
Signed-off-by: Song Gao
---
target/loongarch/csr.c| 5 +
target/loongarch/tcg/csr_helper.c | 22 +++
target/loongarch/tcg/helper.h | 1 +
.../tcg/insn_trans
me code style;
3: Merge patch8 and patch9 into one patch8;
4: Fix patch7 get wrong cpu_num and irq_num;
5: Add vmstate_msg for messag-interrupt registers migrate;
6: Update test scripts use '-bios', because kernel use avec need acpi
support. the bios is qemu/pc_bios/edk2-loongarch
when cpu added, connect avec irq to cpu INT_AVEC irq pin.
Signed-off-by: Song Gao
---
hw/intc/loongarch_avec.c | 71
hw/loongarch/virt.c | 7
2 files changed, 78 insertions(+)
diff --git a/hw/intc/loongarch_avec.c b/hw/intc/loongarch_avec.c
when loongarch cpu set irq is INT_AVEC, we need set CSR_ESTAT.MSGINT bit
and CSR_ECFG.MSGINT bit.
Signed-off-by: Song Gao
---
target/loongarch/cpu-csr.h | 6 --
target/loongarch/cpu.c | 10 ++
2 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/target/loongarch/cpu
the AVEC controller use [2fe0-2ff00) Memory.
Signed-off-by: Song Gao
---
hw/intc/loongarch_avec.c | 24
hw/loongarch/virt.c | 39 +++-
include/hw/intc/loongarch_avec.h | 1 +
include/hw/loongarch/virt.h | 1
Implement avec set irq and update CSR_MSIS.
Signed-off-by: Song Gao
---
hw/intc/loongarch_avec.c | 35 +--
1 file changed, 33 insertions(+), 2 deletions(-)
diff --git a/hw/intc/loongarch_avec.c b/hw/intc/loongarch_avec.c
index 1f9f376898..8ccd6092e6 100644
--- a
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