On Fri May 16, 2025 at 1:36 AM AEST, Cédric Le Goater wrote:
> On 5/12/25 05:10, Nicholas Piggin wrote:
>> These changes gets the powernv xive2 to the point it is able to run
>> PowerVM with good stability.
>>
>> * Various bug fixes around lost interrupts particularly.
On Mon May 12, 2025 at 1:10 PM AEST, Nicholas Piggin wrote:
> From: Michael Kowal
>
> This can make it easier to see what the target system is trying to
> do.
>
Reviewed-by: Nicholas Piggin
> [npiggin: split from larger patch]
> Signed-off-by: Michael Kowal
> ---
>
On Mon May 12, 2025 at 1:10 PM AEST, Nicholas Piggin wrote:
> From: Glenn Miles
>
> When an XIVE context is pulled while it has an active, unacknowledged
> group interrupt, XIVE will check to see if a context on another thread
> can handle the interrupt and, if so, notify that con
On Mon May 12, 2025 at 1:10 PM AEST, Nicholas Piggin wrote:
> From: Glenn Miles
>
> Add support for redistributing a presented group interrupt if it
> is precluded as a result of changing the CPPR value. Without this,
> group interrupts can be lost.
Reviewed-by: Nicholas Piggin
On Mon May 12, 2025 at 1:10 PM AEST, Nicholas Piggin wrote:
> From: Glenn Miles
>
> Booting AIX in a PowerVM partition requires the use of the "Acknowledge
> O/S Interrupt to even O/S reporting line" special operation provided by
> the IBM XIVE interrupt controller. Thi
On Mon May 12, 2025 at 1:10 PM AEST, Nicholas Piggin wrote:
> From: Glenn Miles
>
> Add more tracing around notification, redistribution, and escalation.
>
Reviewed-by: Nicholas Piggin
> Signed-off-by: Glenn Miles
> ---
> hw/intc/trace-events | 6 ++
> h
On Mon May 12, 2025 at 1:10 PM AEST, Nicholas Piggin wrote:
> From: Glenn Miles
>
> Change pregs to pool_regs, for clarity.
>
Reviewed-by: Nicholas Piggin
> [npiggin: split from larger patch]
> Signed-off-by: Glenn Miles
> ---
> hw/intc/xive2.c | 11 +---
On Mon May 12, 2025 at 1:10 PM AEST, Nicholas Piggin wrote:
> From: Glenn Miles
>
> Adds support for extracting additional configuration flags from
> the XIVE configuration register that are needed for redistribution
> of group interrupts.
Reviewed-by: Nicholas Piggin
>
>
On Mon May 12, 2025 at 1:10 PM AEST, Nicholas Piggin wrote:
> From: Michael Kowal
>
> Writes to the Flush Control registers were logged as invalid
> when they are allowed. Clearing the unsupported want_cache_disable
> feature is supported, so don't log an error in that case.
On Mon May 12, 2025 at 1:10 PM AEST, Nicholas Piggin wrote:
> From: Glenn Miles
>
> According to the XIVE spec, updating the CPPR should also update the
> PIPR. The final value of the PIPR depends on other factors, but it
> should never be set to a value that is above the CPPR.
On Mon May 12, 2025 at 1:10 PM AEST, Nicholas Piggin wrote:
> From: Glenn Miles
>
> The current xive algorithm for finding a matching group vCPU
> target always uses the first vCPU found. And, since it always
> starts the search with thread 0 of a core, thread 0 is almost
> alw
On Mon May 12, 2025 at 1:10 PM AEST, Nicholas Piggin wrote:
> From: Glenn Miles
>
> A problem was seen where uart interrupts would be lost resulting in the
> console hanging. Traces showed that a lower priority interrupt was
> preempting a higher priority interrupt, which woul
On Mon May 12, 2025 at 1:10 PM AEST, Nicholas Piggin wrote:
> From: Michael Kowal
>
> When the END Event Queue wraps the END EQ Generation bit is flipped and the
> Generation Flipped bit is set to one. On a END cache Watch read operation,
> the Generation Flipped bit needs to be r
On Mon May 12, 2025 at 1:10 PM AEST, Nicholas Piggin wrote:
> From: Michael Kowal
>
> In a multi chip environment there will be remote/forwarded VSDs. The check
> to find a matching INT controller (XIVE) of the remote block number was
> checking the INTs chip number. Block numbe
On Mon May 12, 2025 at 1:10 PM AEST, Nicholas Piggin wrote:
> From: Glenn Miles
>
> Add support for XIVE ESB Interrupt Escalation.
>
> Suggested-by: Michael Kowal
> [This change was taken from a patch provided by Michael Kowal.]
> Signed-off-by: Glenn Miles
>
On Mon May 12, 2025 at 1:10 PM AEST, Nicholas Piggin wrote:
> From: Glenn Miles
>
> The queue size of an Event Notification Descriptor (END)
> is determined by the 'cl' and QsZ fields of the END.
> If the cl field is 1, then the queue size (in bytes) will
> be the s
On Thu May 15, 2025 at 6:42 AM AEST, Mike Kowal wrote:
>
> On 5/11/2025 10:10 PM, Nicholas Piggin wrote:
>> Further split xive_tctx_pipr_update() by splitting out a new function
>> that is used to re-compute the PIPR from IPB. This is generally only
>> used with XIVE1,
On Fri May 16, 2025 at 1:21 AM AEST, Mike Kowal wrote:
>
> On 5/14/2025 3:10 PM, Mike Kowal wrote:
>>
>> On 5/11/2025 10:10 PM, Nicholas Piggin wrote:
>>> xive_tctx_pipr_update() is used for multiple things. In an effort
>>> to make things simpler and les
On Fri May 16, 2025 at 1:16 AM AEST, Mike Kowal wrote:
>
> On 5/11/2025 10:10 PM, Nicholas Piggin wrote:
>> The relationship between an interrupt signaled in the TIMA and the QEMU
>> irq line to the processor to be 1:1, so they should be raised and
>
> ...needs to be...
>
On Thu May 15, 2025 at 6:10 AM AEST, Mike Kowal wrote:
>
> On 5/11/2025 10:10 PM, Nicholas Piggin wrote:
>> xive_tctx_pipr_update() is used for multiple things. In an effort
>> to make things simpler and less overloaded, split out the function
>> that is used to present a n
On Thu May 15, 2025 at 5:54 AM AEST, Mike Kowal wrote:
>
> On 5/11/2025 10:10 PM, Nicholas Piggin wrote:
>> Have the match_nvt method only perform a TCTX match but don't present
>> the interrupt, the caller presents. This has no functional change, but
>> allows for
On Thu May 15, 2025 at 5:07 AM AEST, Mike Kowal wrote:
>
> On 5/11/2025 10:10 PM, Nicholas Piggin wrote:
>> Have xive_tctx_accept clear NSR in one shot rather than masking out bits
>> as they are tested, which makes it clear it's reset to 0, and does not
>> have a part
xive_tctx_pipr_update() is used for multiple things. In an effort
to make things simpler and less overloaded, split out the function
that is used to present a new interrupt to the tctx.
Signed-off-by: Nicholas Piggin
---
hw/intc/xive.c| 8 +++-
hw/intc/xive2.c | 2 +-
include
Report access size in XIVE TM operation error logs.
Signed-off-by: Nicholas Piggin
---
hw/intc/xive.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index 3eb28c2265..80b07a0afe 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
From: Glenn Miles
The current xive algorithm for finding a matching group vCPU
target always uses the first vCPU found. And, since it always
starts the search with thread 0 of a core, thread 0 is almost
always used to handle group interrupts. This can lead to additional
interrupt latency and po
When CPPR priority is decreased, pending interrupts do not need to be
re-checked if one is already presented because by definition that will
be the highest priority.
This prevents a presented group interrupt from being lost.
Signed-off-by: Nicholas Piggin
---
hw/intc/xive2.c | 4 +++-
1 file
After pulling the pool context, if a pool irq had been presented and
was cleared in the process, there could be a pending irq in phys that
should be presented. Process the phys irq ring after pulling pool ring
to catch this case and avoid losing irqs.
Signed-off-by: Nicholas Piggin
---
hw/intc
OS-push operation must re-present pending interrupts. Use the
newly created xive2_tctx_process_pending() function instead of
duplicating the logic.
Signed-off-by: Nicholas Piggin
---
hw/intc/xive2.c | 42 ++
1 file changed, 10 insertions(+), 32 deletions
Implement set LGS for the POOL ring.
Signed-off-by: Nicholas Piggin
---
hw/intc/xive.c | 8
1 file changed, 8 insertions(+)
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index dc64edf13d..807a1c1c34 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -532,6 +532,12 @@ static void
: Nicholas Piggin
---
hw/intc/xive2.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c
index 21cd07df68..392ac6077e 100644
--- a/hw/intc/xive2.c
+++ b/hw/intc/xive2.c
@@ -945,8 +945,9 @@ static void xive2_tctx_need_resend(Xive2Router *xrtr
Add some assertions to try to ensure presented group interrupts do
not get lost without being redistributed, if they become precluded
by CPPR or preempted by a higher priority interrupt.
Signed-off-by: Nicholas Piggin
---
hw/intc/xive.c | 2 ++
hw/intc/xive2.c | 1 +
2 files changed, 3
Have xive_tctx_accept clear NSR in one shot rather than masking out bits
as they are tested, which makes it clear it's reset to 0, and does not
have a partial NSR value in the register.
Signed-off-by: Nicholas Piggin
---
hw/intc/xive.c | 6 ++
1 file changed, 2 insertions(+), 4 dele
This improves the implementation of pulling pool and phys contexts in
XIVE1, by following closer the OS pulling code.
In particular, the old ring data is returned rather than the modified,
and irq signals are reset on pull.
Signed-off-by: Nicholas Piggin
---
hw/intc/xive.c | 66
Group interrupts should not be taken from the backlog and presented
if they are precluded by CPPR.
Fixes: 855434b3b8 ("ppc/xive2: Process group backlog when pushing an OS
context")
Signed-off-by: Nicholas Piggin
---
hw/intc/xive2.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletio
The relationship between an interrupt signaled in the TIMA and the QEMU
irq line to the processor to be 1:1, so they should be raised and
lowered together and "just in case" lowering should be avoided (it could
mask
Signed-off-by: Nicholas Piggin
---
hw/intc/xive.c | 3 +--
1 file
Typo, IBP should be IPB.
Signed-off-by: Nicholas Piggin
---
hw/intc/trace-events | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
index 0ba9a02e73..f77f9733c9 100644
--- a/hw/intc/trace-events
+++ b/hw/intc/trace-events
Implement the phys (aka hard) VP push. PowerVM uses this operation.
Signed-off-by: Nicholas Piggin
---
hw/intc/xive.c | 2 ++
hw/intc/xive2.c| 11 +++
include/hw/ppc/xive2.h | 2 ++
3 files changed, 15 insertions(+)
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index
From: Glenn Miles
When disabling (pulling) an xive interrupt context, we need
to redistribute any active group interrupts to other threads
that can handle the interrupt if possible. This support had
already been added for the OS context but had not yet been
added to the pool or physical context.
From: Michael Kowal
This can make it easier to see what the target system is trying to
do.
[npiggin: split from larger patch]
Signed-off-by: Michael Kowal
---
hw/intc/pnv_xive2.c | 24
1 file changed, 16 insertions(+), 8 deletions(-)
diff --git a/hw/intc/pnv_xive2.c b
When pushing a context, the lower-level context becomes valid if it
had V=1, and so on. Iterate lower level contexts and send them
pending interrupts if they become enabled.
Signed-off-by: Nicholas Piggin
---
hw/intc/xive2.c | 36
1 file changed, 28
A group interrupt that gets preempted by a higher priority interrupt
delivery must be redistributed otherwise it would get lost.
Signed-off-by: Nicholas Piggin
---
hw/intc/xive2.c | 14 --
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/hw/intc/xive2.c b/hw/intc/xive2
This is needed by the next patch which will re-send on all lower
rings when pushing a context.
Signed-off-by: Nicholas Piggin
---
hw/intc/xive.c | 24
hw/intc/xive2.c | 28
2 files changed, 28 insertions(+), 24 deletions(-)
diff --git a/hw
, but PIPR and NSR must not present the lower priority
interrupt.
Signed-off-by: Nicholas Piggin
---
hw/intc/xive.c | 18 +-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index bf4c0634ca..25f6c69c44 100644
--- a/hw/intc/xive.c
+++ b
xive2 must take into account redistribution of group interrupts if
the VP directed priority exceeds the group interrupt priority after
this operation. The xive1 code is not group aware so implement this
for xive2.
Signed-off-by: Nicholas Piggin
---
hw/intc/xive.c | 2 ++
hw/intc/xive2
From: Glenn Miles
Adds support for extracting additional configuration flags from
the XIVE configuration register that are needed for redistribution
of group interrupts.
Signed-off-by: Glenn Miles
---
hw/intc/pnv_xive2.c | 16
hw/intc/pnv_xive2_regs.h | 1 +
include/hw/p
Have xive_tctx_notify() also set the new PIPR value and rename it to
xive_tctx_pipr_set(). This can replace the last xive_tctx_pipr_update()
caller because it does not need to update IPB (it already sets it).
Signed-off-by: Nicholas Piggin
---
hw/intc/xive.c| 39
signaling ring from the presenting ring.
Instead of alt_regs, use the names sig_regs and sig_ring, and regs and
ring for the presenting ring being worked on. Add a helper function to
get the sign_regs, and add some asserts to ensure the POOL regs are
never used to signal interrupts.
Signed-off
Pushing a context and loading IPB from NVP is defined to merge ('or')
that IPB into the TIMA IPB register. PIPR should therefore be calculated
based on the final IPB value, not just the NVP value.
Fixes: 9d2b6058c5b ("ppc/xive2: Add grouping level to notification")
Signed-off
Certain TIMA operations should only be performed when a ring is valid,
others when the ring is invalid, and they are considered undefined if
used incorrectly. Add checks for this condition.
Signed-off-by: Nicholas Piggin
---
hw/intc/xive.c| 196
From: Glenn Miles
Add more tracing around notification, redistribution, and escalation.
Signed-off-by: Glenn Miles
---
hw/intc/trace-events | 6 ++
hw/intc/xive.c | 3 +++
hw/intc/xive2.c | 13 -
3 files changed, 17 insertions(+), 5 deletions(-)
diff --git a/hw/in
From: Glenn Miles
A problem was seen where uart interrupts would be lost resulting in the
console hanging. Traces showed that a lower priority interrupt was
preempting a higher priority interrupt, which would result in the higher
priority interrupt never being handled.
The new interrupt's priori
Have the match_nvt method only perform a TCTX match but don't present
the interrupt, the caller presents. This has no functional change, but
allows for more complicated presentation logic after matching.
Signed-off-by: Nicholas Piggin
---
hw/intc/pnv_xive.c| 16 +++---
hw
When the pool context is pulled, the shared pool/phys signal is
reset, which loses the qemu irq if a phys interrupt was presented.
Only reset the signal if a poll irq was presented.
Signed-off-by: Nicholas Piggin
---
hw/intc/xive2.c | 18 ++
1 file changed, 10 insertions(+), 8
From: Glenn Miles
Add support for redistributing a presented group interrupt if it
is precluded as a result of changing the CPPR value. Without this,
group interrupts can be lost.
Signed-off-by: Glenn Miles
---
hw/intc/xive2.c | 82 -
1 file chan
Implement pool context push TIMA op.
Signed-off-by: Nicholas Piggin
---
hw/intc/xive.c | 4
hw/intc/xive2.c| 50 --
include/hw/ppc/xive2.h | 2 ++
3 files changed, 39 insertions(+), 17 deletions(-)
diff --git a/hw/intc/xive.c b/hw
The second part of the set CPPR operation is to process (or re-present)
any pending interrupts after CPPR is adjusted.
Split this presentation processing out into a standalone function that
can be used in other places.
Signed-off-by: Nicholas Piggin
---
hw/intc/xive2.c | 137
Firmware expects to read back the WATCH_FULL bit from the VC_ENDC_WATCH_SPEC
register, so don't clear it on read.
Don't bother clearing the reads-as-zero CONFLICT bit because it's masked
at write already.
Signed-off-by: Nicholas Piggin
---
hw/intc/pnv_xive2.c | 1 -
1 file chan
From: Glenn Miles
Booting AIX in a PowerVM partition requires the use of the "Acknowledge
O/S Interrupt to even O/S reporting line" special operation provided by
the IBM XIVE interrupt controller. This operation is invoked by writing
a byte (data is irrelevant) to offset 0xC10 of the Thread Inter
x27;s not clear whether non-pool VPs always or never get CPPR updated.
Before this patch, OS contexts always save CPPR, so we will assume that
is the behaviour.
Signed-off-by: Nicholas Piggin
---
hw/intc/xive2.c | 51 +
include/hw/ppc/xive2_regs.h | 1
Further split xive_tctx_pipr_update() by splitting out a new function
that is used to re-compute the PIPR from IPB. This is generally only
used with XIVE1, because group interrputs require more logic.
Signed-off-by: Nicholas Piggin
---
hw/intc/xive.c | 25 ++---
1 file
From: Glenn Miles
When an XIVE context is pulled while it has an active, unacknowledged
group interrupt, XIVE will check to see if a context on another thread
can handle the interrupt and, if so, notify that context. If there
are no contexts that can handle the interrupt, then the interrupt is
a
From: Glenn Miles
Change pregs to pool_regs, for clarity.
[npiggin: split from larger patch]
Signed-off-by: Glenn Miles
---
hw/intc/xive2.c | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c
index 968b698677..ec4b9320b4 100644
---
From: Michael Kowal
Writes to the Flush Control registers were logged as invalid
when they are allowed. Clearing the unsupported want_cache_disable
feature is supported, so don't log an error in that case.
Signed-off-by: Michael Kowal
---
hw/intc/pnv_xive2.c | 36 ++
From: Glenn Miles
According to the XIVE spec, updating the CPPR should also update the
PIPR. The final value of the PIPR depends on other factors, but it
should never be set to a value that is above the CPPR.
Also added support for redistributing an active group interrupt when it
is precluded as
by re-starting the selection logic if the
backlog irq was not found or priority did not match LSMFB (LSMFB
is updated so next time around it would see the right value and
not loop infinitely).
Signed-off-by: Nicholas Piggin
---
hw/intc/xive2.c | 32 ++--
1 file chang
From: Michael Kowal
In a multi chip environment there will be remote/forwarded VSDs. The check
to find a matching INT controller (XIVE) of the remote block number was
checking the INTs chip number. Block numbers are not tied to a chip number.
The matching remote INT is the one that matches the
If CPPR is lowered to preclude the pending interrupt, NSR should be
cleared and the qemu_irq should be lowered. This avoids some cases
of supurious interrupts.
Signed-off-by: Nicholas Piggin
---
hw/intc/xive.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/intc/xive.c b/hw/intc
From: Glenn Miles
Add support for XIVE ESB Interrupt Escalation.
Suggested-by: Michael Kowal
[This change was taken from a patch provided by Michael Kowal.]
Signed-off-by: Glenn Miles
---
hw/intc/xive2.c | 62 ++---
include/hw/ppc/xive2.h | 1
From: Michael Kowal
When the END Event Queue wraps the END EQ Generation bit is flipped and the
Generation Flipped bit is set to one. On a END cache Watch read operation,
the Generation Flipped bit needs to be reset.
While debugging an error modified END not valid error messages to include
the
Rather than functions to return masks to test NSR bits, have functions
to test those bits directly. This should be no functional change, it
just makes the code more readable.
Signed-off-by: Nicholas Piggin
---
hw/intc/xive.c| 51 +++
include/hw
From: Glenn Miles
The queue size of an Event Notification Descriptor (END)
is determined by the 'cl' and QsZ fields of the END.
If the cl field is 1, then the queue size (in bytes) will
be the size of a cache line 128B * 2^QsZ and QsZ is limited
to 4. Otherwise, it will be 4096B * 2^QsZ with QsZ
: Add special handling for pool targets")
Signed-off-by: Nicholas Piggin
---
hw/intc/xive.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index 80b07a0afe..cebe409a1a 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -54,7 +54,8 @@ stati
ppc/xive2: Remote VSDs need to match on forwarding address
ppc/xive2: Reset Generation Flipped bit on END Cache Watch
pnv/xive2: Print value in invalid register write logging
pnv/xive2: Permit valid writes to VC/PC Flush Control registers
Nicholas Piggin (34):
ppc/xive: Fix xive trace ev
On Mon May 5, 2025 at 3:25 PM AEST, Akihiko Odaki wrote:
> On 2025/05/02 12:04, Nicholas Piggin wrote:
>> ahci-test has a bunch of tests where the pci bar was not mapped. Avoid
>> unmapping it in these cases, to keep iomaps balanced.
>>
>> Cc: Michael S. Tsirkin
>
On Mon May 5, 2025 at 3:37 PM AEST, Akihiko Odaki wrote:
> On 2025/05/02 12:04, Nicholas Piggin wrote:
>> This function is duplicated 3 times, with more potential future users.
>> Factor it into libqos, using qtest_memset instead of qtest_writel to
>> clear the message ju
On Mon May 5, 2025 at 3:25 PM AEST, Akihiko Odaki wrote:
> On 2025/05/02 12:04, Nicholas Piggin wrote:
>> ahci-test has a bunch of tests where the pci bar was not mapped. Avoid
>> unmapping it in these cases, to keep iomaps balanced.
>>
>> Cc: Michael S. Tsirkin
>
On Mon May 5, 2025 at 3:05 PM AEST, Akihiko Odaki wrote:
> On 2025/05/02 12:04, Nicholas Piggin wrote:
>> msix messages are written to memory in little-endian order, so they
>> should not be byteswapped depending on target endianness, but read
>> as le and converted to hos
On Mon May 5, 2025 at 4:03 PM AEST, Akihiko Odaki wrote:
> On 2025/05/02 12:17, Nicholas Piggin wrote:
>> Timer expiry that results in an interrupt does not rearm the timer so
>> an interrupt can appear immediately after the interrupt generated by
>> timer expiry.
>>
On Mon May 5, 2025 at 3:51 PM AEST, Akihiko Odaki wrote:
> On 2025/05/02 12:17, Nicholas Piggin wrote:
>> The msix interrupt throttling timer expiry sends an interrupt even if
>> there is no unmasked interrupt causes. This can be observed by seeing
>> two interrupts in respo
On Mon May 5, 2025 at 3:45 PM AEST, Akihiko Odaki wrote:
> On 2025/05/02 12:16, Nicholas Piggin wrote:
>> The guest value xITR logic is not required now that the write functions
>> store necessary data to be read back, and internal users mask and shift
>> fields they need as t
On Mon May 5, 2025 at 3:41 PM AEST, Akihiko Odaki wrote:
> On 2025/05/02 12:16, Nicholas Piggin wrote:
>> The spec explicitly permits xITR register interval field to have a value
>> of zero to disable throttling. The e1000e model already allows for this
>> in the throttling
On Fri May 2, 2025 at 1:30 PM AEST, Nicholas Piggin wrote:
> This is merged from two series now because code especially the test
> cases have started to depend on one another.
Question for the list, hw/usb/* is marked orphan. I don't have the
bandwidth to take it on. There's
On Fri May 2, 2025 at 6:24 PM AEST, Philippe Mathieu-Daudé wrote:
> On 2/5/25 05:30, Nicholas Piggin wrote:
>> msix
>
> Hmm? :)
Oops, thanks. Too much juggling around of the different patch series.
This depends on some of the libqos pci changes so I split it out (and
it's
il the CBW packet arrives.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Nicholas Piggin
---
include/hw/usb/msd.h | 14 ++---
hw/usb/dev-storage.c | 50 +++-
2 files changed, 33 insertions(+), 31 deletions(-)
diff --git a/include/hw/usb/msd.h
msix
---
tests/qtest/usb-hcd-xhci-test.c | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/tests/qtest/usb-hcd-xhci-test.c b/tests/qtest/usb-hcd-xhci-test.c
index 7f801f8f1a0..2eecc8d9f26 100644
--- a/tests/qtest/usb-hcd-xhci-test.c
+++ b/tests/qtest/usb-hcd-xhci-t
This adds a qtest for the improvement to the MSD protocol that
allows an IN packet before the CBW packet. Send a CSW packet
before a zero-length CBW command packet is sent. This test would
fail with the MSD change reverted.
Signed-off-by: Nicholas Piggin
---
tests/qtest/usb-hcd-xhci-test.c
Prepare to use some of these constants in xhci qtest code.
Signed-off-by: Nicholas Piggin
---
hw/usb/hcd-xhci.h | 214 ++
hw/usb/hcd-xhci.c | 450 +++---
2 files changed, 360 insertions(+), 304 deletions(-)
diff --git a/hw/usb/hcd
warning of possible guest error if size is not exact,
but still accept the packets.
Signed-off-by: Nicholas Piggin
---
hw/usb/dev-storage.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/usb/dev-storage.c b/hw/usb/dev-storage.c
index 7bc2f7664b2..fe8955bf212 100644
--- a/
To prepare to support another USB PCI Host Controller, make some PCI
configuration dynamic.
Signed-off-by: Nicholas Piggin
---
hw/usb/hcd-xhci-pci.h | 9
hw/usb/hcd-xhci-pci.c | 118 +-
2 files changed, 103 insertions(+), 24 deletions(-)
diff
The async packet handling logic has places that infer whether the
async packet is data or CSW, based on context. This is not wrong,
it just makes the logic easier to follow if they are categorised
when they are accepted.
Signed-off-by: Nicholas Piggin
---
include/hw/usb/msd.h | 5 +-
hw/usb
Add tracing for more received packet types, cbw_state changes, and
some more SCSI callbacks. These were useful in debugging relaxed
packet ordering support.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Nicholas Piggin
---
hw/usb/dev-storage.c | 61
Run some TR NOOP commands through the transfer ring.
Signed-off-by: Nicholas Piggin
---
tests/qtest/usb-hcd-xhci-test.c | 36 +
1 file changed, 36 insertions(+)
diff --git a/tests/qtest/usb-hcd-xhci-test.c b/tests/qtest/usb-hcd-xhci-test.c
index 39c5c36e940
This is not really required for the state machine but it improves
the symmetry of zero-data packets with data packets, and helps with
assertions and reasoning about traces.
Signed-off-by: Nicholas Piggin
---
include/hw/usb/msd.h | 1 +
hw/usb/dev-storage.c | 10 +++---
2 files changed, 8
Errors in incoming USB MSD packet format or context would typically
be guest software errors. Log these under guest errors.
Signed-off-by: Nicholas Piggin
---
hw/usb/dev-storage.c | 53 +++-
1 file changed, 42 insertions(+), 11 deletions(-)
diff --git a
The mass storage reset request handling does not reset in-flight
SCSI requests or USB MSD packets. Implement this by calling the
device reset handler which should take care of everything.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Nicholas Piggin
---
hw/usb/dev-storage.c | 2 +-
1 file
Add more assertions to help verify internal logic.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Nicholas Piggin
---
hw/usb/dev-storage.c | 23 +++
1 file changed, 19 insertions(+), 4 deletions(-)
diff --git a/hw/usb/dev-storage.c b/hw/usb/dev-storage.c
index
These structures are hardware interfaces, ensure the layout is
correct. Add defines for the data sizes throughout the code.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Nicholas Piggin
---
hw/usb/dev-storage.c | 21 -
1 file changed, 16 insertions(+), 5 deletions
This also adds some missing constants rather than open-coding
offsets and sizes.
Signed-off-by: Nicholas Piggin
---
hw/usb/hcd-xhci.h | 16
hw/usb/hcd-xhci.c | 48 ++-
2 files changed, 38 insertions(+), 26 deletions(-)
diff --git a
n "unknown"
packet until the CBW arrives, then they are categorized into a DATA or
CSW packet.
It is not clear whether the spec permits multiple such packets before
the CBW. This implementation permits only one, which seems to be enough
for AIX.
Signed-off-by: Nicholas Piggin
---
inclu
Add tests which init the host controller registers to the point where
command and event rings, irqs are operational. Enumerate ports and set
up an attached device context that enables device transfer ring to be
set up and tested.
Signed-off-by: Nicholas Piggin
---
hw/usb/hcd-xhci.h
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