This is needed by the next patch which will re-send on all lower
rings when pushing a context.
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
---
hw/intc/xive.c | 24 ++++++++++++------------
hw/intc/xive2.c | 28 ++++++++++++++++------------
2 files changed, 28 insertions(+), 24 deletions(-)
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index 69118999e6..9ade9ec6c1 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -606,7 +606,7 @@ static uint64_t xive_tm_pull_os_ctx(XivePresenter *xptr,
XiveTCTX *tctx,
return qw1w2;
}
-static void xive_tctx_need_resend(XiveRouter *xrtr, XiveTCTX *tctx,
+static void xive_tctx_restore_nvp(XiveRouter *xrtr, XiveTCTX *tctx,
uint8_t nvt_blk, uint32_t nvt_idx)
{
XiveNVT nvt;
@@ -632,16 +632,6 @@ static void xive_tctx_need_resend(XiveRouter *xrtr,
XiveTCTX *tctx,
uint8_t *regs = &tctx->regs[TM_QW1_OS];
regs[TM_IPB] |= ipb;
}
-
- /*
- * Always call xive_tctx_recompute_from_ipb(). Even if there were no
- * escalation triggered, there could be a pending interrupt which
- * was saved when the context was pulled and that we need to take
- * into account by recalculating the PIPR (which is not
- * saved/restored).
- * It will also raise the External interrupt signal if needed.
- */
- xive_tctx_pipr_recompute_from_ipb(tctx, TM_QW1_OS); /* fxb */
}
/*
@@ -663,7 +653,17 @@ static void xive_tm_push_os_ctx(XivePresenter *xptr,
XiveTCTX *tctx,
/* Check the interrupt pending bits */
if (vo) {
- xive_tctx_need_resend(XIVE_ROUTER(xptr), tctx, nvt_blk, nvt_idx);
+ xive_tctx_restore_nvp(XIVE_ROUTER(xptr), tctx, nvt_blk, nvt_idx);
+
+ /*
+ * Always call xive_tctx_recompute_from_ipb(). Even if there were no
+ * escalation triggered, there could be a pending interrupt which
+ * was saved when the context was pulled and that we need to take
+ * into account by recalculating the PIPR (which is not
+ * saved/restored).
+ * It will also raise the External interrupt signal if needed.
+ */
+ xive_tctx_pipr_recompute_from_ipb(tctx, TM_QW1_OS); /* fxb */
}
}
diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c
index a9b188b909..53e90b8178 100644
--- a/hw/intc/xive2.c
+++ b/hw/intc/xive2.c
@@ -940,14 +940,14 @@ static uint8_t xive2_tctx_restore_ctx(Xive2Router *xrtr,
XiveTCTX *tctx,
return cppr;
}
-static void xive2_tctx_need_resend(Xive2Router *xrtr, XiveTCTX *tctx,
+/* Restore TIMA VP context from NVP backlog */
+static void xive2_tctx_restore_nvp(Xive2Router *xrtr, XiveTCTX *tctx,
uint8_t ring,
uint8_t nvp_blk, uint32_t nvp_idx,
bool do_restore)
{
- uint8_t *sig_regs = xive_tctx_signal_regs(tctx, ring);
uint8_t *regs = &tctx->regs[ring];
- uint8_t ipb, nsr = sig_regs[TM_NSR];
+ uint8_t ipb;
Xive2Nvp nvp;
/*
@@ -978,14 +978,6 @@ static void xive2_tctx_need_resend(Xive2Router *xrtr,
XiveTCTX *tctx,
}
/* IPB bits in the backlog are merged with the TIMA IPB bits */
regs[TM_IPB] |= ipb;
-
- if (xive_nsr_indicates_group_exception(ring, nsr)) {
- /* redistribute precluded active grp interrupt */
- g_assert(ring == TM_QW2_HV_POOL); /* PHYS ring has the grp interrupt */
- xive2_redistribute(xrtr, tctx, xive_nsr_exception_ring(ring, nsr));
- }
- xive2_tctx_process_pending(tctx, ring == TM_QW2_HV_POOL ?
- TM_QW3_HV_PHYS : ring);
}
/*
@@ -1028,8 +1020,20 @@ static void xive2_tm_push_ctx(XivePresenter *xptr,
XiveTCTX *tctx,
/* Check the interrupt pending bits */
if (v) {
- xive2_tctx_need_resend(XIVE2_ROUTER(xptr), tctx, ring,
+ Xive2Router *xrtr = XIVE2_ROUTER(xptr);
+ uint8_t *sig_regs = xive_tctx_signal_regs(tctx, ring);
+ uint8_t nsr = sig_regs[TM_NSR];
+
+ xive2_tctx_restore_nvp(xrtr, tctx, ring,
nvp_blk, nvp_idx, do_restore);
+
+ if (xive_nsr_indicates_group_exception(ring, nsr)) {
+ /* redistribute precluded active grp interrupt */
+ g_assert(ring == TM_QW2_HV_POOL); /* PHYS ring has the interrupt */
+ xive2_redistribute(xrtr, tctx, xive_nsr_exception_ring(ring, nsr));
+ }
+ xive2_tctx_process_pending(tctx, ring == TM_QW2_HV_POOL ?
+ TM_QW3_HV_PHYS : ring);
}
}
--
2.47.1
