> On 27 May 2025, at 16:52, Marc Zyngier wrote:
>
> On Tue, 27 May 2025 16:55:32 +0100,
> Miguel Luis wrote:
>>
>> Hi Marc,
>>
>>> On 27 May 2025, at 13:46, Marc Zyngier wrote:
>>>
>>> On Tue, 27 May 2025 14:24:31 +0100,
>>&
Hi Marc,
> On 27 May 2025, at 13:46, Marc Zyngier wrote:
>
> On Tue, 27 May 2025 14:24:31 +0100,
> Miguel Luis wrote:
>>
>>
>>
>>> On 27 May 2025, at 12:02, Marc Zyngier wrote:
>>>
>>> On Tue, 27 May 2025 12:40:35 +0100,
>>
> On 27 May 2025, at 12:02, Marc Zyngier wrote:
>
> On Tue, 27 May 2025 12:40:35 +0100,
> Miguel Luis wrote:
>>
>> Hi Marc,
>>
>>> On 27 May 2025, at 07:39, Marc Zyngier wrote:
>>>
>>> Hi Eric,
>>>
>>> On Tue,
> On 27 May 2025, at 12:01, Marc Zyngier wrote:
>
> On Tue, 27 May 2025 12:33:23 +0100,
> Miguel Luis wrote:
>>
>> Hi Eric,
>>
>>> On 27 May 2025, at 06:24, Eric Auger wrote:
>>>
>>> Now that ARM nested virt has landed in kvm/next,
Hi Marc,
> On 27 May 2025, at 07:39, Marc Zyngier wrote:
>
> Hi Eric,
>
> On Tue, 27 May 2025 07:24:32 +0100,
> Eric Auger wrote:
>>
>> Now that ARM nested virt has landed in kvm/next, let's turn the series
>> into a PATCH series. The linux header update was made against kvm/next.
>>
>> For
Hi Eric,
> On 27 May 2025, at 06:24, Eric Auger wrote:
>
> Now that ARM nested virt has landed in kvm/next, let's turn the series
> into a PATCH series. The linux header update was made against kvm/next.
>
> For gaining virt functionality in KVM accelerated L1, The host needs to
> be booted wit
pected which concerns this
> patch-set. Please have a look.
>
For arm64:
I’ve ran make check and bios-tables-test passed successfully and got 0 failed
tests.
After boot the number of vcpus matched what was initially requested via -smp
cpus.
I’ve also tested this patchset alongside the upco
Hi Gustavo,
> On 18 Oct 2024, at 17:57, Gustavo Romero wrote:
>
> Hi Miguel,
>
> On 10/15/24 15:41, Miguel Luis wrote:
>> Hi Salil,
>> I’ve ran the usual tests successfully of hotplug/unplug from the number of
>> cold-booted cpus up to maxcpus and migratio
https://lists.cs.columbia.edu/pipermail/kvmarm/2018-July/032316.html
> [13] https://lists.gnu.org/archive/html/qemu-devel/2020-01/msg06517.html
> [14]
> https://op-lists.linaro.org/archives/list/linaro-open-discussi...@op-lists.linaro.org/thread/7CGL6JTACPUZEYQC34CZ2ZBWJGSR74WE/
> [15]
Hi Salil,
I’ve ran the usual tests successfully of hotplug/unplug from the number of
cold-booted cpus up to maxcpus and migration on ARM. Please feel free to add:
Tested-by: Miguel Luis
Thanks
Miguel
> On 14 Oct 2024, at 19:22, Salil Mehta wrote:
>
> Certain CPU architecture speci
Hi Salil,
> On 9 Oct 2024, at 03:17, Salil Mehta wrote:
>
> This patch adds various utility functions that may be required to fetch or
> check
> the state of possible vCPUs. It also introduces the concept of *disabled*
> vCPUs,
> which are part of the *possible* vCPUs but are not enabled. This
cket_id, 0),
> +DEFINE_PROP_INT32("cluster-id", ARMCPU, cluster_id, 0),
> +DEFINE_PROP_INT32("core-id", ARMCPU, core_id, 0),
> +DEFINE_PROP_INT32("thread-id", ARMCPU, thread_id, 0),
> DEFINE_PROP_INT32("core-count", ARMCPU, cor
Hi Peter,
> On 8 Oct 2024, at 11:53, Peter Maydell wrote:
>
> On Fri, 27 Sept 2024 at 19:40, Annie Li wrote:
>>
>> From: Miguel Luis
>>
>> For reference: qmp_system_sleep relies on wakeup support delegated
>> by qemu_wakeup_suspe
cpus.
Hot unplug down to the number of boot cpus.
Hotplug vcpus then migrate to a new VM.
Hot unplug down to the number of boot cpus then migrate to a new VM.
Up to 6 successive live migrations.
And in which LGTM.
Please feel free to add,
Tested-by: Miguel Luis
Regards,
Miguel
[1]
https:/
Hi Eric,
> On 8 Feb 2024, at 15:55, Eric Auger wrote:
>
> Hi Miguel,
>
> On 2/27/23 17:37, Miguel Luis wrote:
>> This series adds ARMv8.3/8.4 nested virtualization support in KVM mode.
>>
>> To enable nested virtualization for a guest, the host must expose EL2
, which is a good
> idea anyway and also works around what Marc Z and I think is
> a KVM bug that otherwise causes boot of the L2 kernel to hang
> * patch 3 is a GIC bug which is not FEAT_NV specific but for
> some reason only manifests when booting an L1 kernel under NV
>
I&#
> On 6 Dec 2023, at 14:25, Michal Suchánek wrote:
>
> On Wed, Dec 06, 2023 at 01:17:08PM -0100, Miguel Luis wrote:
>> Hi!
>>
>> On 04/12/2023 18:40, Philippe Mathieu-Daudé wrote:
>>> Unplugging vCPU triggers the following assertion in
>>
Hi!
On 04/12/2023 18:40, Philippe Mathieu-Daudé wrote:
> Unplugging vCPU triggers the following assertion in
> tcg_register_thread():
>
> 796 void tcg_register_thread(void)
> 797 {
> ...
> 812 /* Claim an entry in tcg_ctxs */
> 813 n = qatomic_fetch_inc(&tcg_cur_ctxs);
> 814 g_as
On 11/15/23 20:56, Alex Bennée via Gdb wrote:
> "Nicholas Piggin" writes:
>
>> On Wed Nov 8, 2023 at 12:23 AM AEST, Alex Bennée wrote:
>>> We already do a couple of "info registers" for specific tests but this
>>> is a more comprehensive multiarch test. It also has some output
>>> helpful for debu
> On 16 Oct 2023, at 10:01, Miguel Luis wrote:
>
> Hi Salil,
>
>> On 16 Oct 2023, at 09:52, Salil Mehta wrote:
>>
>> Hi Miguel,
>>
>>> From: Miguel Luis
>>> Sent: Friday, October 13, 2023 5:34 PM
>>> To: Salil Mehta
&
Hi Salil,
> On 16 Oct 2023, at 09:52, Salil Mehta wrote:
>
> Hi Miguel,
>
>> From: Miguel Luis
>> Sent: Friday, October 13, 2023 5:34 PM
>> To: Salil Mehta
>> Cc: qemu-devel@nongnu.org; qemu-...@nongnu.org; Marc Zyngier
>> ; jean-phili...
++
> include/exec/gdbstub.h | 5 ++
> include/hw/acpi/cpu.h | 5 +-
> include/hw/acpi/cpu_hotplug.h | 4 ++
> include/hw/acpi/generic_event_device.h | 5 ++
> include/hw/core/cpu.h | 1 +
> include/sysemu/kvm.h | 16 +++
> system/physmem.c | 29
> 15 files changed, 184 insertions(+), 27 deletions(-)
>
I tested it for Arm64, make check, boot/reboot, live migration and found no
issues,
so for this, please feel free to add:
Tested-by: Miguel Luis
Thank you,
Miguel
> --
> 2.34.1
>
Hi Salil,
> On 12 Oct 2023, at 17:54, Salil Mehta wrote:
>
> Hi Miguel,
>
>> From: Miguel Luis
>> Sent: Thursday, October 12, 2023 6:02 PM
>> To: Salil Mehta
>> Cc: qemu-devel@nongnu.org; qemu-...@nongnu.org; Marc Zyngier
>> ; jean-phili...
> https://uefi.org/specs/ACPI/6.5/05_ACPI_Software_Programming_Model.html#gic-cpu-interface-gicc-structure
> [8] https://bugzilla.tianocore.org/show_bug.cgi?id=4481#c5
> [9]
> https://cloud.google.com/kubernetes-engine/docs/concepts/verticalpodautoscaler
> [10]
> https://doc
Hi Eric,
Thanks in advance for your comment.
> On 6 Jul 2023, at 08:16, Eric Auger wrote:
>
> Hi Miguel,
>
> On 2/27/23 17:37, Miguel Luis wrote:
>> From: Haibo Xu
>>
>> KVM_CAP_ARM_EL2 must be supported by the cpu to enable ARM_FEATURE_EL2.
>> EL2 b
t;> +GString *s = g_string_new(NULL);
>> +int vq = max_svq(cpu);
>> +int row_count = vq * 16;
>> +int row_width = vq * 128;
>> +int i;
>> +
>> +g_string_printf(s, "");
>> +g_string_append_printf(s, "> \"
On 3/17/23 17:12, Luis Machado wrote:
On 3/17/23 17:07, Peter Maydell wrote:
On Fri, 17 Mar 2023 at 16:55, Luis Machado wrote:
On 3/17/23 16:37, Peter Maydell wrote:
Having run into this problem in another couple of situations, one of
which involved gdb 10, I think I'm increasingly favo
On 3/17/23 17:07, Peter Maydell wrote:
On Fri, 17 Mar 2023 at 16:55, Luis Machado wrote:
On 3/17/23 16:37, Peter Maydell wrote:
Having run into this problem in another couple of situations, one of
which involved gdb 10, I think I'm increasingly favouring option
2 here. The affected gdbs
On 3/17/23 16:37, Peter Maydell wrote:
On Wed, 15 Mar 2023 at 09:51, Luis Machado wrote:
On 3/13/23 11:44, Luis Machado wrote:
On 3/13/23 11:22, Peter Maydell via Gdb wrote:
Luis and I came up with two options:
(1) leave QEMU outputting the pauth xml as-is, and tell people
whose gdb 12
Hi,
On 3/13/23 11:44, Luis Machado wrote:
On 3/13/23 11:22, Peter Maydell via Gdb wrote:
On Fri, 10 Mar 2023 at 18:20, Alex Bennée wrote:
(adding some more gdb types to CC)
Fabiano Rosas writes:
Peter Maydell writes:
On Fri, 10 Mar 2023 at 10:31, Alex Bennée wrote:
You need a
On 3/13/23 19:21, Richard Henderson wrote:
On 3/13/23 04:44, Luis Machado wrote:
Luis: I think that rather than doing (2) with a QEMU namespace,
we should define a gdb namespace for this. That makes it clear
that this is still a gdb-upstream-sanctioned way of exposing
the pauth registers
rg.qemu.aarch64.pauth" made it stop crashing and I can read the
registers just fine.
That would work, although I would prefer to probe support so we can use
the official namespace.
I don't think there's a way to probe for this problem. I spoke
to Luis about this, and appa
containing system
registers gdb doesn't
care about).
But then presumably a pauth-aware GDB won't actually know
the values it needs to be able to convert between with-PAC
and without-PAC addresses for backtracing?
Luis, how is this intended to work? Is there some way the
stub can chec
Hi Marc,
> On 6 Mar 2023, at 13:32, Marc Zyngier wrote:
>
> On Mon, 06 Mar 2023 14:02:33 +,
> Peter Maydell wrote:
>>
>> On Mon, 27 Feb 2023 at 16:37, Miguel Luis wrote:
>>>
>>> From: Haibo Xu
>>>
>>> Use the
Hi Peter,
> On 6 Mar 2023, at 13:02, Peter Maydell wrote:
>
> On Mon, 27 Feb 2023 at 16:37, Miguel Luis wrote:
>>
>> From: Haibo Xu
>>
>> Use the VGIC maintenance IRQ if VHE is requested. As per the ARM GIC
>> Architecture Specification for GICv3
Hi Richard,
> On 27 Feb 2023, at 18:26, Richard Henderson
> wrote:
>
> On 2/27/23 06:37, Miguel Luis wrote:
>> -if (vms->virt && (kvm_enabled() || hvf_enabled())) {
>> +if (vms->virt && (kvm_enabled() || hvf_enabled())
>> +&am
Hi Richard,
> On 27 Feb 2023, at 18:24, Richard Henderson
> wrote:
>
> On 2/27/23 06:37, Miguel Luis wrote:
>> From: Haibo Xu
>> KVM_CAP_ARM_EL2 must be supported by the cpu to enable ARM_FEATURE_EL2.
>> EL2 bits on ID_AA64PFR0 state unsupported on the v
Hi Cornelia,
> On 27 Feb 2023, at 15:49, Cornelia Huck wrote:
>
> On Mon, Feb 27 2023, Miguel Luis wrote:
>
>> From: Haibo Xu
>>
>> linux-headers define host properties needed for the VMM to interact with
>> KVM, so let's include them *while* they&
From: Haibo Xu
Introduce query support for KVM_CAP_ARM_EL2.
Ref:
https://lore.kernel.org/qemu-devel/65b8771bfecada08bf02c9cf87c2f0f9cdf943b3.1617281290.git.haibo...@linaro.org/
Signed-off-by: Haibo Xu
Signed-off-by: Miguel Luis
---
target/arm/kvm64.c | 5 +
target/arm/kvm_arm.h | 12
From: Haibo Xu
VHE enablement if host supports EL2.
Ref:
https://lore.kernel.org/qemu-devel/b7c2626e6c720ccc43e57197dff3dac72d613640.1616052890.git.haibo...@linaro.org/
Signed-off-by: Haibo Xu
Signed-off-by: Miguel Luis
---
hw/arm/virt.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion
.2880505-1-...@kernel.org/
Miguel Luis (5):
linux-headers: [kvm,arm64] add the necessary definitions to match host
kernel
hw/intc/gicv3: add support for setting KVM vGIC maintenance IRQ
target/arm/kvm: add helper to detect EL2 when using KVM
target/arm: enable feature ARM_FEATURE_EL2
://lore.kernel.org/qemu-devel/49a4944e2f148c56938380b981afe154b7a8b7ee.1617281290.git.haibo...@linaro.org/
Signed-off-by: Haibo Xu
[Miguel Luis: avoid direct usage of helpers (_check_attr(); _access())]
Signed-off-by: Miguel Luis
---
hw/arm/virt.c | 5 +
hw/intc
qemu-devel/636b5932e4cf061b6f97516e82d4319c1d29b871.1616052889.git.haibo...@linaro.org/
Signed-off-by: Haibo Xu
Signed-off-by: Miguel Luis
---
linux-headers/asm-arm64/kvm.h | 2 ++
linux-headers/linux/kvm.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/linux-headers/asm-arm64/kvm.h b/linux-headers/asm-a
[Miguel Luis: use of ID_AA64PFR0 for cpu features]
Signed-off-by: Miguel Luis
---
target/arm/cpu.h | 2 +-
target/arm/kvm64.c | 16
2 files changed, 17 insertions(+), 1 deletion(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 9aeed3c848..de2a88b43e 100644
--- a/target
with Luis Machado, add two more masks in order to support
pointers within the high half of the address space (i.e. TTBR1 vs TTBR0).
Cc: Luis Machado
Cc: Thiago Jung Bauermann
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1105
Signed-off-by: Richard Henderson
---
configs/targets
Should all the rest be in a third bit of xml?
Luis, do you have the specs for what the existing implementations
are doing here ?
Support for the extra stack pointers was contributed by ST (Torbjörn and Yvan
cc-ed), so I'd say ST-Link was the debugging stub the GDB changes were base
//
00F0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 //
-0100: 00 00 00 00 00 00 00 00 00 00 00 00 //
+0100: 00 00 00 00 00 00 00 00 00 00 00 00 51 45 4D 55 // QEMU
+0110: 00 00 00 00
MADT has been updated with the GIC Structures from ACPI 6.0 Errata A
and so MADT revision and GICC Structure must be updated also.
Fixes: 37f33084ed2e ("acpi: arm/virt: madt: use build_append_int_noprefix() API
to compose MADT table")
Signed-off-by: Miguel Luis
Reviewed-by: Ani Sinh
i.org/sites/default/files/resources/ACPI_6_0_Errata_A.PDF
This patch series originates from a previous RFC [1] discussion. Reviewed-by
tags were kept on patches 2/4 and 3/4.
[1]: https://lists.gnu.org/archive/html/qemu-devel/2022-10/msg01326.html
Miguel Luis (4):
tests/acpi: virt: allow acpi MAD
ed through a
supplemental vendor-specific hypervisor API. Firmware implementers would
place zero bytes into this field, denoting that no hypervisor is present in
the actual firmware."
Signed-off-by: Miguel Luis
Reviewed-by: Ani Sinha
---
hw/acpi/aml-build.c | 13 ++---
Step 3 from bios-tables-test.c documented procedure.
Signed-off-by: Miguel Luis
---
tests/qtest/bios-tables-test-allowed-diff.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b
> On 11 Oct 2022, at 05:02, Ani Sinha wrote:
>
> On Mon, Oct 10, 2022 at 6:53 PM Miguel Luis wrote:
>>
>> Update the Fixed ACPI Description Table (FADT) to revision 6.0 of the ACPI
>> specification adding the field "Hypervisor Vendor Identity" that was mis
sion follows Ani Sinha's suggestion [2] of using "QEMU" for the
hypervisor vendor ID.
[1]: https://lists.nongnu.org/archive/html/qemu-devel/2022-10/msg00911.html
[2]: https://lists.nongnu.org/archive/html/qemu-devel/2022-10/msg00989.html
Signed-off-by: Miguel Luis
---
hw/acpi/aml
//
00F0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 //
-0100: 00 00 00 00 00 00 00 00 00 00 00 00 //
+0100: 00 00 00 00 00 00 00 00 00 00 00 00 51 45 4D 55 // QEMU
+0110: 00 00 00 00
ery welcome.
Thanks in advance.
Miguel
[1]: https://lists.nongnu.org/archive/html/qemu-devel/2022-10/msg00989.html
Miguel Luis (4):
tests/acpi: virt: allow acpi MADT and FADT changes
acpi: fadt: support revision 6.0 of the ACPI specification
acpi:
MADT has been updated with the GIC Structures from ACPI 6.0 Errata A
and so MADT revision and GICC Structure must be updated also.
Fixes: 37f33084ed2e ("acpi: arm/virt: madt: use build_append_int_noprefix() API
to compose MADT table")
Signed-off-by: Miguel Luis
Reviewed-by: Ani Sinh
Step 3 from bios-tables-test.c documented procedure.
Signed-off-by: Miguel Luis
---
tests/qtest/bios-tables-test-allowed-diff.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b
> On 7 Oct 2022, at 15:21, Ani Sinha wrote:
>
> On Fri, Oct 7, 2022 at 8:16 PM Miguel Luis wrote:
>>
>> The ACPI GTDT table contains two invalid 64-bit physical addresses according
>> to
>> the ACPI spec. 6.5 [1]. Those are the Counter Control Base physic
00 00 00 00 00 00 00 1A 00 00 00 00 00 00 00 //
-0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 //
+0050: FF FF FF FF FF FF FF FF 00 00 00 00 00 00 00 00 //
Signed-off-by: Miguel Luis
Acked-by: Ani Sinha
---
tests/data/acpi/virt
Step 3 from bios-tables-test.c documented procedure.
Signed-off-by: Miguel Luis
Acked-by: Ani Sinha
---
tests/qtest/bios-tables-test-allowed-diff.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest/bios-tables-test-allowed-diff.h
0x0.
[1]:
https://uefi.org/specs/ACPI/6.5/05_ACPI_Software_Programming_Model.html#gtdt-table-structure
Changelog:
v2:
Updated with collected tags from v1.
v1: https://lists.nongnu.org/archive/html/qemu-devel/2022-09/msg02847.html
Miguel Luis (3):
tests/acpi: virt: allow acpi GTDT changes
begin()/acpi_table_end() instead of build_header()")
Signed-off-by: Miguel Luis
Reviewed-by: Ani Sinha
---
hw/arm/virt-acpi-build.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 9b3aee01bf..13c6e3e468 100644
--
> On 21 Sep 2022, at 03:39, Ani Sinha wrote:
>
>
>
> On Tue, 20 Sep 2022, Miguel Luis wrote:
>
>> Step 6 & 7 of the bios-tables-test.c documented procedure.
>>
>> Differences between disassembled ASL files for GTDT:
>>
&
Hi Ani,
> On 7 Oct 2022, at 04:25, Ani Sinha wrote:
>
>
>
> On Thu, 6 Oct 2022, Miguel Luis wrote:
>
>> Update the Fixed ACPI Description Table (FADT) to revision 6.0 of the ACPI
>> specification adding the field "Hypervisor Vendor Identity" that was
0 00 00 00 00 //
-0100: 00 00 00 00 00 00 00 00 00 00 00 00 //
+0100: 00 00 00 00 00 00 00 00 00 00 00 00 74 63 67 00 // tcg.
+0110: 00 00 00 00 //
Signed-off-by: Miguel Luis
---
tests/
MADT has been updated with the GIC Structures from ACPI 6.0 Errata A
and so MADT revision and GICC Structure must be updated also.
Fixes: 37f33084ed2e ("acpi: arm/virt: madt: use build_append_int_noprefix() API
to compose MADT table")
Signed-off-by: Miguel Luis
---
hw/arm/virt-ac
leration name. This would
provide values like 'KVM' for example when KVM is used.
Ref: https://uefi.org/sites/default/files/resources/ACPI_6_0_Errata_A.PDF
Open to discussion, your comments, thoughts and suggestions are very welcome.
Thanks in advance.
Miguel
Miguel Luis (4):
tests/a
provide that information?
On this RFC there's the suggestion of having this information in sync by the
current acceleration name. This also seems to imply that QEMU, which generates
the FADT table, and the FADT consumer need to be in sync with the values of this
field.
Signed-off-by: Mi
Step 3 from bios-tables-test.c documented procedure.
Signed-off-by: Miguel Luis
---
tests/qtest/bios-tables-test-allowed-diff.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b
Step 3 from bios-tables-test.c documented procedure.
Signed-off-by: Miguel Luis
---
tests/qtest/bios-tables-test-allowed-diff.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b
00 00 00 00 00 00 00 1A 00 00 00 00 00 00 00 //
-0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 //
+0050: FF FF FF FF FF FF FF FF 00 00 00 00 00 00 00 00 //
Signed-off-by: Miguel Luis
---
tests/data/acpi/virt/GTDT
begin()/acpi_table_end() instead of build_header()")
Signed-off-by: Miguel Luis
---
hw/arm/virt-acpi-build.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 9b3aee01bf..13c6e3e468 100644
--- a/hw/arm/virt-acpi-bui
0x0.
[1]:
https://uefi.org/specs/ACPI/6.5/05_ACPI_Software_Programming_Model.html#gtdt-table-structure
Miguel Luis (3):
tests/acpi: virt: allow acpi GTDT changes
acpi: arm/virt: build_gtdt: fix invalid 64-bit physical addresses
tests/acpi: virt: update ACPI GTDT binaries
hw/arm/virt-acpi
From: Daniel Henrique Barboza
> Subject: [PATCH] ppc/pvn.c: fix "system-id" FDT when -uuid is set
I don't know enough to review this, but there's a typo on the commit message
(pvn.c -> pnv.c). :)
--
Luis Pires
Instituto de Pesquisas ELDORADO
Aviso
eve these should be marked as false positives.
We *could* also wrap set_dfp{64,128} in new macros that would then reference
only the appropriate parts of dfp, but, in this case, I don't think it's worth
the trouble.
Thanks,
--
Luis Pires
Instituto de Pesquisas ELDORADO
Aviso Le
On 11/5/21 1:15 PM, Alex Bennée wrote:
Luis Machado writes:
On 11/4/21 6:03 PM, Luis Machado wrote:
On 10/4/21 3:44 PM, Luis Machado wrote:
Hi,
On 9/21/21 10:55 AM, Peter Maydell wrote:
On Tue, 19 Jan 2021 at 15:57, Alex Bennée
wrote:
Claudio Fontana writes:
On 1/19/21 3:50 PM
On 11/4/21 6:03 PM, Luis Machado wrote:
On 10/4/21 3:44 PM, Luis Machado wrote:
Hi,
On 9/21/21 10:55 AM, Peter Maydell wrote:
On Tue, 19 Jan 2021 at 15:57, Alex Bennée
wrote:
Claudio Fontana writes:
On 1/19/21 3:50 PM, Alex Bennée wrote:
Claudio Fontana writes:
qemu-system-aarch64
On 10/4/21 3:44 PM, Luis Machado wrote:
Hi,
On 9/21/21 10:55 AM, Peter Maydell wrote:
On Tue, 19 Jan 2021 at 15:57, Alex Bennée wrote:
Claudio Fontana writes:
On 1/19/21 3:50 PM, Alex Bennée wrote:
Claudio Fontana writes:
qemu-system-aarch64: -gdb
unix:path=/tmp/tmp9ru5tgk8qemu
Convert To Fixed Quad
dxex:DFP Extract Biased Exponent
dxexq: DFP Extract Biased Exponent Quad
Signed-off-by: Luis Pires
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
target/ppc/dfp_helper.c | 20 +--
target/ppc/helper.h | 20
Move the following instructions to decodetree:
dtstdc: DFP Test Data Class
dtstdcq: DFP Test Data Class Quad
dtstdg: DFP Test Data Group
dtstdgq: DFP Test Data Group Quad
Signed-off-by: Luis Pires
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
target/ppc/dfp_helper.c
Move the following instructions to decodetree:
dqua: DFP Quantize
dquaq: DFP Quantize Quad
drrnd: DFP Reround
drrndq: DFP Reround Quad
Signed-off-by: Luis Pires
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
target/ppc/dfp_helper.c | 8 ++---
target
Without Inexact Quad
Signed-off-by: Luis Pires
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
target/ppc/dfp_helper.c | 12 +++
target/ppc/helper.h | 12 +++
target/ppc/insn32.decode| 23 +
target/ppc/translate/dfp
Implement the following PowerISA v3.1 instruction:
dcffixqq: DFP Convert From Fixed Quadword Quad
Signed-off-by: Luis Pires
Reviewed-by: Richard Henderson
---
target/ppc/dfp_helper.c | 12
target/ppc/helper.h | 1 +
target/ppc/insn32.decode
This will be used to implement PowerPC's dcffixqq.
Signed-off-by: Luis Pires
Reviewed-by: Richard Henderson
---
include/libdecnumber/decNumber.h | 2 ++
libdecnumber/decNumber.c | 36
2 files changed, 38 insertions(+)
diff --git a/include/libdecn
Implement the following PowerISA v3.1 instruction:
dctfixqq: DFP Convert To Fixed Quadword Quad
Signed-off-by: Luis Pires
Reviewed-by: Richard Henderson
---
target/ppc/dfp_helper.c | 52 +
target/ppc/helper.h | 1 +
target/ppc/insn32
-by: Luis Pires
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
target/ppc/dfp_helper.c | 20 +--
target/ppc/helper.h | 20 +--
target/ppc/insn32.decode| 31 ++--
target/ppc/translate/dfp-impl.c.inc | 56
decNumberIntegralToInt128
Changes in v2:
- Renamed abs64() to uabs64()
Bruno Larsen (1):
target/ppc: Move REQUIRE_ALTIVEC/VECTOR to translate.c
Fernando Valle (1):
target/ppc: Introduce REQUIRE_FPU
Luis Pires (13):
libdecnumber: introduce decNumberFrom[U]Int128
target/ppc: Implement DCFFIXQ
This will be used to implement PowerPC's dctfixqq.
Signed-off-by: Luis Pires
Reviewed-by: Richard Henderson
---
include/libdecnumber/decNumber.h | 2 +
include/libdecnumber/decNumberLocal.h | 2 +-
libdecnumber/decContext.c | 7 +-
libdecnumber/decNumber.c
Before moving the existing DFP instructions to decodetree, drop the
nip update that shouldn't be done for these instructions.
Signed-off-by: Luis Pires
Reviewed-by: Richard Henderson
---
target/ppc/translate/dfp-impl.c.inc | 8
1 file changed, 8 deletions(-)
diff --git a/targe
Significand Right Immediate
dscriq: DFP Shift Significand Right Immediate Quad
Also deleted dfp-ops.c.inc, now that all PPC DFP instructions were
moved to decodetree.
Signed-off-by: Luis Pires
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
target/ppc/dfp_helper.c
From: Fernando Valle
Signed-off-by: Fernando Valle
Signed-off-by: Luis Pires
Reviewed-by: Richard Henderson
---
target/ppc/translate.c | 8
1 file changed, 8 insertions(+)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index c2fafebd1c..48a484eef6 100644
--- a/target
Signed-off-by: Luis Pires
Reviewed-by: Richard Henderson
---
include/qemu/host-utils.h | 36
1 file changed, 36 insertions(+)
diff --git a/include/qemu/host-utils.h b/include/qemu/host-utils.h
index a3a7ced78d..ca979dc6cc 100644
--- a/include/qemu/host
Significance Quad
dtstsfi: DFP Test Significance Immediate
dtstsfiq: DFP Test Significance Immediate Quad
Signed-off-by: Luis Pires
Reviewed-by: Richard Henderson
---
target/ppc/dfp_helper.c | 20
target/ppc/helper.h | 20
target/ppc/insn32.decode
From: Bruno Larsen
Move REQUIRE_ALTIVEC to translate.c and rename it to REQUIRE_VECTOR.
Signed-off-by: Bruno Larsen
Signed-off-by: Matheus Ferst
Signed-off-by: Fernando Valle
Signed-off-by: Luis Pires
Reviewed-by: Richard Henderson
Acked-by: David Gibson
---
target/ppc/translate.c
es
>
>
> r~
>
> ---
> tcg/tcg.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
Reviewed-by: Luis Pires
--
Luis Pires
Instituto de Pesquisas ELDORADO
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
On 10/20/21 10:16 AM, LEROY Christophe wrote:
Le 20/10/2021 à 14:43, Cédric Le Goater a écrit :
On 10/20/21 13:42, BALATON Zoltan wrote:
On Wed, 20 Oct 2021, Philippe Mathieu-Daudé wrote:
On 10/5/21 14:29, Thomas Huth wrote:
On 05/10/2021 14.20, BALATON Zoltan wrote:
On Tue, 5 Oct 2021,
llowing the final extend to be eliminated.
>
> Reviewed-by: Alex Bennée
> Signed-off-by: Richard Henderson
> ---
> tcg/optimize.c | 50 +++--
> -
> 1 file changed, 47 insertions(+), 3 deletions(-)
Reviewed-by: Luis Pires
--
Lui
optimize.c | 2 ++
> 1 file changed, 2 insertions(+)
Reviewed-by: Luis Pires
--
Luis Pires
Instituto de Pesquisas ELDORADO
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
nged, 2 insertions(+), 1 deletion(-)
Reviewed-by: Luis Pires
--
Luis Pires
Instituto de Pesquisas ELDORADO
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
gt; Reviewed-by: Alex Bennée
> Signed-off-by: Richard Henderson
> ---
> tcg/optimize.c | 123 -
> 1 file changed, 102 insertions(+), 21 deletions(-)
Reviewed-by: Luis Pires
--
Luis Pires
Instituto de Pesquisas ELDORAD
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