gt; @@ -70,6 +69,7 @@ def test_sbsaref_edk2_firmware(self):
> >
> > fetch_firmware(self)
> >
> > +self.set_machine('sbsa-ref')
> > self.vm.add_args('-cpu', 'cortex-a57')
> > self.vm.launch()
>
> Sorry, last patch, I f
than 8 TiB of RAM
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Leif Lindholm
/
Leif
> ---
> hw/arm/sbsa-ref.c | 8 +---
> 1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
> index deae5cf9861..3b
On Thu, 12 Jun 2025 at 16:17, Jonathan Cameron
wrote:
> On Fri, 30 May 2025 18:54:30 +0800
> wangyuquan wrote:
> > Dynamic cxl topology problem
> >
> > Actually the ideal expectation is sbsa-ref could also have a dynamic cxl
> > topology by user
> > parameters. Accor
Doh! Add the lists back in. (No idea how I dropped them off.)
On Mon, 3 Mar 2025 at 17:02, Leif Lindholm
wrote:
>
> Hi Kun,
>
> Apologies for delay in responding - I was out last week.
> I agree with this addition, since a TPM is a requirement for servers.
>
> However, to
Juszkiewicz
Reviewed-by: Leif Lindholm
> ---
> MAINTAINERS | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 822f34344b..776e0b997d 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -918,7 +918,6 @@ SBSA-REF
> M: Radoslaw
On Fri, 13 Dec 2024 at 19:30, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
For sbsa:
Reviewed-by: Leif Lindholm
/
Leif
> ---
> hw/watchdog/sbsa_gwdt.c | 2 +-
> hw/watchdog/wdt_aspeed.c | 2 +-
> hw/watchdog/wdt_imx2.c | 2 +-
> 3 files change
(oops, +Marcin)
On 2024-12-05 11:40, Leif Lindholm wrote:
From: Leif Lindholm
I'm migrating to Qualcomm's new open source email infrastructure, so
update my email address, and update the mailmap to match.
Signed-off-by: Leif Lindholm
Reviewed-by: Leif Lindholm
---
.mail
From: Leif Lindholm
I'm migrating to Qualcomm's new open source email infrastructure, so
update my email address, and update the mailmap to match.
Signed-off-by: Leif Lindholm
---
.mailmap| 5 +++--
MAINTAINERS | 2 +-
2 files changed, 4 insertions(+), 3 deletions(-)
di
ferent platform this could feel quite hacky, but in
reality even 2GB falls within "ridiculously low for an SBSA platform".
If we're worried about overhead for CI jobs that do not require the
feature, we could always conditionalize it on RME being enabled. But I'd
be happy t
: Marcin Juszkiewicz
Reviewed-by: Leif Lindholm
Thanks!
---
docs/system/arm/sbsa.rst | 4
hw/arm/sbsa-ref.c| 11 ++-
2 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/docs/system/arm/sbsa.rst b/docs/system/arm/sbsa.rst
index 2bf22a1d0b..2bf3fc8d59 100644
On 2024-05-31 10:37, Marcin Juszkiewicz wrote:
Updated firmware for QEMU CI is already in merge queue so we can move
platform to be future proof.
All supported cpus work fine with 1GHz timer frequency when firmware is
fresh enough.
Signed-off-by: Marcin Juszkiewicz
Reviewed-by: Leif
chain (gcc 12.2.0).
Missing signoff?
Apart from that:
Reviewed-by: Leif Lindholm
---
tests/avocado/machine_aarch64_sbsaref.py | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/tests/avocado/machine_aarch64_sbsaref.py
b/tests/avocado/machine_aarch64_sbsare
for "max" as default to have stable set of features enabled
by default. It is still supported and can be selected with "--cpu"
argument.
I still want to move to max at some point :)
But this is a good improvement for now.
Reviewed-by: Leif Lindholm
Signed-off-by: Marcin J
d provides only data we use in firmware.
>
> Added NUMA information to list of things reported by DeviceTree.
>
> Signed-off-by: Marcin Juszkiewicz
Reviewed-by: Leif Lindholm
Thanks!
/
Leif
> ---
> docs/system/arm/sbsa.rst | 35 ++-
>
for that aspect:
Reviewed-by: Leif Lindholm
/
Leif
hw/ide/ahci-allwinner.c| 3 +--
hw/ide/ahci.c | 1 +
9 files changed, 43 insertions(+), 34 deletions(-)
create mode 100644 include/hw/ide/ahci-sysbus.h
diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/ar
On Sun, Oct 22, 2023 at 16:51:23 +0100, David Woodhouse wrote:
> From: David Woodhouse
>
> Signed-off-by: David Woodhouse
Reviewed-by: Leif Lindholm
> ---
> hw/arm/sbsa-ref.c | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/hw/arm/sbsa-r
ponent does not
necessarily want/need the same maintainers as the sbsa-ref platform.
I'm still happy to maintain it, and it may make sense to keep it under
this header for now.
(In which case
Reviewed-by: Leif Lindholm
)
Regards,
Leif
> F: docs/system/arm/sbsa.rst
> F: tests/avocado/machine_aarch64_sbsaref.py
>
> --
> 2.41.0
>
On 2023-09-19 11:12, Peter Maydell wrote:
This patchset is an RFC that wires up the NS EL2 virtual timer IRQ on
the virt board, similarly to what
https://patchew.org/QEMU/20230913140610.214893-1-marcin.juszkiew...@linaro.org/
does for the sbsa-ref board.
Patches 1 and 3 are the usual dance to ke
uired.
Signed-off-by: Leif Lindholm
---
hw/arm/virt-acpi-build.c | 12 ++--
hw/arm/virt.c| 24 ++--
include/hw/arm/virt.h| 14 +++---
3 files changed, 27 insertions(+), 23 deletions(-)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-bu
virt.h defines a number of IRQs that are ultimately described by Arm's
Base System Architecture specification. Move these to a dedicated header
so that they can be reused by other platforms that do the same.
Include that header from virt.h to minimise churn.
Signed-off-by: Leif Lin
ation instead of doing the
translation, as suggested by Peter.
- Added explicit comment that listed IDs are INTIDs.
Changes since RFC:
- Compilation tested
- Reordered patches 1-2 as suggested by Philippe.
Leif Lindholm (3):
{include/}hw/arm: refactor virt PPI logic
include/hw/arm: mov
Use the private peripheral interrupt definitions from bsa.h instead of
defining them locally. Refactor to use the INTIDs defined there instead
of the PPI# used previously.
Signed-off-by: Leif Lindholm
---
hw/arm/sbsa-ref.c | 20 +---
1 file changed, 9 insertions(+), 11 deletions
same header instead of defining its own values
locally.
Changes since RFC:
- Compilation tested
- Reordered patches 1-2 as suggested by Philippe.
Leif Lindholm (3):
{include/}hw/arm: refactor virt PPI logic
include/hw/arm: move BSA definitions to bsa.h
hw/arm/sbsa-ref: use bsa.h for PPI defini
Use the private peripheral interrupt definitions from bsa.h instead of
defining them locally. Refactor to use PPI() to convert from INTID macro
where necessary.
Signed-off-by: Leif Lindholm
---
hw/arm/sbsa-ref.c | 23 +++
1 file changed, 11 insertions(+), 12 deletions
On Fri, Sep 15, 2023 at 13:35:19 +0200, Marcin Juszkiewicz wrote:
> Update prebuilt firmware images to have TF-A with Neoverse V1 support enabled.
> This allowed us to enable test for this cpu in sbsa-ref machine.
>
> Signed-off-by: Marcin Juszkiewicz
Acked-by: Leif Lindholm
&g
used.
Signed-off-by: Leif Lindholm
---
hw/arm/virt-acpi-build.c | 4 ++--
hw/arm/virt.c| 9 +
include/hw/arm/virt.h| 14 +++---
3 files changed, 14 insertions(+), 13 deletions(-)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 6b674231c2..963c5
virt.h defines a number of IRQs that are ultimately described by Arm's
Base System Architecture specification. Move these to a dedicated header
so that they can be reused by other platforms that do the same.
Include that header from virt.h to minimise churn.
Signed-off-by: Leif Lin
On 2023-09-14 14:15, Marcin Juszkiewicz wrote:
W dniu 14.09.2023 o 14:01, Leif Lindholm pisze:
While reviewing Marcin's patch this morning, cross referencing different
specifications and looking at various places around the source code in
order to convinced myself he really hadn
used.
Signed-off-by: Leif Lindholm
---
hw/arm/virt-acpi-build.c | 4 ++--
hw/arm/virt.c| 9 +
include/hw/arm/bsa.h | 14 +++---
3 files changed, 14 insertions(+), 13 deletions(-)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 6b674231c2..963c5
Use the private peripheral interrupt definitions from bsa.h instead of
defining them locally. Refactor to use PPI() to convert from INTID macro
where necessary.
Signed-off-by: Leif Lindholm
---
hw/arm/sbsa-ref.c | 24 +++-
1 file changed, 11 insertions(+), 13 deletions
virt.h defines a number of IRQs that are ultimately described by Arm's
Base System Architecture specification. Move these to a dedicated header
so that they can be reused by other platforms that do the same.
Include that header from virt.h to minimise churn.
Signed-off-by: Leif Lin
ovement to me.
Not even compilation tested, just the least confusing way of asking
whether the change could be accepted at all.
Leif Lindholm (3):
include/hw/arm: move BSA definitions to bsa.h
{include/}hw/arm: refactor BSA/virt PPI logic
hw/arm/sbsa-ref: use bsa.h for PPI definitions
h
On Thu, Sep 07, 2023 at 10:35:51 +1000, Gavin Shan wrote:
> Set mc->valid_cpu_types so that the user specified CPU type can
> be validated in machine_run_board_init(). We needn't to do it
> by ourselves.
>
> Signed-off-by: Gavin Shan
Reviewed-by: Leif Lindholm
> ---
On 2023-06-27 15:27, Peter Maydell wrote:
Serious question: would it be preferable if we moved to a custom DT node
where we stick everything in as KEY=VALUE pairs to reduce this confusion?
I don't really mind, I just want it to be clear what is going on here
so that when I'm reviewing patches I
On 2023-06-27 14:27, Peter Maydell wrote:
On Tue, 27 Jun 2023 at 13:52, Leif Lindholm wrote:
On 2023-06-27 13:12, Peter Maydell wrote:
On Mon, 26 Jun 2023 at 08:52, Marcin Juszkiewicz
wrote:
Add PCI Express information into DeviceTree as part of SBSA-REF
versioning.
Trusted Firmware will
On 2023-06-27 13:12, Peter Maydell wrote:
On Mon, 26 Jun 2023 at 08:52, Marcin Juszkiewicz
wrote:
Add PCI Express information into DeviceTree as part of SBSA-REF
versioning.
Trusted Firmware will read it and provide to next firmware level.
Signed-off-by: Marcin Juszkiewicz
---
hw/arm/sbsa
Hi Peter,
On 2023-06-19 13:47, Peter Maydell wrote:
On Wed, 7 Jun 2023 at 03:34, Yuquan Wang wrote:
The current sbsa-ref cannot use EHCI controller which is only
able to do 32-bit DMA, since sbsa-ref doesn't have RAM below 4GB.
Hence, this uses system bus XHCI to provide a usb controller with
Hi Yuquan,
On Fri, Jun 02, 2023 at 11:24:11 +0800, Yuquan Wang wrote:
> > > > To skip the migration hazard, my prefernece is we just leave the EHCI
> > > > device in for now, and add a separate XHCI on PCIe. We can drop the
> > > > EHCI device at some point in the future.
> > >
> > > Why PCIe for
+Ard
On Thu, Jun 01, 2023 at 16:01:43 +0100, Peter Maydell wrote:
> > >> Also has EHCI never worked, or has it worked in some modes and so this
> > >> change should be versioned?
> > >
> > > AIUI, EHCI has never worked and can never have worked, because
> > > this board's RAM is all above 4G and t
On 2023-05-31 16:27, Peter Maydell wrote:
On Wed, 31 May 2023 at 15:58, Graeme Gregory wrote:
The current sbsa-ref cannot use EHCI controller which is only
able to do 32-bit DMA, since sbsa-ref doesn't have RAM above 4GB.
Hence, this uses XHCI to provide a usb controller with 64-bit
DMA capabli
Reviewed-by: Leif Lindholm
---
hw/arm/sbsa-ref.c | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index 792371fdce..9204e8605f 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -29,6 +29,7 @@
#include "
On 2023-05-05 13:09, Marcin Juszkiewicz wrote:
Bochs card is normal PCI Express card so it fits better in system with
PCI Express bus. VGA is simple legacy PCI card.
Signed-off-by: Marcin Juszkiewicz
Reviewed-by: Leif Lindholm
---
hw/arm/sbsa-ref.c | 2 +-
1 file changed, 1 insertion
On 2023-05-15 11:15, Peter Maydell wrote:
On Mon, 15 May 2023 at 11:04, Marcin Juszkiewicz
wrote:
Let add GIC information into DeviceTree as part of SBSA-REF versioning.
Trusted Firmware will read it and provide to next firmware level.
Bumps platform version to 0.1 one so we can check is nod
mc->minimum_page_bits = 12;
Seems reasonable; Leif, any objection?
None.
Longer-term, I still want to move to "max" as the default, but that is
likely to require some invasive changes to TF-A, and this is already a
huge improvement. So:
Reviewed-by: Leif Lindholm
Thanks!
/
Leif
traditional nitpick and ask this to be added above
sysemu/numa.h in order to maintain alphabetical ordering within the
sysemu block?
With that:
Reviewed-by: Leif Lindholm
> #include "exec/hwaddr.h"
> #include "kvm_arm.h"
> #include "hw/arm/boot.h"
> --
> 2.38.1
>
> To unify tests for AArch64/virt and AArch64/sbsa-ref we boot
> the same Alpine Linux image on both.
>
> Signed-off-by: Marcin Juszkiewicz
> Signed-off-by: Philippe Mathieu-Daudé
> Message-Id: <20230323082813.971535-1-marcin.juszkiew...@linaro.org>
Thanks for this.
From: Leif Lindholm
Due to a change in upstream TF-A, boot fails (in edk2) on all cpus that
don't implement FEAT_DIT. The only currently emulated cpu that "supports"
this feature is "max". So switch to using that cpu by default for
sbsa-ref.
However, it is worth
From: Leif Lindholm
We have mainly (well, as will become clear, in fact "exclusively") been using
sbsa-ref with the "max" CPU. But sbsa-ref was created with a default CPU of
Cortex-A57, which we have not updated along the way.
However, the "max" cpu has seen a bug
Hi everyone,
As some of you might have noticed, my email setup broke a little over
a month ago. At the time I was on leave, so did not notice for a
while. And upon my return, it turned out it had broken in New and
Exciting ways - so it took some time to restore.
This has now been achieved, and I
revision ID register found on a physical platform.
These properties are both introduced with the value 0.
(Hence, a machine where the DT is lacking these nodes is equivalent
to version 0.0.)
Signed-off-by: Leif Lindholm
Cc: Peter Maydell
Cc: Radoslaw Biernacki
Cc: Cédric Le Goater
NUVIA was acquired by Qualcomm in March 2021, but kept functioning on
separate infrastructure for a transitional period. We've now switched
over to contributing as Qualcomm Innocation Center (quicinc), so update
my email address to reflect this.
Signed-off-by: Leif Lindholm
Cc: Leif Lindhol
On Fri, Apr 29, 2022 at 09:17:09 +0200, Cédric Le Goater wrote:
> > Signed-off-by: Leif Lindholm
> > Cc: Peter Maydell
> > Cc: Radoslaw Biernacki
> > Cc: Cédric Le Goater
> > ---
> > hw/arm/sbsa-ref.c | 3 +++
> > 1 file changed, 3 insertions(+)
&g
On Thu, Apr 28, 2022 at 13:46:36 +0100, Peter Maydell wrote:
> On Wed, 27 Apr 2022 at 19:13, Leif Lindholm wrote:
> >
> > NUVIA was acquired by Qualcomm in March 2021, but kept functioning on
> > separate infrastructure for a transitional period. We've now switched
&
Hi Cedric,
On Thu, Apr 28, 2022 at 10:55:54 +0200, Cédric Le Goater wrote:
> > The sbsa-ref machine is continuously evolving. Some of the changes we
> > want to make in the near future, to align with real components (e.g.
> > the GIC-700), will break compatibility for existing firmware.
> >
> > I
incremented.
These properties are both introduced with the value 0.
(Hence, a machine where the DT is lacking these nodes is equivalent
to version 0.0.)
Signed-off-by: Leif Lindholm
Cc: Peter Maydell
Cc: Radoslaw Biernacki
Cc: Cédric Le Goater
---
hw/arm/sbsa-ref.c | 3 +++
1 file changed, 3
NUVIA was acquired by Qualcomm in March 2021, but kept functioning on
separate infrastructure for a transitional period. We've now switched
over to contributing as Qualcomm Innocation Center (quicinc), so update
my email address to reflect this.
Signed-off-by: Leif Lindholm
Cc: Leif Lindhol
On Wed, Apr 27, 2022 at 7:13 PM Leif Lindholm
wrote:
>
> NUVIA was acquired by Qualcomm in March 2021, but kept functioning on
> separate infrastructure for a transitional period. We've now switched
> over to contributing as Qualcomm Innocation Center (quicinc), so update
>
On Thu, Nov 11, 2021 at 16:55:09 +, Peter Maydell wrote:
> On Tue, 9 Nov 2021 at 22:52, Leif Lindholm wrote:
> >
> > On Tue, Nov 09, 2021 at 21:21:46 +, Peter Maydell wrote:
> > > The other thing we should nail down is how the user is going to
> > > sel
On Tue, Nov 09, 2021 at 21:21:46 +, Peter Maydell wrote:
> > Hmm, right. So you're thinking containing the versioning fully in the
> > interfaces presented by the model:
> > - Is the version node present?
> > - If so, is it greater than X?
> > - If so, is it great enough to support the SC
On Tue, Nov 09, 2021 at 13:43:50 +, Peter Maydell wrote:
> On Fri, 15 Oct 2021 at 13:23, Leif Lindholm wrote:
> > (Apologies for delay. Alex also tells me you are currently away, but
> > there is no strong urgency here.)
>
> (Thanks for the ping via Alex -- I missed
Hi Peter,
(Apologies for delay. Alex also tells me you are currently away, but
there is no strong urgency here.)
On Thu, Sep 23, 2021 at 17:00:35 +0100, Peter Maydell wrote:
> > If we assume that we don't want to further complicate this set by
> > adding the additional logic *now*, I see three op
Hi Peter,
On Tue, Sep 07, 2021 at 12:00:45 +0100, Peter Maydell wrote:
> On Thu, 2 Sept 2021 at 09:23, Li, Chunming
> wrote:
> > Eric Auger wrote:
> >> On 9/2/21 8:46 AM, Li, Chunming wrote:
> >>> Eric Auger wrote:
>
> Then I think you need to bring a proper motivation behind adding the
>
On Thu, Sep 02, 2021 at 13:51:26 +0100, Peter Maydell wrote:
> On Thu, 2 Sept 2021 at 13:43, Leif Lindholm wrote:
> > On Thu, Aug 19, 2021 at 14:27:19 +0100, Peter Maydell wrote:
> > > If you want a command line switch to let the user say whether the
> > > ITS should be
Hi Peter,
On Thu, Aug 19, 2021 at 14:27:19 +0100, Peter Maydell wrote:
> On Thu, 12 Aug 2021 at 17:53, Shashi Mallela
> wrote:
> >
> > Included creation of ITS as part of SBSA platform GIC
> > initialization.
> >
> > Signed-off-by: Shashi Mallela
> > ---
> > hw/arm/sbsa-ref.c | 79
; exit with a hopefully helpful error message.
>
> Because we now handle this check in a machine-agnostic way, we
> can remove the check from sbsa-ref.
>
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/503
> Signed-off-by: Peter Maydell
Reviewed-by: Leif Lindho
On Thu, Jul 08, 2021 at 21:05:02 +0100, Peter Maydell wrote:
> On Thu, 8 Jul 2021 at 20:40, Leif Lindholm wrote:
> > I think my summary-summary would be:
> > - I think we will need to introduce a compatiblity-breaking change to
> > sbsa-ref.
> > - I think we will ne
:00 +0100, Leif Lindholm wrote:
> On Fri, Jun 04, 2021 at 11:36:02 -0400, shashi.mall...@linaro.org wrote:
> > On Fri, 2021-06-04 at 11:42 +0100, Leif Lindholm wrote:
> > > On Thu, Jun 03, 2021 at 11:31:21 -0400, shashi.mall...@linaro.org
> > > wrote:
> > > >
On Thu, Jun 03, 2021 at 11:31:21 -0400, shashi.mall...@linaro.org wrote:
> On Thu, 2021-06-03 at 12:42 +0100, Leif Lindholm wrote:
> > On Wed, Jun 02, 2021 at 14:00:41 -0400, Shashi Mallela wrote:
> > > Included creation of ITS as part of SBSA platform GIC
> > > initiali
On Wed, Jun 02, 2021 at 14:00:41 -0400, Shashi Mallela wrote:
> Included creation of ITS as part of SBSA platform GIC
> initialization.
>
> Signed-off-by: Shashi Mallela
> ---
> hw/arm/sbsa-ref.c | 26 +++---
> 1 file changed, 23 insertions(+), 3 deletions(-)
>
> diff --git
On Thu, Mar 04, 2021 at 15:14:36 +, Peter Maydell wrote:
> On Thu, 4 Mar 2021 at 13:53, Leif Lindholm wrote:
> >
> > On Wed, Mar 03, 2021 at 18:06:46 +, Peter Maydell wrote:
> > > On Wed, 3 Mar 2021 at 17:48, Leif Lindholm wrote:
> > > > It would b
On Wed, Mar 03, 2021 at 18:06:46 +, Peter Maydell wrote:
> On Wed, 3 Mar 2021 at 17:48, Leif Lindholm wrote:
> > It would be good if we could get 6.0 closer to SBSA compliance.
>
> How far away are we at the moment ?
>
> > Would it be worth the effort to make this co
ble PMU counters.
>
> So let make QEMU provide those 6 PMU counters.
>
> SBSA-ACS says now:
>
> 12 : Check number of PMU counters : Result: PASS
>
> Signed-off-by: Marcin Juszkiewicz
Reviewed-by: Leif Lindholm
It would be good if we could get 6.0 close
On Fri, Feb 19, 2021 at 12:08:05 +, Peter Maydell wrote:
> On Fri, 19 Feb 2021 at 11:58, Daniel P. Berrangé wrote:
> > Is the behaviour reported really related to KVM specifically, as opposed
> > to all hardware based virt backends ?
> >
> > eg is it actually a case of some machine types being
On Thu, Feb 11, 2021 at 13:36:37 +0100, Marcin Juszkiewicz wrote:
> Cortex-A53 supports 40bits of address space. sbsa-ref's memory starts
> above this limit.
>
> Signed-off-by: Marcin Juszkiewicz
Acked-by: Leif Lindholm
> ---
> hw/arm/sbsa-ref.c | 1 -
>
On Thu, Feb 11, 2021 at 13:36:38 +0100, Marcin Juszkiewicz wrote:
> Let add 'max' cpu while work goes on adding newer CPU types than
> Cortex-A72. This allows us to check SVE etc support.
>
> Signed-off-by: Marcin Juszkiewicz
Acked-by: Leif Lindholm
> ---
> hw/ar
On Tue, Feb 02, 2021 at 10:39:22 +, Peter Maydell wrote:
> On Sun, 24 Jan 2021 at 02:53, Leif Lindholm wrote:
> >
> > GICv4 sets aside 256K per redistributor configuration block, whereas GICv3
> > only uses 128K. However, some codebases (like TF-A, EDK2) will happ
On Tue, Feb 02, 2021 at 10:31:16 +, Peter Maydell wrote:
> On Sun, 24 Jan 2021 at 02:53, Leif Lindholm wrote:
> >
> > Make gicv3_idreg() able to return either gicv3 or gicv4 data.
> > Add a parameter to specify gic version.
> >
> > Signed-off-by: Le
The VLPI frames are what make the redistributor size change, so ensure
we state in GICD_TYPER that we have them.
Signed-off-by: Leif Lindholm
---
hw/intc/arm_gicv3_dist.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/intc/arm_gicv3_dist.c b/hw/intc/arm_gicv3_dist.c
index b65f56f903
GICv3 sets aside 128K for each redistributor block, whereas GICv4 sets
aside 256K. To enable use of the gicv3 model for gicv4, abstract this
away as the helper function gicv3_redist_size() and replace the current
hardcoded locations with calls to this function.
Signed-off-by: Leif Lindholm
Make gicv3_idreg() able to return either gicv3 or gicv4 data.
Add a parameter to specify gic version.
Signed-off-by: Leif Lindholm
---
hw/intc/arm_gicv3_dist.c | 2 +-
hw/intc/arm_gicv3_redist.c | 2 +-
hw/intc/gicv3_internal.h | 12 ++--
3 files changed, 12 insertions(+), 4
... problematic ... system, which will misbehave if you try
to use the virtual LPIs. But it does help with letting me use QEMU for
modelling a platform containing a GICv4, and share firmware images with
other prototyping platforms.
Leif Lindholm (4):
hw/intc: don't bail out gicv3 model ini
As a first step towards GICv4 compatibility, add support for gic revision 4
to GICv3 driver (i.e. don't bail out if revision 4 is encountered).
Signed-off-by: Leif Lindholm
---
hw/intc/arm_gicv3_common.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw
Add entries present in ARM DDI 0487F.c (August 2020).
Signed-off-by: Leif Lindholm
Reviewed-by: Peter Maydell
Reviewed-by: Laurent Desnogues
---
target/arm/cpu.h | 28
1 file changed, 28 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index
Signed-off-by: Leif Lindholm
---
target/arm/cpu.h | 31 +++
1 file changed, 31 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 063228de2a..18c1cb02bb 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1736,6 +1736,37 @@ FIELD(V7M_FPCCR
When FEAT_MTE is implemented, the AArch64 view of CTR_EL0 adds the
TminLine field in bits [37:32].
Extend the ctr field to be able to hold this context.
Signed-off-by: Leif Lindholm
---
target/arm/cpu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/cpu.h b
nition for CCSIDR_EL1 fields when FEAT_CCIDX implemented.
- Add patch extending also ARMCPU.ctr to 64-bit.
- Rebase to current master.
v1->v2:
- Correct CCSIDR_EL1 field sizes in 3/5.
- Rebase to current master.
Leif Lindholm (6):
target/arm: fix typo in cpu.h ID_AA64PFR1 field name
target/
Add entries present in ARM DDI 0487F.c (August 2020).
Signed-off-by: Leif Lindholm
Reviewed-by: Peter Maydell
Reviewed-by: Laurent Desnogues
---
target/arm/cpu.h | 15 +++
1 file changed, 15 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 18c1cb02bb
The AArch64 view of CLIDR_EL1 extends the ICB field to include also bit
32, as well as adding a Ttype field when FEAT_MTE is implemented.
Extend the clidr field to be able to hold this context.
Signed-off-by: Leif Lindholm
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
Reviewed
SBSS -> SSBS
Signed-off-by: Leif Lindholm
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
Reviewed-by: Laurent Desnogues
---
target/arm/cpu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 7e6c881a7e..5e3cf77
On Thu, Dec 17, 2020 at 13:18:03 +0100, Laurent Desnogues wrote:
> On Thu, Dec 17, 2020 at 1:10 PM Leif Lindholm wrote:
> [...]
> > > > > > +FIELD(CCSIDR_EL1, LINESIZE, 0, 3)
> > > > > > +FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 21)
>
Hi Laurent,
On Thu, Dec 17, 2020 at 11:02:23 +0100, Laurent Desnogues wrote:
> Hi Leif,
>
> On Tue, Dec 15, 2020 at 5:49 PM Leif Lindholm wrote:
> >
> > On Tue, Dec 15, 2020 at 13:23:58 +0100, Laurent Desnogues wrote:
> > > Hello,
> > >
> > >
On Tue, Dec 15, 2020 at 13:23:58 +0100, Laurent Desnogues wrote:
> Hello,
>
> On Tue, Dec 15, 2020 at 12:51 PM Leif Lindholm wrote:
> >
> > Signed-off-by: Leif Lindholm
> > ---
> > target/arm/cpu.h | 24
> > 1 file changed, 24 in
On Tue, Dec 15, 2020 at 12:11:43 +, Peter Maydell wrote:
> On Tue, 15 Dec 2020 at 11:48, Leif Lindholm wrote:
> >
> > First, fix a typo in ID_AA64PFR1 (SBSS -> SSBS).
> >
> > Second, turn clidr in the ARMCPU struct 64-bit, to support all fields
> > defin
On Mon, Dec 14, 2020 at 13:36:51 +, Peter Maydell wrote:
> On Mon, 14 Dec 2020 at 12:36, Leif Lindholm wrote:
> >
> > Signed-off-by: Leif Lindholm
> > ---
> > v1->v2:
> > - Correct CCSIDR_EL1 field sizes.
>
> Hi -- could you resend the whole series
SBSS -> SSBS
Signed-off-by: Leif Lindholm
---
target/arm/cpu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 7e6c881a7e..5e3cf77ec7 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1883,7 +1883,7 @@ FIELD(ID_AA64PFR0,
Add entries present in ARM DDI 0487F.c (August 2020).
Signed-off-by: Leif Lindholm
---
target/arm/cpu.h | 15 +++
1 file changed, 15 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 90ba707b64..efa977eaca 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
The AArch64 view of CLIDR_EL1 extends the ICB field to include also bit
32, as well as adding a Ttype field when FEAT_MTE is implemented.
Extend the clidr field to be able to hold this context.
Signed-off-by: Leif Lindholm
---
target/arm/cpu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion
Add entries present in ARM DDI 0487F.c (August 2020).
Signed-off-by: Leif Lindholm
---
target/arm/cpu.h | 28
1 file changed, 28 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index efa977eaca..fb81eed776 100644
--- a/target/arm/cpu.h
+++ b/target
Rebase to current master.
Leif Lindholm (5):
target/arm: fix typo in cpu.h ID_AA64PFR1 field name
target/arm: make ARMCPU.clidr 64-bit
target/arm: add descriptions of CLIDR_EL1, CCSIDR_EL1, CTR_EL0 to
cpu.h
target/arm: add aarch64 ID register fields to cpu.h
target/arm: add aarc
Signed-off-by: Leif Lindholm
---
target/arm/cpu.h | 24
1 file changed, 24 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index fadd1a47df..90ba707b64 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1736,6 +1736,30 @@ FIELD(V7M_FPCCR, ASPEN, 31
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