I haven't attempted to reproduce the issue recently, I'm afraid. I've
changed jobs twice in the intervening time, so the immediate issue for
me has gone away. If I find an opportunity, I shall try to reproduce
with the most recent versions.
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On Fri, 2 Feb 2007, Justin Fletcher wrote:
On Fri, 2 Feb 2007, Scott Oom wrote:
Hello,
Found a problem when using small pages and getting permission faults.
This patch corrects the decoding of access permissions for small pages
on ARM, was just off by 2 bits.
I may be confused on this, but
On Fri, 2 Feb 2007, Scott Oom wrote:
Hello,
Found a problem when using small pages and getting permission faults.
This patch corrects the decoding of access permissions for small pages
on ARM, was just off by 2 bits.
I may be confused on this, but it still doesn't seem right to me.
You have..
On Thu, 23 Nov 2006, Wolfgang Schildbach wrote:
I very much doubt there is any problem with the CPSR. The ARM emulation
has correctly run hundreds of millions of instructions coming from many
different compilers and hand-written assembly. Can you be more precise in
what the effect is that you se
Hiya,
Tiny fix for the bit manipulation in the PL110 rendering code,
hw/pl110_template.h. There is a sequence of three definitions used in the
graphic routines :
#define FN_2(x, y) FN(x, y) FN(x+1, y)
#define FN_4(x, y) FN_2(x, y) FN_2(x+1, y)
#define FN_8(y) FN_4(0, y) FN_4(4, y)
In the FN_
On Sun, 10 Sep 2006, Paul Brook wrote:
---8<---
if (n != 1)
gen_op_addl_T1_im(-((n - 1) * 4));
}
}
j = 0;
/* Insert something like gen_op_bicl_T1_im(3); here */
for(i=0;i
value is non-zero. Within the OS I'm using, the N flag's value is seldom
intentionally changed, but the Z flag is regularly manipulated.
Justin Fletcher wrote:
Hiya,
I've been using qemu to test an ARM OS with. I hope this is the right
address to contact with patches; I coul
Hiya,
I have found a bug in the implementation of the load/store multiple
instructions in ARM (LDM and STM). These are defined in the ARM ARM to
ignore bits 0 and 1 of the address when the load takes place - that is the
base register for these operations is always treated as a 32bit aligned
v
