Hiya,

Tiny fix for the bit manipulation in the PL110 rendering code, hw/pl110_template.h. There is a sequence of three definitions used in the graphic routines :

#define FN_2(x, y) FN(x, y) FN(x+1, y)
#define FN_4(x, y) FN_2(x, y) FN_2(x+1, y)
#define FN_8(y) FN_4(0, y) FN_4(4, y)

In the FN_4 definition, the second entry should read x+2, rather than x+1. With x+1 we get bits in the wrong order - it's just about usable, but it's not right. This only affects 1bpp and 2bpp modes.

--
Gerph <http://gerph.org/>
... Everybody wants me to sing.


_______________________________________________
Qemu-devel mailing list
Qemu-devel@nongnu.org
http://lists.nongnu.org/mailman/listinfo/qemu-devel

Reply via email to