[PATCH v2 03/12] hw/riscv/virt: Use setprop_sized_cells for memory

Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper and lower 32 bits across cells. Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Signed-off-by: Joel Stanley --- hw/riscv/virt.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/hw

[PATCH v2 12/12] hw/riscv/virt: Use setprop_sized_cells for pcie

Barboza Reviewed-by: Alistair Francis Signed-off-by: Joel Stanley --- hw/riscv/virt.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 67490c5c693a..47e573f85ab1 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -894,8 +894,8

[PATCH v2 10/12] hw/riscv/virt: Use setprop_sized_cells for rtc

Barboza Reviewed-by: Alistair Francis Signed-off-by: Joel Stanley --- hw/riscv/virt.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 7c38a9048044..4fa2bad24804 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -992,8 +992,9

[PATCH v2 07/12] hw/riscv/virt: Use setprop_sized_cells for virtio

Barboza Reviewed-by: Alistair Francis Signed-off-by: Joel Stanley --- hw/riscv/virt.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 67e60eec1f00..851c7cc82ad5 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -856,9 +856,7

[PATCH v2 06/12] hw/riscv/virt: Use setprop_sized_cells for plic

Barboza Reviewed-by: Alistair Francis Signed-off-by: Joel Stanley --- hw/riscv/virt.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 4fd966a34277..67e60eec1f00 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -493,8 +493,8

[PATCH v2 05/12] hw/riscv/virt: Use setprop_sized_cells for aclint

Barboza Reviewed-by: Alistair Francis Signed-off-by: Joel Stanley --- hw/riscv/virt.c | 18 +- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 205fa6e44f29..4fd966a34277 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c

[PATCH v2 02/12] hw/riscv/virt: Use setprop_sized_cells for clint

Barboza Reviewed-by: Alistair Francis Signed-off-by: Joel Stanley --- hw/riscv/virt.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 875eb7155a30..5143a46a 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -346,8 +346,8

[PATCH v2 08/12] hw/riscv/virt: Use setprop_sized_cells for reset

Barboza Reviewed-by: Alistair Francis Signed-off-by: Joel Stanley --- hw/riscv/virt.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 851c7cc82ad5..b59f10dabe19 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -932,8 +932,9

[PATCH v2 04/12] hw/riscv/virt: Use setprop_sized_cells for aplic

Barboza Reviewed-by: Alistair Francis Signed-off-by: Joel Stanley --- hw/riscv/virt.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index e074a296751a..205fa6e44f29 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -655,8 +655,8

[PATCH v2 00/12] hw/riscv/virt: device tree reg cleanups

t,aia=aplic-imsic. Joel Stanley (12): hw/riscv/virt: Fix clint base address type hw/riscv/virt: Use setprop_sized_cells for clint hw/riscv/virt: Use setprop_sized_cells for memory hw/riscv/virt: Use setprop_sized_cells for aplic hw/riscv/virt: Use setprop_sized_cells for aclint hw/riscv

[PATCH v2 09/12] hw/riscv/virt: Use setprop_sized_cells for uart

Barboza Reviewed-by: Alistair Francis Signed-off-by: Joel Stanley --- hw/riscv/virt.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index b59f10dabe19..7c38a9048044 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -966,9 +966,9

[PATCH v2 11/12] hw/riscv/virt: Use setprop_sized_cells for iommu

Barboza Reviewed-by: Alistair Francis Signed-off-by: Joel Stanley --- hw/riscv/virt.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 4fa2bad24804..67490c5c693a 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1088,8 +1088,7

[PATCH v2 01/12] hw/riscv/virt: Fix clint base address type

The address is a hardware address, so use hwaddr for consistency with the rest of the machine. Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Signed-off-by: Joel Stanley --- hw/riscv/virt.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/riscv

Re: [PATCH 01/13] riscv/virt: Fix address type in create_fdt_socket_clint

On Tue, 29 Apr 2025 at 21:56, Daniel Henrique Barboza wrote: > > > > On 4/29/25 3:12 AM, Joel Stanley wrote: > > The address is a hardware address, so use hwaddr for consistency with > > the rest of the machine. > > > > Signed-off-by: Joel Stanley > >

Re: [PATCH 9/9] hw/riscv/virt.c: remove 'long' casts in fmt strings

On Wed, 30 Apr 2025 at 02:41, Daniel Henrique Barboza wrote: > > > > On 4/29/25 9:40 AM, Daniel Henrique Barboza wrote: > > Joel, > > > > I'll make these changes in this patch to be consistent with what we've > > been discussing: > > > >

[PATCH 10/13] hw/riscv/virt: Use setprop_sized_cells for rtc

The current device tree property uses two cells for the address (and for the size), but assumes the they are less than 32 bits by hard coding the high cell to zero. Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper and lower 32 bits across cells. Signed-off-by: Joel Stanley

[PATCH 08/13] hw/riscv/virt: Use setprop_sized_cells for reset

The current device tree property uses two cells for the address (and for the size), but assumes the they are less than 32 bits by hard coding the high cell to zero. Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper and lower 32 bits across cells. Signed-off-by: Joel Stanley

[PATCH 12/13] hw/riscv/virt: Use setprop_sized_cells for pcie

The current device tree property uses two cells for the address (and for the size), but assumes the they are less than 32 bits by hard coding the high cell to zero. Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper and lower 32 bits across cells. Signed-off-by: Joel Stanley

[PATCH 13/13] NOMERGE: virt: Adjust devices so everything is > 4G

Signed-off-by: Joel Stanley --- hw/riscv/virt.c | 42 +- 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index cd19c266e62a..1162b3a4b71a 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -80,27 +80,27

[PATCH 01/13] hw/riscv/virt: Fix clint base address type

The address is a hardware address, so use hwaddr for consistency with the rest of the machine. Signed-off-by: Joel Stanley --- hw/riscv/virt.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 17a790821484..e4c0ac8a2a9a 100644

[PATCH 09/13] hw/riscv/virt: Use setprop_sized_cells for uart

The current device tree property uses two cells for the address (and for the size), but assumes the they are less than 32 bits by hard coding the high cell to zero. Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper and lower 32 bits across cells. Signed-off-by: Joel Stanley

[PATCH 03/13] hw/riscv/virt: Use setprop_sized_cells for memory

Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper and lower 32 bits across cells. Signed-off-by: Joel Stanley --- hw/riscv/virt.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 873d41d10c70..ed28bc06114a 100644

[PATCH 07/13] hw/riscv/virt: Use setprop_sized_cells for virtio

The current device tree property uses two cells for the address (and for the size), but assumes the they are less than 32 bits by hard coding the high cell to zero. Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper and lower 32 bits across cells. Signed-off-by: Joel Stanley

[PATCH 11/13] hw/riscv/virt: Use setprop_sized_cells for iommu

The current device tree property uses two cells for the address (and for the size), but assumes the they are less than 32 bits by hard coding the high cell to zero. Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper and lower 32 bits across cells. Signed-off-by: Joel Stanley

[PATCH 01/13] riscv/virt: Fix address type in create_fdt_socket_clint

The address is a hardware address, so use hwaddr for consistency with the rest of the machine. Signed-off-by: Joel Stanley --- hw/riscv/virt.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 17a790821484..e4c0ac8a2a9a 100644

[PATCH 00/13] hw/riscv/virt: device tree reg cleanups

n the existing code when the reg property describes an address > 4GB. Based-on: 20250423110630.2249904-1-dbarb...@ventanamicro.com Joel Stanley (13): hw/riscv/virt: Fix clint base address type hw/riscv/virt: Use setprop_sized_cells for clint hw/riscv/virt: Use setprop_sized_cells for memory

[PATCH 06/13] hw/riscv/virt: Use setprop_sized_cells for plic

The current device tree property uses two cells for the address (and for the size), but assumes the they are less than 32 bits by hard coding the high cell to zero. Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper and lower 32 bits across cells. Signed-off-by: Joel Stanley

[PATCH 02/13] hw/riscv/virt: Use setprop_sized_cells for clint

The current device tree property uses two cells for the address (and for the size), but assumes the they are less than 32 bits by hard coding the high cell to zero. Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper and lower 32 bits across cells. Signed-off-by: Joel Stanley

[PATCH 04/13] hw/riscv/virt: Use setprop_sized_cells for aplic

The current device tree property uses two cells for the address (and for the size), but assumes the they are less than 32 bits by hard coding the high cell to zero. Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper and lower 32 bits across cells. Signed-off-by: Joel Stanley

[PATCH 05/13] hw/riscv/virt: Use setprop_sized_cells for aclint

The current device tree property uses two cells for the address (and for the size), but assumes the they are less than 32 bits by hard coding the high cell to zero. Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper and lower 32 bits across cells. Signed-off-by: Joel Stanley

Re: [PATCH 9/9] hw/riscv/virt.c: remove 'long' casts in fmt strings

On Fri, 25 Apr 2025 at 22:03, Daniel Henrique Barboza wrote: > > > > On 4/24/25 6:41 AM, Joel Stanley wrote: > > On Wed, 23 Apr 2025 at 20:39, Daniel Henrique Barboza > > wrote: > >> > >> We can avoid the 'long' casts by using PRIx64 and

Re: [PATCH 1/9] hw/riscv/virt.c: enforce s->memmap use in machine_init()

On Fri, 25 Apr 2025 at 21:23, Daniel Henrique Barboza wrote: > > > > On 4/24/25 6:51 AM, Joel Stanley wrote: > > On Wed, 23 Apr 2025 at 20:37, Daniel Henrique Barboza > > wrote: > >> > >> Throughout the code we're accessing the board memmap, most o

Re: [PATCH 9/9] hw/riscv: Add a network device e1000e to the boston-aia

On Fri, 25 Apr 2025 at 23:37, Djordje Todorovic wrote: > > Add a network device e1000e to the boston-aia board model. > There is no pch_gbe emulation, so we add e1000e in slot 0 func 1, > instead. We need to pass func to call pci_parse_devaddr to find > out slot and func. > > Signed-off-by: Chao-y

Re: [PATCH 22/26] target/riscv: convert TT C906 to RISCVCPUDef

On Mon, 28 Apr 2025 at 17:10, Paolo Bonzini wrote: I think a typo has snuck into the subject here. s/TT/Thead/ > > Reviewed-by: Alistair Francis > Signed-off-by: Paolo Bonzini > --- > target/riscv/cpu.c | 61 +- > 1 file changed, 28 insertions(+), 3

Re: [PATCH 1/3] scripts: nixify archive-source.sh

On Thu, Apr 10, 2025 at 02:18:01PM +0200, Paolo Bonzini wrote: > On 4/8/25 22:14, Joel Granados wrote: > > Use "#!/usr/bin/env bash" instead of "#!/bin/bash". This is necessary > > for nix environments as they only provide /usr/bin/env at the standard > &g

Re: [PATCH 1/9] hw/riscv/virt.c: enforce s->memmap use in machine_init()

ning > it to a temp variable 'memmap'. Code is copy/pasted around all the time > and being consistent is important. Reviewed-by: Joel Stanley Cheers, Joel

Re: [PATCH 9/9] hw/riscv/virt.c: remove 'long' casts in fmt strings

"PRIx64, addr); I wondered why this wasn't a HWADDR_PRIx. addr (and NodeInfo::node_mem?) could be a hwaddr? That would make everything more consistent. Cheers, Joel

[PATCH 1/3] scripts: nixify archive-source.sh

Use "#!/usr/bin/env bash" instead of "#!/bin/bash". This is necessary for nix environments as they only provide /usr/bin/env at the standard location. Signed-off-by: Joel Granados --- scripts/archive-source.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --g

[PATCH 0/3] scripts: Add a root dir in archve-source.sh

files are added to the tar.gz root. Comments are greatly appreciated. PS: Had initialy missed adding qemu-devel to CC. Appologies if you received this twice. Signed-off-by: Joel Granados -- --- Joel Granados (3): scripts: nixify archive-source.sh scripts: Add root dir to

[PATCH 3/3] scripts: Clarify doc messages in archive-source.sh

Signed-off-by: Joel Granados --- scripts/archive-source.sh | 12 +--- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/scripts/archive-source.sh b/scripts/archive-source.sh index 7143aaefc1133fe991b329df3c78e6ed7726322f..eb6ee715a8a3a33d8abe333fd896ad1048821b0f 100755

[PATCH 2/3] scripts: Add root dir to arguments

ent is not given. Signed-off-by: Joel Granados --- scripts/archive-source.sh | 78 ++- 1 file changed, 63 insertions(+), 15 deletions(-) diff --git a/scripts/archive-source.sh b/scripts/archive-source.sh index a469a5e2dec4b05e51474f0a1af190

[PATCH-for-10.0] hw/core/machine.c: Fix -machine dumpdtb=file.dtb

on") Signed-off-by: Joel Stanley --- hw/core/machine.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/hw/core/machine.c b/hw/core/machine.c index f52a4f2273b2..63c6ef93d296 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -173

Re: [PATCH] build: Replace meson introspection argument with a builddir

On Thu, Feb 27, 2025 at 10:38:11AM +, Peter Maydell wrote: > On Thu, 27 Feb 2025 at 10:20, Paolo Bonzini wrote: > > > > On 2/27/25 11:07, Joel Granados wrote: > > > Here is the error I see: > > > cmd: > > >meson introspect --buildoptions /home/jo

Re: [PATCH] build: Replace meson introspection argument with a builddir

On Mon, Feb 24, 2025 at 11:57:24AM +0100, Paolo Bonzini wrote: > On 2/4/25 21:10, Joel Granados wrote: > > Replace the meson introspect argument with the build directory instead > > of the meson.build file. The introspect command accepts an optional > > build directory not a

Re: [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two levels of INTC controllers for AST2700 A1

r renames into a different patch. It makes it easier to see what you're adding. Thanks, Joel

[PATCH] build: Replace meson introspection argument with a builddir

Replace the meson introspect argument with the build directory instead of the meson.build file. The introspect command accepts an optional build directory not a file. Signed-off-by: Joel Granados --- For some reason this causes an error when I "remote" compile qemu. In any case, the

Re: [PATCH 2/2] hw/openrisc: Fixed undercounting of TTCR in continuous mode

in this context, this appears to be off-by-one. > > > I think -(ttmr & mask) alone is correct. > > > > Thanks, I did send a mail to Joel asking about this bit. He didn't respond > > for 2 > > weeks to I just sent the patch as is as it appears to work.

Re: [PATCH] hw/aspeed: Correct minimum access size for all models

On Mon, 18 Nov 2024 at 20:40, Peter Maydell wrote: > > On Mon, 18 Nov 2024 at 02:19, Joel Stanley wrote: > > > > Guest code was performing a byte load to the SCU MMIO region, leading to > > the guest code crashing (it should be using proper accessors, but > > tha

[PATCH] hw/aspeed: Correct minimum access size for all models

ccess size of 1. [1] See the 'ARM Address Space Mapping' table in the ASPEED docs. This is section 6.1 in the ast2400 and ast2700, and 7.1 in the ast2500 and ast2600 datasheets. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2636 Signed-off-by: Joel Stanley --- hw/fsi/aspeed

Re: [PATCH v6] hw/misc/aspeed_hace: Fix SG Accumulative hashing

d-master-v2019.04/arch/arm/mach-aspeed/ast2600/spl.c#L46 > I added "printf" in "do_hash_operation" function and ensure this function was > called in HACE model. Thanks for clarifying Jamin. It would be great if these u-boot changes could be submitted to mainline u-boot. Cheers, Joel

Re: [PATCH v6] hw/misc/aspeed_hace: Fix SG Accumulative hashing

On Wed, 23 Oct 2024 at 02:35, Cédric Le Goater wrote: > > On 10/22/24 13:54, Joel Stanley wrote: > > On Wed, 16 Oct 2024 at 01:23, Jamin Lin wrote: > > > >> 3. Test HACE model with u-boot hash command > >> a. load test file to address 8300 via tftp &g

Re: [PATCH v6] hw/misc/aspeed_hace: Fix SG Accumulative hashing

n tests/qtest/aspeed_hace-test.c. The upstream u-boot situation is a mess, and cannot be used to exercise the qemu model at this stage. Cheers, Joel

Missing image on storage.kernelci.org

I was attempting to run some boot tests today and saw this: (11/39) tests/avocado/boot_linux_console.py:BootLinuxConsole.test_arm_bpim2u_gmac: CANCEL: Missing asset http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20221116.0/armel/rootfs.ext2.xz (5.21 s) Cheers, Joel

Re: [PATCH v2] aspeed: Deprecate the tacoma-bmc machine

ine? I know the kernel device tree removed the i2c tpm, but there's no harm in it being present in the qemu machine. The bonnell device tree should boot fine on the rainier machine for your purposes. Cheers, Joel

Re: [PATCH] hw/openrisc: Fixed undercounting of TTCR in continuous mode

arly-complete patch that brings hw/openrisc/cputimer.c into closer alignment with target/mips/sysemu/cp0_timer.c . However, don't we run into problems with undercounting with clock_ns_to_ticks, because if I understand correctly it will round ticks down, not up?, which is the problem I was trying to avoid in the first place. Joel

[PATCH] hw/openrisc: Fixed undercounting of TTCR in continuous mode

accumulating error over time. Signed-off-by: Joel Holdsworth --- hw/openrisc/cputimer.c | 22 +- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/hw/openrisc/cputimer.c b/hw/openrisc/cputimer.c index 835986c4db..ddc129aa48 100644 --- a/hw/openrisc/cputimer.c +++ b/hw

Re: Deprecation/removal of nios2 target support

g the obsolescence in the Linux kernel. > Just an FYI that the RTEMS Project plans to drop NIOS II support based on what happens with the tooling. --joel > > -- > Joseph S. Myers > josmy...@redhat.com > >

Re: [PATCH rfcv1 23/23] intel_iommu: modify x-scalable-mode to be string option

On Wed, Jan 31, 2024 at 11:24:18PM +0800, Yi Liu wrote: > On 2024/1/31 22:40, Joel Granados wrote: > > On Mon, Jan 15, 2024 at 06:37:35PM +0800, Zhenzhong Duan wrote: > >> From: Yi Liu > >> > >> Intel VT-d 3.0 introduces scalable mode, and it has a bunch of c

Re: [PATCH rfcv1 23/23] intel_iommu: modify x-scalable-mode to be string option

>scalable_mode = false; > +s->scalable_modern = false; > +} > + > if ((s->aw_bits != VTD_HOST_AW_39BIT) && > (s->aw_bits != VTD_HOST_AW_48BIT) && > !s->scalable_modern) { > -- > 2.34.1 > > I noticed that this patch changes quite a bit from the previous version that you had. I Specifically noticed that you dropped VTD_ECAP_PRS from intel_iommu_internal.h. I was under the impression that this set the Page Request Servicves capability in the IOMMU effectively enabling PRI in the iommu. Why did you remove it from your original patch? Thx in advance Best -- Joel Granados signature.asc Description: PGP signature

Re: Questions regarding the still unpublished qemu series https://github.com/yiliu1765/qemu/tree/zhenzhong/wip/iommufd_nesting_rfcv1

On Thu, Dec 21, 2023 at 03:33:47AM +, Duan, Zhenzhong wrote: > Hi Joel, > > >-Original Message----- > >From: Joel Granados > >Subject: Questions regarding the still unpublished qemu series > >https://github.com/yiliu1765/qemu/tree/zhenzhong/wip/iommufd_

Questions regarding the still unpublished qemu series https://github.com/yiliu1765/qemu/tree/zhenzhong/wip/iommufd_nesting_rfcv1

: Why assert on the permissions being NONE if they might be read|write? Hope this makes sense. Don't hesitate to get back to me if you see that there is something missing in my explanation. Best -- Joel Granados signature.asc Description: PGP signature

Re: [RFC PATCH 11/11] ppc/pnv: Change powernv default to powernv10

On Wed, 11 Oct 2023 at 07:28, Nicholas Piggin wrote: > > On Tue Oct 10, 2023 at 10:05 PM AEST, Joel Stanley wrote: > > On Tue, 10 Oct 2023 at 18:24, Nicholas Piggin wrote: > > > > > > POWER10 is the latest IBM Power machine. Although it is not offered in &g

Re: [PATCH v2] misc/pca9552: Let external devices set pca9552 inputs

On Fri, 6 Oct 2023 at 07:23, Glenn Miles wrote: > > Allow external devices to drive pca9552 input pins by adding > input GPIO's to the model. This allows a device to connect > its output GPIO's to the pca9552 input GPIO's. > > In order for an external device to set the state of a pca9552 > pin, t

Re: [RFC PATCH 10/11] ppc/spapr: change pseries machine default to POWER10 CPU

On Tue, 10 Oct 2023 at 18:25, Nicholas Piggin wrote: > > POWER10 is the latest pseries CPU. > > Signed-off-by: Nicholas Piggin Reviewed-by: Joel Stanley > --- > hw/ppc/spapr.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/hw/ppc/spapr

Re: [RFC PATCH 11/11] ppc/pnv: Change powernv default to powernv10

; powernv10 at the moment. > > Signed-off-by: Nicholas Piggin Reviewed-by: Joel Stanley Do we need to update the docs? We should consider updating the skiboot to the latest release too. > --- > hw/ppc/pnv.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) >

Re: [RFC PATCH 05/11] testing/avocado: ppc add new BookE boot_linux_console.py tests

modern BookE images now. > > Signed-off-by: Nicholas Piggin Reviewed-by: Joel Stanley Should we get mpe to add a https://github.com/linuxppc/qemu-ci-images for you to keep those kernel images? But perhaps you'd prefer to keep them on gitlab. Just a suggestion. > --- > tes

Re: [PATCH 1/4] aspeed/i2c: Clean up local variable shadowing

; > Signed-off-by: Cédric Le Goater Reviewed-by: Joel Stanley messy. > --- > hw/i2c/aspeed_i2c.c | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c > index 7275d40749a9..1037c22b2f79 100644 > --- a/hw/i2c/a

Re: [Qemu-devel] [PATCH 08/19] aspeed/timer: Fix behaviour running Linux

l variable name, as well as handling the const and non-const variants with the one macro. https://elixir.bootlin.com/linux/v6.5/source/include/linux/minmax.h Cheers, Joel

Re: [PATCH v3.2 5/7] aspeed: Create flash devices only when defaults are enabled

noted that in this case, the ROM will not be installed and the > initial boot sequence (U-Boot loading) will fetch instructions using > SPI transactions which is significantly slower. That's exactly how HW > operates though. > > Signed-off-by: Cédric Le Goater Reviewe

Re: [PATCH v3 5/7] aspeed: Create flash devices only when defaults are enabled

On Thu, 31 Aug 2023 at 13:22, Cédric Le Goater wrote: > > On 8/31/23 15:00, Joel Stanley wrote: > > On Thu, 31 Aug 2023 at 12:39, Cédric Le Goater wrote: > >> > >> When the -nodefaults option is set, flash devices should be created > >> with : > >>

Re: [PATCH v3 5/7] aspeed: Create flash devices only when defaults are enabled

the first foray for the aspeed machines into nodefaults removing things that previously would have just worked. I know we haven't had it in our recommended command lines for a long time, so that's fine. Reviewed-by: Joel Stanley Should the content of your commit message go in the docs? &g

Re: [PATCH for-8.2 2/3] pnv/lpc: Hook up xscom region for P9/P10

On Tue, 29 Aug 2023 at 14:45, Cédric Le Goater wrote: > > On 8/9/23 16:56, Frederic Barrat wrote: > > Hello Joel, > > > > So we're re-using the same xscom ops as on P8. A quick look at the > > definition of those 4 registers on P8 (0xb0020) and on P9/P10 (0x0

Re: [PATCH] tests/avocado/machine_aspeed.py: Update SDK images

re any value in testing both the old and the new images? Reviewed-by: Joel Stanley > > Signed-off-by: Cédric Le Goater > --- > > Requires patches from Hang Yu [1] > > [1] > https://lore.kernel.org/qemu-devel/20230812065230.8839-1-francis_...@stu.pku.edu.cn/ >

Re: [PATCH v1 5/7] hw/fsi: IBM's On-chip Peripheral Bus

PEED SoC due > to tight integration of the FSI master IP with the OPB, mainly the > existence of an MMIO-mapping of the CFAM address straight onto a > sub-region of the OPB address space. > > Signed-off-by: Andrew Jeffery > Signed-off-by: Cédric Le Goater > Signed-off-b

Re: [PATCH v1 4/7] hw/fsi: Introduce IBM's FSI

a CFAM. > > Signed-off-by: Andrew Jeffery > Signed-off-by: Cédric Le Goater > Signed-off-by: Ninad Palsule Reviewed-by: Joel Stanley > --- > hw/fsi/cfam.c | 1 + > hw/fsi/fsi-master.c | 203 > hw/fsi/fsi.c

Re: [PATCH v1 6/7] hw/fsi: Aspeed APB2OPB interface

On Fri, 25 Aug 2023 at 20:31, Ninad Palsule wrote: > > This is a part of patchset where IBM's Flexible Service Interface is > introduced. > > An APB-to-OPB bridge enabling access to the OPB from the ARM core in > the AST2600. Hardware limitations prevent the OPB from being directly > mapped into A

Re: [PATCH v1 7/7] hw/arm: Hook up FSI module in AST2600

On Fri, 25 Aug 2023 at 20:35, Ninad Palsule wrote: > > This patchset introduces IBM's Flexible Service Interface(FSI). > > Time for some fun with inter-processor buses. FSI allows a service > processor access to the internal buses of a host POWER processor to > perform configuration or debugging.

Re: [PATCH v1 1/7] hw/fsi: Introduce IBM's Local bus

On Fri, 25 Aug 2023 at 20:31, Ninad Palsule wrote: > > This is a part of patchset where IBM's Flexible Service Interface is > introduced. > > The LBUS is modelled to maintain the qdev bus hierarchy and to take > advantage of the object model to automatically generate the CFAM > configuration block

Re: [PATCH v1 0/7] Introduce model for IBM's FSP

Hi Ninad, On Fri, 25 Aug 2023 at 20:51, Ninad Palsule wrote: > > Hello, > > Please review the patch-set. > > This is a first step towards introducing model for IBM's Flexible > Service Interface. The full functionality will be implemented over the > time. You have a typo in the subject, I think

Re: [PATCH v1 00/23] Q35 support for Xen

with them, so I am hoping progress is moving forward on the Xen side. I wish I could work on this full time to get everything as it needs to be soon. -Joel On Tue, Aug 22, 2023 at 10:18 AM Anthony PERARD wrote: > Hi Joel, > > We had a design session about Q35 support during Xen Summit, an

[PATCH for-8.2 3/3] HACK: pnv/lpc: Set up XSCOM dt for P9

t(lpc); lpc->chip_id = gcid; - lpc->mbase = (void *)addr; + lpc->xbase = dt_get_address(lpc_node, 0, NULL); lpc->fw_idsel = 0xff; lpc->fw_rdsz = 0xff; lpc->node = lpc_node; Signed-off-by: Joel Stanley --- hw/ppc/pnv_lpc.c | 5 +

[PATCH for-8.2 1/3] pnv/lpc: Place mmio regs in their own memory region

The P9 and P10 models re-used the xscom_regs memory region for the mmio access, which is confusing. Add a separate memory region in preparation for enabling both xscom and mmio access. Signed-off-by: Joel Stanley --- include/hw/ppc/pnv_lpc.h | 3 ++- hw/ppc/pnv.c | 4 ++-- hw/ppc

[PATCH for-8.2 2/3] pnv/lpc: Hook up xscom region for P9/P10

>From P9 on the LPC bus is memory mapped. However the xscom access still is possible, so add it too. Signed-off-by: Joel Stanley --- include/hw/ppc/pnv_xscom.h | 6 ++ hw/ppc/pnv.c | 4 hw/ppc/pnv_lpc.c | 6 ++ 3 files changed, 16 insertions(+) diff --gi

[PATCH for-8.2 0/3] pnv/lpc: Hook up xscoms for LPC

not be applied. Joel Stanley (3): pnv/lpc: Place mmio regs in their own memory region pnv/lpc: Hook up xscom region for P9/P10 HACK: pnv/lpc: Set up XSCOM dt for P9 include/hw/ppc/pnv_lpc.h | 3 ++- include/hw/ppc/pnv_xscom.h | 6 ++ hw/ppc/pnv.c | 8 ++-- hw/ppc

[PATCH] configure: Fix linux-user host detection for ppc64le

Revert the changes in the recent "Fix linux-user host detection for riscv64" patch as it broke ppc64le. Instead add riscv to the switch statement that performs normalisation of the host cpu name. Fixes: 89e5b7935e92 ("configure: Fix linux-user host detection for riscv64")

Re: [PATCH] configure: Fix linux-user host detection for riscv64

tement instead of adding the host_arch variable? @@ -508,6 +501,9 @@ case "$cpu" in cpu="ppc64" CPU_CFLAGS="-m64 -mlittle-endian" ;; + riscv*) +cpu="riscv" ;; + s390) CPU_CFLAGS="-m31" ;; s390x) Cheers, Joel > > Fi

Re: [PATCH v7 00/14] linux-user: brk fixes

. > change that to become: > info->brk = HOST_PAGE_ALIGN(hiaddr); That stopped the crashing, and the binaries seem to run fine. I tested on two hosts: ppc64le (64K) and arm64 (16K). Cheers, Joel

Re: [PATCH v7 00/14] linux-user: brk fixes

c64le host now segfaults: $ gdb -q -ex r --args ./build/qemu-arm -d guest_errors,page,strace ~/hello Reading symbols from ./build/qemu-arm... Starting program: /scratch/joel/qemu/build/qemu-arm -d guest_errors,page,strace /home/joel/hello [Thread debugging using libthread_db enabled] Using hos

Re: [PATCH v6 0/8] linux-user: brk fixes

On Tue, 1 Aug 2023 at 23:28, Helge Deller wrote: > > This patch series is a fix-up for some current problems > regarding heap memory / brk handling in qemu which happens > on some 32-bit platforms, e.g. problems loading static > binaries. > > This series includes the 5 patches from Akihiko Odaki >

Re: [PATCH 0/5] linux-user: brk/mmap fixes

On Mon, 31 Jul 2023 at 18:24, Helge Deller wrote: > > I re-read the thread again. As it seems Joel already tried the latest > > version from me? Sadly I can't test myself on ppc64le (static binary > > needs klibc-PupSAGgtpafMlSLXOLgje1kXFo8.so in /usr/lib which I can&#x

Re: [PATCH 0/5] linux-user: brk/mmap fixes

y Helge Deller, have you seen it? > ("linux-user: Fix and optimize target memory layout", a v5 already). Applying this series fixes the qemu-arm running the static armhf binary on my ppc64le host that I reported here[1]. Tested-by: Joel Stanley The changes conflict with Helge's

Re: [PATCH v5 0/3] linux-user: Fix and optimize target memory layout

o, World!\n");} Built like this: arm-linux-gnueabihf-gcc -o hello-armhf hello.c -static arm-linux-gnueabi-gcc -o hello hello.c -static on an Ubuntu 23.04 host. Cheers, Joel

Re: [PATCH] gdbstub: Fix client Ctrl-C handling

On Sun, 30 Jul 2023 at 09:43, Nicholas Piggin wrote: > > On Wed Jul 26, 2023 at 4:35 PM AEST, Joel Stanley wrote: > > On Wed, 12 Jul 2023 at 02:12, Nicholas Piggin wrote: > > > > > > On Tue Jul 11, 2023 at 9:03 PM AEST, Matheus Tavares Bernardino wrote: &g

Re: [PATCH] gdbstub: Fix client Ctrl-C handling

r before the stop filtering patch. > > Could go further and only stop the machine if it was a 3, or send a > stop packet even if we were stopped, etc. but all that get further from > a minimal fix. I was taking a look at -rc1 and it looks like this hasn't made it in. Is it something we want to propose including? As a user of qemu I'd vote for it to go in. Cheers, Joel

[PATCH] ppc: Add stub implementation of TRIG SPRs

Linux sets these to control cache flush behaviour on Power9. Supervisor and hypervisor are allowed to write, and reads are noops. Add implementations to avoid noisy messages when booting Linux under the pseries machine with guest_errors enabled. Reviewed-by: Nicholas Piggin Signed-off-by: Joel

Re: [RFC PATCH v4 20/24] vfio/iommufd: Implement the iommufd backend

(const char *dev, int devfd) " %s (fd=%d)" > +vfio_iommufd_bind_device(int iommufd, const char *name, int devfd, int > devid) " [iommufd=%d] Succesfully bound device %s (fd=%d): output devid=%d" > +vfio_iommufd_attach_device(int iommufd, const char *name, int devfd, int > ioasid, int hwptid) " [iommufd=%d] Succesfully attached device %s (%d) to > ioasid=%d: output hwptd=%d" > +vfio_iommufd_detach_device(int iommufd, const char *name, int ioasid) " > [iommufd=%d] Detached %s from ioasid=%d" > +vfio_iommufd_alloc_ioas(int iommufd, int ioas_id) " [iommufd=%d] new IOMMUFD > container with ioasid=%d" > +vfio_iommufd_device_info(char *name, int devfd, int num_irqs, int > num_regions, int flags) " %s (%d) num_irqs=%d num_regions=%d flags=%d" > +vfio_iommufd_fail_attach_existing_container(const char *msg) " %s" > +vfio_iommufd_container_reset(char *name) " Successfully reset %s" > diff --git a/include/hw/vfio/vfio-common.h b/include/hw/vfio/vfio-common.h > index 81a87d88b6..6434a442fd 100644 > --- a/include/hw/vfio/vfio-common.h > +++ b/include/hw/vfio/vfio-common.h > @@ -85,6 +85,26 @@ typedef struct VFIOLegacyContainer { > QLIST_HEAD(, VFIOGroup) group_list; > } VFIOLegacyContainer; > > +#ifdef CONFIG_IOMMUFD > +typedef struct VFIOIOASHwpt { > +uint32_t hwpt_id; > +QLIST_HEAD(, VFIODevice) device_list; > +QLIST_ENTRY(VFIOIOASHwpt) next; > +} VFIOIOASHwpt; > + > +typedef struct IOMMUFDBackend IOMMUFDBackend; > + > +typedef struct VFIOIOMMUFDContainer { > +VFIOContainer bcontainer; > +IOMMUFDBackend *be; > +uint32_t ioas_id; > +QLIST_HEAD(, VFIOIOASHwpt) hwpt_list; > +} VFIOIOMMUFDContainer; > +#endif > + > +typedef QLIST_HEAD(VFIOAddressSpaceList, VFIOAddressSpace) > VFIOAddressSpaceList; > +extern VFIOAddressSpaceList vfio_address_spaces; > + > typedef struct VFIODeviceOps VFIODeviceOps; > > typedef struct VFIODevice { > @@ -110,6 +130,10 @@ typedef struct VFIODevice { > OnOffAuto pre_copy_dirty_page_tracking; > bool dirty_pages_supported; > bool dirty_tracking; > +#ifdef CONFIG_IOMMUFD > +int devid; > +IOMMUFDBackend *iommufd; > +#endif > } VFIODevice; > > struct VFIODeviceOps { > diff --git a/include/hw/vfio/vfio-container-base.h > b/include/hw/vfio/vfio-container-base.h > index b18fa92146..51aff4af05 100644 > --- a/include/hw/vfio/vfio-container-base.h > +++ b/include/hw/vfio/vfio-container-base.h > @@ -117,6 +117,9 @@ void vfio_container_init(VFIOContainer *container, > void vfio_container_destroy(VFIOContainer *container); > > #define TYPE_VFIO_IOMMU_BACKEND_LEGACY_OPS "vfio-iommu-backend-legacy-ops" > +#ifdef CONFIG_IOMMUFD > +#define TYPE_VFIO_IOMMU_BACKEND_IOMMUFD_OPS "vfio-iommu-backend-iommufd-ops" > +#endif > #define TYPE_VFIO_IOMMU_BACKEND_OPS "vfio-iommu-backend-ops" > > DECLARE_CLASS_CHECKERS(VFIOIOMMUBackendOpsClass, > -- > 2.34.1 > > -- Joel Granados signature.asc Description: PGP signature

Re: [PATCH v2] ppc/pnv: Add QME region for P10

trying to describe why we have the + 0x1000. Each core sets a bit in the xscom address space, with the first core setting bit 12, second bit 13, etc. So there's actually no registers at PNV10_XSCOM_QME_BASE, but so the addressing is easier to follow, I chose to start the base where we do, and make the region 0x1000 bigger. That was my understanding at least. Cheers, Joel > > Thanks, > Nick

Re: [PATCH v2] ppc/pnv: Add QME region for P10

On Fri, 7 Jul 2023 at 07:30, Cédric Le Goater wrote: > > On 7/7/23 09:12, Joel Stanley wrote: > > The Quad Management Engine (QME) manages power related settings for its > > quad. The xscom region is separate from the quad xscoms, therefore a new > > region is added. The

[PATCH v2] ppc/pnv: Add QME region for P10

special wakeup (SPWU) registers. This quietens some sxcom errors when skiboot boots on p10. Power9 does not have a QME. Signed-off-by: Joel Stanley --- v2: Clean up extra whitespace Make realize quad specific so power9 doesn't end up with the qme region --- include/hw/ppc/pnv_core.h

Re: [PATCH] ppc/pnv: Add QME region for P10

E_SIZE; > > xscom_qme_size is only defined on power10 and it is 0 on power9. The region > is nevertheless initialized on power9 and never mapped. > > I think we should introduce a specific realize routine for each proc now. I overlooked the P9 behaviour, thanks for pointing that out. I'll make the realise proc specific. Cheers, Joel

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