Kernel provides the guidance of dynamic MSI-X allocation support of
passthrough device, by clearing the VFIO_IRQ_INFO_NORESIZE flag to
guide user space.
Fetch the flags from host to determine if dynamic MSI-X allocation is
supported.
Originally-by: Reinette Chatre
Signed-off-by: Jing Liu
_nr is not
efficient and unnecessary.
Signed-off-by: Jing Liu
Tested-by: Reinette Chatre
Reviewed-by: Alex Williamson
---
Changes since v2:
- Use a bool type to test (vdev->nr_vectors < nr + 1). (Alex)
- Revise the comments. (Alex)
- Apply Alex's Reviewed-by.
Changes since v1:
, create a function
for that.
Suggested-by: Alex Williamson
Signed-off-by: Jing Liu
Reviewed-by: Cédric Le Goater
Reviewed-by: Alex Williamson
---
Changes since v2:
- Apply Cédric's Reviewed-by.
- Apply Alex's Reviewed-by.
Changes since v1:
- Revise Qemu to QEMU. (Cédric)
- Use g_a
rs being allocated on host. To
consolidate them, we use vector 0 with an invalid fd to get MSI-X
enabled and create a common function for this. This is cleaner than
setting userspace triggering and immediately release.
Any feedback is appreciated.
Jing
[1] https://lwn.net/Articles/931679/
Jin
according to the VFIO_DEVICE_SET_IRQS ioctl.
When dynamic MSI-X allocation is supported, we only want the guest
unmasked vectors being allocated and enabled. Use vector 0 with an
invalid fd to get MSI-X enabled, after that, all the vectors can be
allocated in need.
Signed-off-by: Jing Liu
Reviewed-by
ck is appreciated.
Jing
[1] https://lwn.net/Articles/931679/
Jing Liu (4):
vfio/pci: detect the support of dynamic MSI-X allocation
vfio/pci: enable vector on dynamic MSI-X allocation
vfio/pci: use an invalid fd to enable MSI-X
vfio/pci: enable MSI-X in interrupt restoring on dynamic allocation
Kernel provides the guidance of dynamic MSI-X allocation support of
passthrough device, by clearing the VFIO_IRQ_INFO_NORESIZE flag to
guide user space.
Fetch the flags from host to determine if dynamic MSI-X allocation is
supported.
Originally-by: Reinette Chatre
Signed-off-by: Jing Liu
ries_nr is not
efficient and unnecessary.
Signed-off-by: Jing Liu
Tested-by: Reinette Chatre
---
Changes since v1:
- Revise Qemu to QEMU.
Changes since RFC v1:
- Test vdev->msix->noresize to identify the allocation mode. (Alex)
- Move defer_kvm_irq_routing test out and update nr_vectors in
, create a function
for that.
Suggested-by: Alex Williamson
Signed-off-by: Jing Liu
---
Changes since v1:
- Revise Qemu to QEMU. (Cédric)
- Use g_autofree to automatically release. (Cédric)
- Just return 'ret' and let the caller of vfio_enable_msix_no_vec()
report the error. (Cédric)
Cha
according to the VFIO_DEVICE_SET_IRQS ioctl.
When dynamic MSI-X allocation is supported, we only want the guest
unmasked vectors being allocated and enabled. Use vector 0 with an
invalid fd to get MSI-X enabled, after that, all the vectors can be
allocated in need.
Signed-off-by: Jing Liu
---
Changes
, create a function
for that.
Suggested-by: Alex Williamson
Signed-off-by: Jing Liu
---
Changes since RFC v1:
- A new patch. Use an invalid fd to get MSI-X enabled instead of using
userspace triggering. (Alex)
---
hw/vfio/pci.c | 50 ++
1 file changed
/931679/
Jing Liu (4):
vfio/pci: detect the support of dynamic MSI-X allocation
vfio/pci: enable vector on dynamic MSI-X allocation
vfio/pci: use an invalid fd to enable MSI-X
vfio/pci: enable MSI-X in interrupt restoring on dynamic allocation
hw/vfio/pci.c| 126
ries_nr is not
efficient and unnecessary.
Signed-off-by: Jing Liu
Tested-by: Reinette Chatre
---
Changes since RFC v1:
- Test vdev->msix->noresize to identify the allocation mode. (Alex)
- Move defer_kvm_irq_routing test out and update nr_vectors in a
common place before vfio_enable_
according to the VFIO_DEVICE_SET_IRQS ioctl.
When dynamic MSI-X allocation is supported, we only want the guest
unmasked vectors being allocated and enabled. Use vector 0 with an
invalid fd to get MSI-X enabled, after that, all the vectors can be
allocated in need.
Signed-off-by: Jing Liu
---
Changes
Kernel provides the guidance of dynamic MSI-X allocation support of
passthrough device, by clearing the VFIO_IRQ_INFO_NORESIZE flag to
guide user space.
Fetch the flags from host to determine if dynamic MSI-X allocation is
supported.
Originally-by: Reinette Chatre
Signed-off-by: Jing Liu
Chatre
Signed-off-by: Jing Liu
---
hw/vfio/pci.c| 12
hw/vfio/pci.h| 1 +
hw/vfio/trace-events | 2 ++
3 files changed, 15 insertions(+)
diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c
index a205c6b1130f..0c4ac0873d40 100644
--- a/hw/vfio/pci.c
+++ b/hw/vfio/pci.c
@@ -1572,6
according to the ioctl().
When dynamic MSI-X allocation is supported, we only want the guest
unmasked vectors being allocated and enabled. Therefore, Qemu can first
set vector 0 to enable MSI-X and after that, all the vectors can be
allocated in need.
Signed-off-by: Jing Liu
---
hw/vfio/pci.c | 32
ries_nr is not
efficient and unnecessary.
Signed-off-by: Jing Liu
Tested-by: Reinette Chatre
---
hw/vfio/pci.c | 40 +++-
1 file changed, 27 insertions(+), 13 deletions(-)
diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c
index 0c4ac0873d40..8c485636445c 100644
---
enabling, the API can decide which
should be allocated via the event fd value. In this way, the interrupts
allocation on target would be the same as migration source.
Jing Liu (2):
vfio/pci: enable vector on dynamic MSI-X allocation
vfio/pci: dynamic MSI-X allocation in interrupt restoring
: Chao Peng
Signed-off-by: Chao Peng
Co-developed-by: Liu Jiang
Signed-off-by: Liu Jiang
Co-developed-by: Zha Bin
Signed-off-by: Zha Bin
Signed-off-by: Jing Liu
---
content.tex | 171 ++--
msi-state.c | 4 ++
2 files changed, 159
: Zha Bin
Signed-off-by: Jing Liu
---
content.tex | 48 +++-
msi-state.c | 3 ++-
2 files changed, 49 insertions(+), 2 deletions(-)
diff --git a/content.tex b/content.tex
index dcf6c71..2fd1686 100644
--- a/content.tex
+++ b/content.tex
@@ -1770,7 +1770,8
Signed-off-by: Liu Jiang
Co-developed-by: Zha Bin
Signed-off-by: Zha Bin
Signed-off-by: Jing Liu
---
content.tex | 53 -
1 file changed, 40 insertions(+), 13 deletions(-)
diff --git a/content.tex b/content.tex
index 826bc7d..5881253 100644
Signed-off-by: Zha Bin
Signed-off-by: Jing Liu
---
content.tex | 7 +++
1 file changed, 7 insertions(+)
diff --git a/content.tex b/content.tex
index 5881253..ff151ba 100644
--- a/content.tex
+++ b/content.tex
@@ -5840,6 +5840,9 @@ \chapter{Reserved Feature Bits}\label{sec:Reserved
Feature
;v2:
* Change version update to feature bit
* Add mask/unmask support
* Add two MSI sharing/non-sharing modes
* Change MSI registers layout and bits
Jing Liu (5):
virtio-mmio: Add feature bit for MMIO notification
virtio-mmio: Enhance queue notification support
virtio-mmio: Add feature bit for M
Co-developed-by: Zha Bin
Signed-off-by: Zha Bin
Signed-off-by: Jing Liu
---
content.tex | 9 +
1 file changed, 9 insertions(+)
diff --git a/content.tex b/content.tex
index d68cfaf..826bc7d 100644
--- a/content.tex
+++ b/content.tex
@@ -5810,6 +5810,9 @@ \chapter{Reserved Feature Bits
On 8/30/2019 10:27 PM, Sergio Lopez wrote:
Jing Liu writes:
Hi Sergio,
On 8/29/2019 11:46 PM, Sergio Lopez wrote:
Jing Liu writes:
Hi Sergio,
The idea is interesting and I tried to launch a guest by your
guide but seems failed to me. I tried both legacy and normal modes,
but the
Hi Sergio,
On 8/29/2019 11:46 PM, Sergio Lopez wrote:
Jing Liu writes:
Hi Sergio,
The idea is interesting and I tried to launch a guest by your
guide but seems failed to me. I tried both legacy and normal modes,
but the vncviewer connected and told me that:
The vm has no graphic display
Hi Sergio,
The idea is interesting and I tried to launch a guest by your
guide but seems failed to me. I tried both legacy and normal modes,
but the vncviewer connected and told me that:
The vm has no graphic display device.
All the screen in vnc is just black.
kernel config:
CONFIG_KVM_MMIO=y
C
Ping~ :)
Thanks,
Jing
On 7/25/2019 2:14 PM, Jing Liu wrote:
Intel CooperLake cpu adds AVX512_BF16 instruction, defining as
CPUID.(EAX=7,ECX=1):EAX[bit 05].
The patch adds a property for setting the subleaf of CPUID leaf 7 in
case that people would like to specify it.
The release spec link as
Hi,
Looking forward to your comments. :)
Thanks!
Jing
On 7/25/2019 2:14 PM, Jing Liu wrote:
Intel CooperLake cpu adds AVX512_BF16 instruction, defining as
CPUID.(EAX=7,ECX=1):EAX[bit 05].
The patch adds a property for setting the subleaf of CPUID leaf 7 in
case that people would like to
/c5/15/\
architecture-instruction-set-extensions-programming-reference.pdf
Signed-off-by: Jing Liu
---
target/i386/cpu.c | 39 ++-
target/i386/cpu.h | 7 +++
target/i386/kvm.c | 3 ++-
3 files changed, 47 insertions(+), 2 deletions(-)
diff --git a/target
On 7/22/2019 7:50 PM, Paolo Bonzini wrote:
On 22/07/19 04:59, Jing Liu wrote:
On 7/19/2019 4:10 PM, Paolo Bonzini wrote:
On 19/07/19 09:20, Jing Liu wrote:
Then CPUID[7,0].EAX is set automatically to 0 or 1 depending on whether
BF16 is enabled or not.
Could I ask why don't we dir
On 7/19/2019 4:10 PM, Paolo Bonzini wrote:
On 19/07/19 09:20, Jing Liu wrote:
Then CPUID[7,0].EAX is set automatically to 0 or 1 depending on whether
BF16 is enabled or not.
Could I ask why don't we directly check BF16 enabling when
cpu_x86_cpuid(env, 7, 0, ...) during kvm_arch_init
On 7/18/2019 4:15 PM, Paolo Bonzini wrote:
On 18/07/19 06:55, Jing Liu wrote:
+ *eax = kvm_arch_get_supported_cpuid(cs->kvm_state, 0x7,
+ count, R_EAX);
This needs to be firstly checked as follows, otherwise some
architectures wo
On 7/11/2019 1:38 PM, Jing Liu wrote:
Intel CooperLake cpu adds AVX512_BF16 instruction, defining as
CPUID.(EAX=7,ECX=1):EAX[bit 05].
The release spec link as follows,
https://software.intel.com/sites/default/files/managed/c5/15/\
architecture-instruction-set-extensions-programming
Intel CooperLake cpu adds AVX512_BF16 instruction, defining as
CPUID.(EAX=7,ECX=1):EAX[bit 05].
The release spec link as follows,
https://software.intel.com/sites/default/files/managed/c5/15/\
architecture-instruction-set-extensions-programming-reference.pdf
Signed-off-by: Jing Liu
---
target
Intel CooperLake cpu adds AVX512_BF16 instruction, defining as
CPUID.(EAX=7,EXC=1):EAX[bit 05].
The release spec link as follows,
https://software.intel.com/sites/default/files/managed/c5/15/\
architecture-instruction-set-extensions-programming-reference.pdf
Signed-off-by: Jing Liu
---
target
Add hint to firmware (e.g. SeaBIOS) to reserve addtional
BUS/IO/MEM/PREF resource for legacy pci-pci bridge. Add the
resource reserve capability deleting in pci_bridge_dev_exitfn.
Signed-off-by: Jing Liu
---
hw/pci-bridge/pci_bridge_dev.c | 24
1 file changed, 24
add refactoring patch
* add teardown function
* some other fixes
Jing Liu (2):
hw/pci: factor PCI reserve resources to a separate structure
hw/pci: add PCI resource reserve capability to legacy PCI bridge
hw/pci-bridge/gen_pcie_root_port.c | 33 +
hw/pci-bridge/
Factor "bus_reserve", "io_reserve", "mem_reserve", "pref32_reserve"
and "pref64_reserve" fields of the "GenPCIERootPort" structure out
to "PCIResReserve" structure, so that other PCI bridges can
reuse it to add res
Add hint to firmware (e.g. SeaBIOS) to reserve addtional
BUS/IO/MEM/PREF resource for legacy pci-pci bridge.
Signed-off-by: Jing Liu
---
hw/pci-bridge/pci_bridge_dev.c | 25 +
1 file changed, 25 insertions(+)
diff --git a/hw/pci-bridge/pci_bridge_dev.c b/hw/pci-bridge
Factor "bus_reserve", "io_reserve", "mem_reserve", "pref32_reserve"
and "pref64_reserve" fields of the "GenPCIERootPort" structure out
to "PCIResReserve" structure, so that other PCI bridges can
reuse it to add res
n function called pci_bridge_qemu_reserve_cap_uninit().
Last we enable the resource reserve capability for legacy PCI bridge
so that firmware can reserve additional resources for the bridge.
Change Log:
v2 -> v1
* add refactoring patch
* add teardown function
* some other fixes
Jing Liu (3):
h
Clean up the PCI config space of resource reserve capability.
Signed-off-by: Jing Liu
---
hw/pci/pci_bridge.c | 9 +
include/hw/pci/pci_bridge.h | 1 +
2 files changed, 10 insertions(+)
diff --git a/hw/pci/pci_bridge.c b/hw/pci/pci_bridge.c
index 15b055e..dbcee90 100644
--- a
Add hint to firmware (e.g. SeaBIOS) to reserve addtional
IO/MEM/PREF spaces for legacy pci-pci bridge, to enable
some pci devices hotplugging whose IO/MEM/PREF spaces
requests are larger than the ones in pci-pci bridge set
by firmware.
Signed-off-by: Jing Liu
---
hw/pci-bridge/pci_bridge_dev.c
On 2017/7/25 下午11:48, Daniel P. Berrange wrote:
On Tue, Jul 25, 2017 at 04:45:46PM +0100, Stefan Hajnoczi wrote:
On Mon, Jul 24, 2017 at 02:44:13PM +0800, Jing Liu wrote:
On 2017/7/21 上午11:47, Cleber Rosa wrote:
One of the "sub-"tests of test 087 requires CONFIG_LINUX_AIO.
As
Hi Cleber,
On 2017/7/21 上午11:47, Cleber Rosa wrote:
One of the "sub-"tests of test 087 requires CONFIG_LINUX_AIO.
As a PoC/RFC, this goes the easy route and skips the test as a whole
when that feature is missing. Other approaches include splitting
the test and adding extra filtering.
Signed-
Hi Cleber Rosa,
On 2017/7/19 上午5:22, Cleber Rosa wrote:
On 07/18/2017 02:07 PM, John Snow wrote:
On 07/17/2017 11:01 PM, Jing Liu wrote:
[...]
I see issues here:
1) The qemu-iotests "runner", that is, "./check", understands that a
file number is a test. No fu
On 2017/7/19 上午2:07, John Snow wrote:
On 07/17/2017 11:01 PM, Jing Liu wrote:
Hi all,
Do you anybody have iotests failure: 188, 189 and 087 of the latest qemu
upsteam?
I just wondered if it has something wrong with my test machines because
I have different results with two machines
Hi Eric,
On 2017/7/18 下午10:57, Eric Blake wrote:
On 07/17/2017 10:01 PM, Jing Liu wrote:
Hi all,
Do you anybody have iotests failure: 188, 189 and 087 of the latest qemu
upsteam?
I just wondered if it has something wrong with my test machines because
I have different results with two
Hi all,
Do you anybody have iotests failure: 188, 189 and 087 of the latest qemu
upsteam?
I just wondered if it has something wrong with my test machines because
I have different results with two machines.
Thanks.
Jing
Dear Conny,
On 07/05/2016 03:56 PM, Cornelia Huck wrote:
+
+static const TypeInfo virtual_css_bridge_info = {
+.name = TYPE_VIRTUAL_CSS_BRIDGE,
+.parent= TYPE_SYS_BUS_DEVICE,
+.instance_size = sizeof(SysBusDevice),
So we do not use VirtualCssBridge macro which inc
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