>>> Is there a better name than 'tcg_itype' ? Putting 'type' in the
>>> name of a type is a bit redundant, and suggests it contains
>>> a type rather than an insn.
>>
>> I'm open to suggestions there as well. On x86 and ia64, it won't hold an
>> entire insn, so "tcg_insn" seemed inappropriate.
>
>
> diff --git a/tci.c b/tci.c
> index 18c888e..94b7851 100644
> --- a/tci.c
> +++ b/tci.c
> @@ -952,8 +952,16 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t
> *tb_ptr)
> break;
> #if TCG_TARGET_HAS_rot_i64
> case INDEX_op_rotl_i64:
> +t0 = *tb_ptr++;
> +
> -static inline void tcg_out_addi(TCGContext *s, int ext,
> -TCGReg rd, TCGReg rn, unsigned int aimm)
> +static void tcg_out_addi(TCGContext *s, int ext, TCGReg rd, TCGReg rn,
> + tcg_target_long aimm)
> {
> -/* add immediate aimm unsign
> static inline Int128 int128_neg(Int128 a)
> {
> -a.lo = ~a.lo;
> -a.hi = ~a.hi;
> -return int128_add(a, int128_one());
> +uint64_t lo = -a.lo;
> +return (Int128) { lo, ~a.hi + !lo };
> }
This leaves int128_one unused. (Also the temporary lo seems a bit
pointless, since you
> diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
> index b6eed1f..cb89419 100644
> --- a/tcg/arm/tcg-target.h
> +++ b/tcg/arm/tcg-target.h
> @@ -73,10 +73,13 @@ typedef enum {
> #define TCG_TARGET_HAS_eqv_i32 0
> #define TCG_TARGET_HAS_nand_i32 0
> #define TCG_TARGET_H
> @@ -458,7 +458,15 @@ static inline void cpu_to_32wu(uint32_t *p, uint32_t v)
>
> static inline unsigned long leul_to_cpu(unsigned long v)
> {
> -return le_bswap(v, HOST_LONG_BITS);
> +/* In order to break an include loop between here and
> + qemu-common.h, don't rely on HOST_LONG_
> Checkpatch doesn't work well with the pattern
>
> #ifdef SOMETHING
> if (foo) {
> bar();
> } else
> #endif
> {
> baz1();
> baz2();
> }
>
> Which is exactly the case for all three errors reported in this series.
> I know of no other good way to arrange this
> @@ -621,6 +627,87 @@ static TCGArg *tcg_constant_folding(TCGContext *s,
> uint16_t *tcg_opc_ptr,
> break;
> }
>
> +/* Simplify using known-zero bits */
> +mask = -1;
> +switch (op) {
> +CASE_OP_32_64(ext8s):
> +if ((temps[args[1]].
Eric Blake wrote:
> assert(start >= 0 && length > 0 && (unsigned) start + length <= 64);
This is shorter and avoids the ugly cast:
assert(start >= 0 && length > 0 && length <= 64 - start);
Jay.
On 30 Oct 2011, Avi Kivity wrote:
> The memory API supports 64-bit buses (e.g. PCI). A size on such a bus cannot
> be represented with a 64-bit data type, if both 0 and the entire address
> space size are to be represented. Futhermore, any address arithemetic may
> overflow and return unexpected
> +/* Attempt to free the storage associated with the local symbols
> + that we threw away. Whether or not this has any effect on the
> + memory allocation depends on the malloc implementation and how
> + many symbols we managed to discard. */
> syms = realloc(syms, nsy
On 25 February 2010 18:05, Stefan Weil wrote:
> b551ec04ca45d1925417dd2ec7c1b7f115c84f1d fixed
> the compilation for 32 bit hosts, but introduced
> a new error for 64 bit hosts:
Sorry. Thanks for fixing it.
Jay.
> Can you try this patch:
It works! Thanks.
> and if it works, possibly only each hunk of it?
Just the first hunk: works!
Just the second hunk: doesn't work
Can you explain why the volatile is necessary? Or is it working around
a problem with the compiler?
Thanks,
Jay.
On 23 February 2010 17:03, Aurelien Jarno wrote:
> Jay Foad a écrit :
>> I'm building QEMU mipsel-linux-user with Ubuntu's GCC 4.4 on an x86
>> host. Whenever I try to run a trivial MIPS executable, QEMU segfaults
>> in cpu_loop() shortly after the call to cpu_mips_
I'm building QEMU mipsel-linux-user with Ubuntu's GCC 4.4 on an x86
host. Whenever I try to run a trivial MIPS executable, QEMU segfaults
in cpu_loop() shortly after the call to cpu_mips_exec().
The problem seems to be that cpu_exec() doesn't preserve ebp. It tries to:
saved_env_reg = (host_r
>> --- a/tcg/ppc/tcg-target.c
>> +++ b/tcg/ppc/tcg-target.c
>> @@ -1693,7 +1693,6 @@ static const TCGTargetOpDef ppc_op_defs[] = {
>> { INDEX_op_qemu_ld16u, { "r", "L" } },
>> { INDEX_op_qemu_ld16s, { "r", "L" } },
>> { INDEX_op_qemu_ld32u, { "r", "L" } },
>> - { INDEX_op_qemu_ld3
>> Does it build if you remove line 1696? If so, I'd suggest doing that.
>>
>
> Yes, that fixes it. Please grep through all tcg targets and send a patch
> removing all references to ld32s if you think it's not necessary.
Done. Unfortunately I'm not in a position to try building any of the
affected
The qemu_ld32s op is only defined if TCG_TARGET_REG_BITS == 64.
Signed-off-by: Jay Foad
---
tcg/hppa/tcg-target.c |1 -
tcg/ppc/tcg-target.c |2 --
tcg/sparc/tcg-target.c |4
3 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/tcg/hppa/tcg-target.c b/tcg/hppa/tcg
> This patch breaks building on ppc32. Reverting it makes it compile again:
> /suse/agraf/git/qemu/tcg/ppc/tcg-target.c:1696: error:
> ‘INDEX_op_qemu_ld32s’ undeclared here (not in a function)
Does it build if you remove line 1696? If so, I'd suggest doing that.
Thanks,
Jay.
Use 32-bit arithmetic for the address offset calculation to fix a
build failure on 32-bit hosts.
Signed-off-by: Jay Foad
---
target-sparc/translate.c | 22 +++---
1 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/target-sparc/translate.c b/target-sparc
On 32-bit hosts op_qemu_ld32s is unused. Remove it to fix the
following assertion failure:
qemu-alpha: tcg/tcg.c:1055:
tcg_add_target_add_op_defs: Assertion `tcg_op_defs[op].used' failed.
Signed-off-by: Jay Foad
---
tcg/tcg-opc.h |5 -
1 files changed, 0 insertions(+), 5 dele
> Yes, except for the Signed-off-by: line.
Do I need to resend it for that? And if so, does that make it PATCH v2
(even though the patch hasn't changed)?
Or can I just put the fixed Signed-off-by: line in a reply?
Thanks,
Jay.
2s op appears to be
unused on 32-bit hosts. Is it OK to just remove it?
Signed-off-by: Jay Foad
---
tcg/tcg-opc.h |5 -
1 files changed, 0 insertions(+), 5 deletions(-)
diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
index 89db3b4..838f1f4 100644
--- a/tcg/tcg-opc.h
+++ b/tcg/tcg-opc.h
@@ -2
/foad/git/qemu/tcg/tcg-op.h:422: note: expected ‘TCGv_i32’ but
argument is of type ‘TCGv_i64’
make[1]: *** [translate.o] Error 1
Does this look like a reasonable fix?
Signed-off-by: Jay Foad
---
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 7e9f0cf..b7d2a32 100644
--- a
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