map-individuals
> @@ -16,3 +16,25 @@ aurel...@aurel32.net
...
> +jho...@kernel.org
This is currently accurate, though most of my contributions were while
working at ImgTec / MIPS. If thats fine,
Acked-by: James Hogan
Cheers
James
On Sun, Feb 16, 2020 at 05:33:44PM +0100, Aleksandar Markovic wrote:
> OK, I will add the patch in the next MIPS queue, since I think its
> significance is more than trivial. It will be sent no later than two weeks
> from now.
Thanks Aleksandar.
> I just wanted the patch to be in the same queue w
On Thu, Feb 13, 2020 at 01:34:57AM +0100, Aleksandar Markovic wrote:
> On Wed, Feb 12, 2020 at 7:44 PM Philippe Mathieu-Daudé
> wrote:
> >
> > Cc'ing qemu-trivial@ & Paolo.
> >
>
> We are in the process of handling this within the company, and this
> patch should go via MIPS tree, not trivial tre
I haven't been active for 18 months, and don't have the hardware set up
to test KVM for MIPS, so mark it as orphaned and remove myself as
maintainer. Hopefully somebody from MIPS can pick this up.
Signed-off-by: James Hogan
Cc: Aleksandar Rikalo
Cc: Aurelien Jarno
Cc: Aleksandar Ma
On Tue, Oct 17, 2017 at 04:21:13PM +0200, Laurent Vivier wrote:
> Le 17/10/2017 à 16:13, james.ho...@imgtec.com a écrit :
> > From: James Hogan
> >
> > Update my imgtec.com email address to my kernel.org one in MAINTAINERS
> > as MIPS will soon no longer be part of Im
On Tue, Oct 17, 2017 at 04:03:04PM +0200, Laurent Vivier wrote:
> Le 17/10/2017 à 15:17, James Hogan a écrit :
> > From: James Hogan
> >
> > Update my imgtec.com email address to my kernel.org one in MAINTAINERS
> > as MIPS will soon no longer be part of Imagination
From: James Hogan
Update my imgtec.com email address to my kernel.org one in MAINTAINERS
as MIPS will soon no longer be part of Imagination Technologies, and add
a mapping in .mailcap so get_maintainer.pl reports the right address.
Signed-off-by: James Hogan
Cc: Michael Tokarev
Cc: Laurent
On Mon, Sep 11, 2017 at 12:52:59PM -0700, Alistair Francis wrote:
> Convert the fprintf() messages in kvm_mips_update_state() to use
> warn_report() as they aren't errors, but are just warnings.
>
> Signed-off-by: Alistair Francis
> Cc: James Hogan
Acked-by: James
ng");
> env->CP0_Config1 &= ~(1 << CP0C1_FP);
> }
> if (!kvm_mips_msa_cap && env->CP0_Config3 & (1 << CP0C3_MSAP)) {
> -fprintf(stderr, "Warning: KVM does not support MSA, disabling\n");
> +warn_report(&qu
On Wed, Aug 30, 2017 at 04:52:04PM -0300, Philippe Mathieu-Daudé wrote:
> Hi James,
>
> On 08/30/2017 03:19 PM, James Hogan wrote:
> [...]
> >> git://github.com/philmd/qemu.git tags/mips-qomify-20170830
> >
> > A sanity check of your branch doesn't r
Hi Philippe,
On Wed, Aug 30, 2017 at 11:41:38AM -0300, Philippe Mathieu-Daudé wrote:
> Hi Igor,
>
> On 08/30/2017 10:50 AM, Igor Mammedov wrote:
> >> [...]
> Also I couldn't test it with KVM.
> [..]
> >>
> >> I'll wait to see if there is some KVM feedback from imgtec folks before
> >> spamin
: use DISAS_EXIT for eret handling").
Fixes: e350d8ca3ac7 ("target/mips: optimize indirect branches")
Signed-off-by: James Hogan
Cc: Aurelien Jarno
Cc: Yongbok Kim
Cc: Richard Henderson
---
Although I've given this a bit of testing, I only actually hit the two
EI cases at t
a8b9 ("Add instruction counter.")
Signed-off-by: James Hogan
Cc: Aurelien Jarno
Cc: Yongbok Kim
---
I've based this on MFC0 Count, but this instruction is also available to
usermode (e.g. CONFIG_USER_ONLY), which I presume is still fine.
---
target/mips/translate.c | 11 +++
1 fi
DMTC0 CP0_Cause does a redundant gen_io_start() and gen_io_end() pair,
even though this is done for all DMTC0 operations outside of the switch
statement. Remove these redundant calls.
Fixes: 5dc5d9f055c5 ("mips: more fixes to the MIPS interrupt glue logic")
Signed-off-by: James Hogan
C
.
Please give a good look (I'm only roughly familiar with icount stuff),
and consider for v2.10.
Cc: Aurelien Jarno
Cc: Yongbok Kim
Cc: Richard Henderson
James Hogan (3):
target/mips: Use BS_EXCP where interrupts are expected
target/mips: Drop redundant gen_io_start/stop()
target/mips
On Mon, Jul 31, 2017 at 01:47:48PM -0700, Richard Henderson wrote:
> On 07/31/2017 06:09 AM, James Hogan wrote:
> > +static int mips_um_ksegs;
> > +
> > uint64_t cpu_mips_kseg0_to_phys(void *opaque, uint64_t addr)
> > {
> > return addr & 0x1f
bstate = BS_STOP for these registers for both mtc0 and dmtc0.
Fixes: 7a387fffce50 ("Add MIPS32R2 instructions, and generally straighten out
the instruction decoding. This is also the first percent towards MIPS64
support.")
Signed-off-by: James Hogan
Cc: Aurelien Jarno
Cc: Yongbok Kim
-
On Wed, Jul 19, 2017 at 08:41:26AM -0700, no-re...@patchew.org wrote:
> ERROR:/tmp/qemu-test/src/tests/test-qga.c:78:fixture_setup: assertion failed
> (fixture->fd != -1): (-1 != -1)
> GTester: last random seed: R02Sdc111f0781db4246a37f87a06bb4b260
> make: *** [check-tests/test-qga] Error 1
> make
eful to be able to run these kernels in QEMU on a PC, so enable it for
TCG too.
This also paves the way for MIPS KVM VZ support (which uses the normal
virtual memory layout) by abstracting whether user mode kernel segments
are in use.
Suggested-by: Paolo Bonzini
Signed-off-by: James Hogan
Cc: Yon
ypes.
Signed-off-by: James Hogan
Cc: Yongbok Kim
Cc: Aurelien Jarno
Cc: Paolo Bonzini
Cc: k...@vger.kernel.org
---
target/mips/helper.c | 23 +++
1 file changed, 11 insertions(+), 12 deletions(-)
diff --git a/target/mips/helper.c b/target/mips/helper.c
index a2b79e87
zini
Cc: k...@vger.kernel.org
James Hogan (2):
mips: Improve segment defs for KVM T&E guests
mips: Add KVM T&E segment support for TCG
hw/mips/addr.c| 12
hw/mips/mips_malta.c | 17 +++--
include/hw/mips/cpudevs.h | 5 +++--
target/mips/helper
elay slot address to be changed from
0xF000 to 0xF800 for these opcodes, but only when microMIPS is
in use.
Fixes: 3c824109da07 ("target-mips: microMIPS ASE support")
Signed-off-by: James Hogan
Cc: Yongbok Kim
Cc: Aurelien Jarno
Cc: Nathan Froyd
---
target/mips/translate.c
On Wed, Jul 19, 2017 at 03:54:47PM +0100, Yongbok Kim wrote:
>
>
> On 18/07/2017 12:55, James Hogan wrote:
> > Add support for the CP0_EBase.WG bit, which allows upper bits to be
> > written (bits 31:30 on MIPS32, or bits 63:30 on MIPS64), along with the
> > CP0_Config
On Wed, Jul 19, 2017 at 12:27:50PM +0200, Aurelien Jarno wrote:
> On 2017-07-18 12:55, James Hogan wrote:
> > Using MFC0 to read CP0_UserLocal uses tcg_gen_ld32s_tl, however
> > CP0_UserLocal is a target_ulong. On a big endian host with a MIPS64
> > target this reads and
On Tue, Jul 18, 2017 at 02:21:20PM -0700, no-re...@patchew.org wrote:
> Checking PATCH 2/14: target/mips: Fix TLBWI shadow flush for EHINV, XI, RI...
> ERROR: space prohibited after that '&' (ctx:WxW)
> #44: FILE: target/mips/op_helper.c:2045:
> +XI0 = (env->CP0_EntryLo0 >> CP0EnLo_XI) & 1;
>
ERL=0 and ERL=1.
Signed-off-by: James Hogan
Reviewed-by: Yongbok Kim
Cc: Aurelien Jarno
---
Changes in v2:
- Add ERL case to log output where cpu_mmu_index() is now used in
op_helper.c
---
target/mips/cpu.h | 17 +
target/mips/op_helper.c | 4
2 files changed, 17
guest).
Signed-off-by: James Hogan
Cc: Yongbok Kim
Cc: Aurelien Jarno
---
Changes in v2:
- Use hwaddr instead of target_ulong for physical addresses in
get_seg[ctl]_physical_address() (Yongbok).
- Fix xkphys privilege control based on access mode (am) (Yongbok).
- Fix xkphys TLB faults to use
Enable the CP0_EBase.WG (write gate) on the I6400 and MIPS64R2-generic
CPUs. This allows 64-bit guests to run KVM itself, which uses
CP0_EBase.WG to point CP0_EBase at XKPhys.
Signed-off-by: James Hogan
Cc: Yongbok Kim
Cc: Aurelien Jarno
---
Changes in v2:
- New patch.
---
target/mips
Add the Enhanced Virtual Addressing (EVA) feature to the P5600 core
configuration, along with the related Segmentation Control (SC) feature
and writable CP0_EBase.WG bit.
This allows it to run Malta EVA kernels.
Signed-off-by: James Hogan
Reviewed-by: Yongbok Kim
Cc: Aurelien Jarno
atomics, and a mem_idx local variable to gen_ld(), gen_st(), and
gen_st_cond().
Signed-off-by: James Hogan
Reviewed-by: Yongbok Kim
Cc: Yongbok Kim
Cc: Aurelien Jarno
---
target/mips/translate.c | 77 ++
1 file changed, 42 insertions(+), 35 deletions
Implement decoding of microMIPS EVA load and store instruction groups in
the POOL31C pool. These use the same gen_ld(), gen_st(), gen_st_cond()
helpers as the MIPS32 decoding, passing the equivalent MIPS32 opcodes as
opc.
Signed-off-by: James Hogan
Cc: Yongbok Kim
Cc: Aurelien Jarno
_idx used for the operation.
Unfortunately some Loongson 2E instructions use overlapping encodings,
so we must be careful not to prevent those from being decoded when EVA
is absent.
Signed-off-by: James Hogan
Cc: Yongbok Kim
Cc: Aurelien Jarno
---
Changes in v2:
- Fix typo in commit message (Yon
uld be
fine as get_physical_address() only compares against MIPS_HFLAG_UM and
MIPS_HFLAG_SM, neither of which should get set by compute_hflags() when
MIPS_HFLAG_DM is set.
Signed-off-by: James Hogan
Reviewed-by: Yongbok Kim
Cc: Aurelien Jarno
---
target/mips/helper.c | 17 +
1 f
Segmentation Control and Enhanced
Virtual Addressing (EVA) extensions (where KSeg1 addresses may not
represent an unmapped uncached segment).
It is also useful on MIPS64 to allow the exception base to reside in
XKPhys, and possibly out of range of KSEG0 and KSEG1.
Signed-off-by: James Hogan
Cc: Yongbok Kim
dard legacy
layout so they can be used in future patches regardless of whether they
are exposed to the guest.
Signed-off-by: James Hogan
Cc: Yongbok Kim
Cc: Aurelien Jarno
---
Changes in v2:
- Use ld_tl and ext32s_tl rather than ld32s_tl to avoid big endian host,
MIPS64 target issues (Yon
ry")
Fixes: 9456c2fbcd82 ("target-mips: add TLBINV support")
Signed-off-by: James Hogan
Cc: Yongbok Kim
Cc: Aurelien Jarno
---
Changes in v2:
- New patch.
---
target/mips/op_helper.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/target/mips/
is added.
Signed-off-by: James Hogan
Reviewed-by: Yongbok Kim
Cc: Aurelien Jarno
---
Changes in v2:
- Also convert reference to hflags & MIPS_HFLAG_KSU in op_helper.c to
cpu_mmu_index (Yongbok).
---
target/mips/cpu.h | 8 +++-
target/mips/op_helper.c | 4 ++--
target/
extend it, as done for various other target_ulong COP0 registers.
Fixes: d279279e2b5c ("target-mips: implement UserLocal Register")
Signed-off-by: James Hogan
Cc: Yongbok Kim
Cc: Aurelien Jarno
Cc: Petar Jovanovic
---
Changes in v2:
- New patch.
---
target/mips/translate.c | 5 +++
es in these cases to only flush the QEMU
TLB.
Signed-off-by: James Hogan
Cc: Yongbok Kim
Cc: Aurelien Jarno
---
Changes in v2:
- New patch.
---
target/mips/helper.c| 2 +-
target/mips/op_helper.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/mips/helper.c b/target
g for physical addresses in
get_seg[ctl]_physical_address() (Yongbok).
- Fix xkphys privilege control based on access mode (am) (Yongbok).
- Fix xkphys TLB faults to use XTLB.
- New patch 14.
Cc: Yongbok Kim
Cc: Aurelien Jarno
Cc: Petar Jovanovic
James Hogan (14):
target/mips: Fix M
On Thu, Oct 13, 2016 at 02:06:25PM +0100, Yongbok Kim wrote:
>
>
> On 06/09/2016 12:03, James Hogan wrote:
> > Implement the optional segmentation control feature in the virtual to
> > physical address translation code.
> >
> > The fixed legacy segment and X
On Mon, Oct 10, 2016 at 03:57:08PM +0100, Yongbok Kim wrote:
>
>
> On 06/09/2016 12:03, James Hogan wrote:
> > The optional segmentation control registers CP0_SegCtl0, CP0_SegCtl1 &
> > CP0_SegCtl2 control the behaviour and required privilege of the legacy
&g
On Thu, Oct 13, 2016 at 02:18:31PM +0100, Yongbok Kim wrote:
>
>
> On 06/09/2016 12:03, James Hogan wrote:
> > The segmentation control feature allows a legacy memory segment to
> > become unmapped uncached at error level (according to CP0_Status.ERL),
> > and in fact
On Fri, Oct 07, 2016 at 05:08:46PM +0100, Yongbok Kim wrote:
> On 06/09/2016 12:03, James Hogan wrote:
> > The MIPS mmu_idx is sometimes calculated from hflags without an env
> > pointer available as cpu_mmu_index() requires.
> >
> > Create a common hflags_mmu_inde
On Fri, Oct 07, 2016 at 04:48:31PM +0100, Yongbok Kim wrote:
> On 06/09/2016 12:03, James Hogan wrote:
> > diff --git a/target-mips/helper.c b/target-mips/helper.c
> > index 29ebf391cb94..2065fc3ec119 100644
> > --- a/target-mips/helper.c
> > +++ b/target-mips/helpe
Hi Marcel,
On Tue, Mar 21, 2017 at 04:16:58PM +0200, Marcel Apfelbaum wrote:
> Can you please check if the below patch fixes the problem?
> Please note it is not a solution.
>
> diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c
> index f9b7244..5b4d429 100644
> --- a/hw/virtio/virtio-p
Hi,
I've bisected the following failure of the virtio_net linux v4.10 driver
to probe in QEMU v2.9.0-rc1 emulating a MIPS Malta machine:
virtio_net virtio0: virtio: device uses modern interface but does not have
VIRTIO_F_VERSION_1
virtio_net: probe of virtio0 failed with error -22
To QEMU commi
On Fri, Dec 02, 2016 at 11:16:41AM +, James Hogan wrote:
> Hi,
>
> On Thu, Dec 01, 2016 at 09:51:59PM +0800, Jin Guojie wrote:
> > * Tested successfully on following machines:
> >
> > | HOST
Hi,
On Thu, Dec 01, 2016 at 09:51:59PM +0800, Jin Guojie wrote:
> * Tested successfully on following machines:
>
> | HOST| qemu-system | Debian ISO |
> |-|
> | mips 32 le |i386 |i386 |
> | mips 32 le |x86_6
On Wed, Nov 30, 2016 at 12:30:19PM -0800, Richard Henderson wrote:
> On 11/30/2016 10:39 AM, Jin Guojie wrote:
> > But even Su cannot provide an R6 machine.
>
> Ok, I guess we will just have to drop the R6 patches for now, until imgtec is
> able to provide feedback on them.
It booted a mips64r6 g
Hi Richard,
On Wed, Nov 30, 2016 at 12:30:19PM -0800, Richard Henderson wrote:
> On 11/30/2016 10:39 AM, Jin Guojie wrote:
> > But even Su cannot provide an R6 machine.
>
> Ok, I guess we will just have to drop the R6 patches for now, until imgtec is
> able to provide feedback on them.
I'm alrea
Hi Richard,
On Tue, Nov 15, 2016 at 10:37:41PM +0100, Richard Henderson wrote:
> On 11/14/2016 10:33 AM, Jin Guojie wrote:
> > I want listen to your advice. Should I test your v2 patch on Loongson
> > and use it? Or whether it is worth modifying my patch and resubmit it
> > according to your revie
On Fri, Oct 07, 2016 at 05:05:30PM +0100, Yongbok Kim wrote:
> On 07/10/2016 16:48, James Hogan wrote:
> > On Fri, Oct 07, 2016 at 04:34:27PM +0100, Yongbok Kim wrote:
> >>> diff --git a/target-mips/translate.c b/target-mips/translate.c
> >>> index df2befbd5294
On Fri, Oct 07, 2016 at 04:34:27PM +0100, Yongbok Kim wrote:
>
>
> On 06/09/2016 12:03, James Hogan wrote:
> > Implement decoding of EVA loads and stores. These access the user
> > address space from kernel mode when implemented, so for each instruction
> > we need to
On Fri, Oct 07, 2016 at 02:42:15PM +0100, Yongbok Kim wrote:
>
>
> On 06/09/2016 12:03, James Hogan wrote:
> > Add support for the CP0_EBase.WG bit, which allows upper bits to be
> > written (bits 31:30 on MIPS32, or bits 63:30 on MIPS64), along with the
> > CP0_Config
bstate = BS_STOP for these registers for both mtc0 and dmtc0.
Fixes: 7a387fffce50 ("Add MIPS32R2 instructions, and generally straighten out
the instruction decoding. This is also the first percent towards MIPS64
support.")
Signed-off-by: James Hogan
Cc: Aurelien Jarno
Cc: Yongbok Kim
-
On Tue, Sep 06, 2016 at 04:18:38AM -0700, no-re...@patchew.org wrote:
> Checking PATCH 1/9: target-mips: Add CP0_Ebase.WG (write gate) support...
> ERROR: space prohibited after that '&' (ctx:WxW)
> #104: FILE: target-mips/op_helper.c:1529:
> +if (arg1 & (1 << CP0EBase_WG) & env->CP0_EBase_rw_b
guest).
Signed-off-by: James Hogan
Cc: Leon Alrae
Cc: Aurelien Jarno
---
target-mips/helper.c | 154 +++-
1 file changed, 123 insertions(+), 31 deletions(-)
diff --git a/target-mips/helper.c b/target-mips/helper.c
index 2065fc3ec119..63d709bd620f 100644
dard legacy
layout so they can be used in future patches regardless of whether they
are exposed to the guest.
Signed-off-by: James Hogan
Cc: Leon Alrae
Cc: Aurelien Jarno
---
target-mips/cpu.h | 31 -
target-mips/helper.h| 3 ++-
target-mips/machine.c | 7 ++--
ta
ERL=0 and ERL=1.
Signed-off-by: James Hogan
Cc: Leon Alrae
Cc: Aurelien Jarno
---
target-mips/cpu.h | 17 +
target-mips/op_helper.c | 2 ++
2 files changed, 15 insertions(+), 4 deletions(-)
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 8ddc965e4735..2abb33027
Segmentation Control and Enhanced
Virtual Addressing (EVA) extensions (where KSeg1 addresses may not
represent an unmapped uncached segment).
It is also useful on MIPS64 to allow the exception base to reside in
XKPhys, and possibly out of range of KSEG0 and KSEG1.
Signed-off-by: James Hogan
Cc: Leon Alrae
atomics, and a mem_idx local variable to gen_ld(), gen_st(), and
gen_st_cond().
Signed-off-by: James Hogan
Cc: Leon Alrae
Cc: Aurelien Jarno
---
target-mips/translate.c | 77 ++
1 file changed, 42 insertions(+), 35 deletions(-)
diff --git a/target-mips
Add the Enhanced Virtual Addressing (EVA) feature to the P5600 core
configuration, along with the related Segmentation Control (SC) feature
and writable CP0_EBase.WG bit.
This allows it to run Malta EVA kernels.
Signed-off-by: James Hogan
Cc: Leon Alrae
Cc: Aurelien Jarno
---
target-mips
used for the operation.
Unfortunately some Loongson 2E instructions use overlapping encodings,
so we must be careful not to prevent those from being decoded when EVA
is absent.
Signed-off-by: James Hogan
Cc: Leon Alrae
Cc: Aurelien Jarno
---
target-mips/translate.c |
is changed. This should
be done at some point, but wasn't necessary for my purposes.
Cc: Leon Alrae
Cc: Aurelien Jarno
James Hogan (9):
target-mips: Add CP0_Ebase.WG (write gate) support
target-mips: Prepare loads/stores for EVA
target-mips: Decode EVA load & store instructions
uld be
fine as get_physical_address() only compares against MIPS_HFLAG_UM and
MIPS_HFLAG_SM, neither of which should get set by compute_hflags() when
MIPS_HFLAG_DM is set.
Signed-off-by: James Hogan
Cc: Leon Alrae
Cc: Aurelien Jarno
---
target-mips/helper.c | 17 +
1 file changed
gen_intermediate_code() to use it.
This will also allow the logic to be more easily updated when a new MMU
mode is added.
Signed-off-by: James Hogan
Cc: Leon Alrae
Cc: Aurelien Jarno
---
target-mips/cpu.h | 8 +++-
target-mips/translate.c | 2 +-
2 files changed, 8 insertions(+), 2 deletions
On Thu, Apr 28, 2016 at 09:53:04AM +0100, Leon Alrae wrote:
> On 27/04/16 23:21, James Hogan wrote:
> > Commit b00c72180c36 ("target-mips: add PC, XNP reg numbers to RDHWR")
> > changed the rdhwr helpers to use check_hwrena() to check the register
> > being accesse
On Thu, Apr 28, 2016 at 10:51:28AM +0200, Aurelien Jarno wrote:
> On 2016-04-27 23:21, James Hogan wrote:
> > Commit b00c72180c36 ("target-mips: add PC, XNP reg numbers to RDHWR")
> > changed the rdhwr helpers to use check_hwrena() to check the register
> > being ac
is disabled in the outer guest's CP0_HWREna by
KVM so it can emulate the inner guest's counter. The emulation fails and
the RI exception is passed to the inner guest.
Fixes: b00c72180c36 ("target-mips: add PC, XNP reg numbers to RDHWR")
Signed-off-by: James Hogan
Cc: Leon Alr
Enable seccomp on MIPS since libseccomp version 2.2.0 when MIPS support
was first added.
Signed-off-by: James Hogan
Reviewed-by: Andrew Jones
Cc: Eduardo Otubo
Cc: Aurelien Jarno
---
configure | 3 +++
1 file changed, 3 insertions(+)
diff --git a/configure b/configure
index 5db29f0245ae
or is that considered less secure? It would seem
preferable if we could kill the whole process in a recognisable way
instead of hanging it.
Changes in v2:
- Added Peter's comment in patch 1.
James Hogan (2):
seccomp: Whitelist cacheflush since 2.2.0 not 2.2.3
configure: Enable seccomp s
to
libseccomp 2.2.0.
Signed-off-by: James Hogan
Reviewed-By: Andrew Jones
Cc: Eduardo Otubo
Cc: Aurelien Jarno
---
Changes in v2:
- Added Peter's comment
---
qemu-seccomp.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/qemu-seccomp.c b/qemu-seccomp.c
On Fri, Apr 08, 2016 at 01:49:44PM +0100, Peter Maydell wrote:
> On 8 April 2016 at 13:39, Andrew Jones wrote:
> > In that message I was referring to arm/aarch64 (the only arch at the
> > time that cared about cacheflush). 2.2.0 was the first version arm got
> > any cacheflush support (same versio
Enable seccomp on MIPS since libseccomp version 2.2.0 when MIPS support
was first added.
Signed-off-by: James Hogan
Cc: Eduardo Otubo
Cc: Aurelien Jarno
---
configure | 3 +++
1 file changed, 3 insertions(+)
diff --git a/configure b/configure
index 5db29f0245ae..f1c307bfc69c 100755
--- a
or is that considered less secure? It would seem
preferable if we could kill the whole process in a recognisable way
instead of hanging it.
James Hogan (2):
seccomp: Whitelist cacheflush since 2.2.0 not 2.2.3
configure: Enable seccomp sandbox for MIPS
configure | 3 +++
qemu-seccomp.c |
MIPS back to
libseccomp 2.2.0.
Signed-off-by: James Hogan
Cc: Eduardo Otubo
Cc: Aurelien Jarno
---
qemu-seccomp.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/qemu-seccomp.c b/qemu-seccomp.c
index 2866e3c2a660..9425dac17155 100644
--- a/qemu-seccomp.c
+++ b/qemu
es.
Fixes: 91478cefaaf2 ("tcg: Allocate indirect_base temporaries in a different
order")
Signed-off-by: James Hogan
Cc: Aurelien Jarno
Cc: Richard Henderson
---
tcg/mips/tcg-target.inc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tc
Hi Alex,
On Thu, Jan 28, 2016 at 10:15:17AM +, Alex Bennée wrote:
> The __atomic primitives have been available since GCC 4.7 and provide
> a richer interface for describing memory ordering requirements. As a
> bonus by using the primitives instead of hand-rolled functions we can
> use tools s
Hi Richard,
On Tue, Feb 09, 2016 at 09:39:55PM +1100, Richard Henderson wrote:
> @@ -1212,11 +1237,24 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg
> base, TCGReg addrl,
> : offsetof(CPUArchState, tlb_table[mem_index][0].addr_write));
> int add_off = offsetof(CPUArchState
Hi Richard,
On Tue, Feb 09, 2016 at 09:40:03PM +1100, Richard Henderson wrote:
> @@ -1313,28 +1315,30 @@ static void tcg_out_movcond(TCGContext *s, TCGCond
> cond, TCGReg ret,
> }
> }
>
> -static void tcg_out_call_int(TCGContext *s, tcg_insn_unit *arg, bool tail)
> +static void tcg_out_ca
Hi Richard,
On Tue, Feb 09, 2016 at 04:50:52PM +, James Hogan wrote:
> > @@ -589,6 +608,50 @@ static void tcg_out_movi(TCGContext *s, TCGType type,
> > }
> > if (TCG_TARGET_REG_BITS == 32 || arg == (int32_t)arg) {
> > tcg_out_opc_imm(s, OPC_LUI, ret,
Hi Richard,
On Tue, Feb 09, 2016 at 04:22:34PM +, James Hogan wrote:
> (gdb) disas/r
> Dump of assembler code for function code_gen_buffer:
>0x00fff30b0064 <+0>: f8 ff 11 8e lw s1,-8(s0)
> => 0x00fff30b0068 <+4>: 08 00 11 60 bnezal
Hi Richard,
On Tue, Feb 09, 2016 at 09:39:59PM +1100, Richard Henderson wrote:
> The DAHI and DATI instructions can eliminate two insns
> off the pre-r6 path.
>
> Signed-off-by: Richard Henderson
> ---
> tcg/mips/tcg-target.c | 63
> +++
> 1 file
Hi Richard,
On Tue, Feb 09, 2016 at 09:40:02PM +1100, Richard Henderson wrote:
> Using compact branches, when possible, avoids a delay slot nop.
>
> Signed-off-by: Richard Henderson
> ---
> include/elf.h | 4 +
> tcg/mips/tcg-target.c | 216
> +++--
Hi Richard,
Awesome, thanks for looking at these patches again :-)
On Tue, Feb 09, 2016 at 09:39:50PM +1100, Richard Henderson wrote:
> +#if !use_mips32r6_instructions
> +{ INDEX_op_muls2_i64, { "r", "r", "rZ", "rZ" } },
> +{ INDEX_op_mulu2_i64, { "r", "r", "rZ", "rZ" } },
> +#endif
this
On Thu, Feb 04, 2016 at 10:04:11AM +, Leon Alrae wrote:
> On 03/02/16 17:16, James Hogan wrote:
> > Here's a v5 refresh of my FPU/MSA patchset for v2.6. Thanks to all who
> > have taken the time to review it so far.
> >
> > This patchset primarily ad
The DPRINTFs in cpu_mips_io_interrupts_pending() and kvm_arch_pre_run()
are particularly noisy during normal execution, and also not
particularly helpful. Remove them so that more important debug messages
can be more easily seen.
Signed-off-by: James Hogan
Reviewed-by: Leon Alrae
Cc: Paolo
Add KVM register access functions for the uint32_t type. This is
required for FP and MSA control registers, which are represented as
unsigned 32-bit integers.
Signed-off-by: James Hogan
Cc: Paolo Bonzini
Cc: Leon Alrae
Cc: Aurelien Jarno
---
Changes in v3:
- Fix big endian (the pointer passed
Rename kvm_mips_{get,put}_one_reg64() to kvm_mips_{get,put}_one_ureg64()
since they take an int64_t pointer, and add separate signed 64-bit
accessors. These will be used for double precision floating point
registers.
Signed-off-by: James Hogan
Cc: Paolo Bonzini
Cc: Leon Alrae
Cc: Aurelien
.MSAP) and so that QEMU can
save/restore the guest modifiable bits (Config5.MSAEn). The MSACSR/MSAIR
registers and the MSA vector registers are now saved/restored. Since the
FP registers are a subset of the vector registers, they are omitted if
the guest has MSA.
Signed-off-by: James Hogan
Cc: Paolo
es in patch 5, 8 & 9 to
avoid compiler undefined behaviour (Leon).
James Hogan (7):
mips/kvm: Remove a couple of noisy DPRINTFs
mips/kvm: Implement PRid CP0 register
mips/kvm: Implement Config CP0 registers
mips/kvm: Support unsigned KVM registers
mips/kvm: Support signed 64-bit KVM r
nd so that QEMU can
save/restore the guest modifiable bits (Config5.FRE, Config5.UFR,
Config5.UFE). The FCSR/FIR registers and the floating point registers
are now saved/restored (depending on the FR mode bit).
Signed-off-by: James Hogan
Cc: Paolo Bonzini
Cc: Leon Alrae
Cc: Aurelien Jarno
---
Ch
them on migration/savevm.
Signed-off-by: James Hogan
Cc: Paolo Bonzini
Cc: Leon Alrae
Cc: Aurelien Jarno
---
Changes in v2:
- Fix line wrapping of kvm_mips_get_one_reg() calls from Config4 and
Config5 (Leon).
- Change (1 << x) to (1U << x) in important places to avoid compil
Implement saving and restoring to KVM state of the Processor ID (PRid)
CP0 register. This allows QEMU to control the PRid exposed to the guest
instead of using the default set by KVM.
Signed-off-by: James Hogan
Reviewed-by: Leon Alrae
Cc: Paolo Bonzini
Cc: Aurelien Jarno
---
target-mips
e
> and only the C code needs to use the alternative 'q_mips' spelling.
>
> CC: James Hogan
> Signed-off-by: Eric Blake
Thanks, that fixes the build for me.
Tested-by: James Hogan
Cheers
James
> ---
> scripts/qapi.py | 2 +-
> cpus.c | 4 ++--
>
Hi Leon,
On Tue, Feb 02, 2016 at 09:58:46AM +, Leon Alrae wrote:
> Hi James,
>
> On 18/12/15 10:46, James Hogan wrote:
> > @@ -611,17 +664,51 @@ static int kvm_mips_get_fpu_registers(CPUState *cs)
> > restore_flush_mode(env);
> > }
> >
Hi Eric,
On 18 November 2015 at 08:52, Eric Blake wrote:
> +# An enumeration of cpu types that enable additional information during
> +# @query-cpus.
> +#
> +# Since: 2.6
> +##
> +{ 'enum': 'CpuInfoArch',
> + 'data': ['x86', 'sparc', 'ppc', 'mips', 'tricore', 'other' ] }
> +
...
> +##
> +# @Cp
sing the uint64 type in the first place.
>
> Signed-off-by: Peter Maydell
> ---
> fpu/softfloat.c | 10 +-
> include/fpu/softfloat.h | 9 -
> target-alpha/fpu_helper.c | 2 +-
> target-mips/kvm.c | 4 ++--
Thanks! For MIPS KVM bits:
Acked
t; Signed-off-by: Andrey Smetanin
> CC: Paolo Bonzini
> CC: Gleb Natapov
> CC: James Hogan
> CC: Paolo Bonzini
> CC: Paul Burton
> CC: Ralf Baechle
> CC: Alexander Graf
> CC: Christian Borntraeger
> CC: Cornelia Huck
> CC: linux-m...@linux-mips.org
> CC: kvm-...
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