This patchset implements MIPS Enhanced Virtual Addressing (EVA) support in QEMU.
This consists of the following architectural features: - Patch 1: CP0_EBase.WG (write gate). This allows more bits of CP0_EBase to be written, which allows the exception vector to be moved into a different segment than kseg0/kseg1. The related CP0_Config5.CV allows cache error exceptions not to be forced to get handled by KSeg1. - Patches 2-4: EVA user memory access instructions (CP0_Config5.EVA). These allow kernel code to access the user mode view of memory, which can no longer be done reliably with normal memory access instructions for MUSUK segment access mode (see below). - Patches 5-8: Segmentation control (CP0_Config3.SC). New cop0 registers are added to reconfigure the virtual memory segments. This allows the traditionally fixed virtual memory segments to be rearranged, and also allows segments to appear differently based on execution mode, for example the access mode MUSUK (Mapped User Supervisor, Unmapped Kernel) makes a segment TLB mapped to user mode and cached unmapped (direct window to physical) to kernel mode, and if EU=1 it is also uncached unmapped to error level (which requires the addition of a new MMU mode). Patch 9 adds the required capabilities to the P5600 CPU type to allow a Malta EVA kernel to be executed. Notable limitations: - Neither CACHEE (the new EVA instruction) or CACHE (the pre-existing non-EVA instruction) generate TLB exceptions for bad addresses, as QEMU implements them only with a Cop0 privilege check. - No attempt has been made to implement BEV overlays yet, which would allow non-standard boot exception vector addresses to be accessed in kernel mode, even if the underlying segment is changed. This should be done at some point, but wasn't necessary for my purposes. Cc: Leon Alrae <leon.al...@imgtec.com> Cc: Aurelien Jarno <aurel...@aurel32.net> James Hogan (9): target-mips: Add CP0_Ebase.WG (write gate) support target-mips: Prepare loads/stores for EVA target-mips: Decode EVA load & store instructions target-mips: Check memory permissions with mem_idx target-mips: Abstract mmu_idx from hflags target-mips: Add an MMU mode for ERL target-mips: Add segmentation control registers target-mips: Implement segmentation control target-mips: Add EVA support to P5600 target-mips/cpu.h | 58 +++++++- target-mips/helper.c | 184 ++++++++++++++++++------ target-mips/helper.h | 3 +- target-mips/machine.c | 9 +- target-mips/op_helper.c | 39 ++++- target-mips/translate.c | 277 ++++++++++++++++++++++++++++++------ target-mips/translate_init.c | 15 +- 7 files changed, 485 insertions(+), 100 deletions(-) -- git-series 0.8.10
