On 7/31/25 21:29, Gustavo Romero wrote:
Hi Stefan and Pierrick,
On 7/31/25 16:23, Pierrick Bouvier wrote:
On 7/31/25 11:58 AM, Gustavo Romero wrote:
Hi,
On 7/28/25 17:14, Gustavo Romero wrote:
Hi,
On 7/28/25 16:03, Pierrick Bouvier wrote:
Hi Alex,
On 7/27/25 1:32 AM, Alex Bennée wrote
Hi Stefan and Pierrick,
On 7/31/25 16:23, Pierrick Bouvier wrote:
On 7/31/25 11:58 AM, Gustavo Romero wrote:
Hi,
On 7/28/25 17:14, Gustavo Romero wrote:
Hi,
On 7/28/25 16:03, Pierrick Bouvier wrote:
Hi Alex,
On 7/27/25 1:32 AM, Alex Bennée wrote:
As our set of multiarch tests has grown
excludes the tests passed via EXTRA_RUNS_WITH_PLUGIN
from the rules created by the shuffled combination of tests and plugins,
to avoid running the tests twice, and generates the rules for the
test/plugin combinations listed in the EXTRA_RUNS_WITH_PLUGIN variable.
Signed-off-by: Gustavo Romero
---
tests
Hi,
On 7/31/25 15:52, Gustavo Romero wrote:
Commit 25aaf0cb7f (“tests/tcg: reduce the number of plugin test
combinations”) added support for running tests with specific plugins
passed via the EXTRA_RUNS variable.
However, due to the optimization, the rules generated as a shuffled
combination
Hi Pierrick,
On 7/31/25 16:23, Pierrick Bouvier wrote:
On 7/31/25 11:58 AM, Gustavo Romero wrote:
Hi,
On 7/28/25 17:14, Gustavo Romero wrote:
Hi,
On 7/28/25 16:03, Pierrick Bouvier wrote:
Hi Alex,
On 7/27/25 1:32 AM, Alex Bennée wrote:
As our set of multiarch tests has grown the practice
Hi,
On 7/28/25 17:14, Gustavo Romero wrote:
Hi,
On 7/28/25 16:03, Pierrick Bouvier wrote:
Hi Alex,
On 7/27/25 1:32 AM, Alex Bennée wrote:
As our set of multiarch tests has grown the practice of running every
plugin with every test is becoming unsustainable. If we switch to
ensuring every
generate the rules
for the tests passed via EXTRA_RUNS.
This commit fixes it by correctly generating the rules for the tests
that require a specific plugin to run.
Signed-off-by: Gustavo Romero
---
tests/tcg/Makefile.target | 21 ---
tests/tcg/multiarch
1101 0101 0011 0010 0011 111 1
+CHKFEAT 1101 0101 0011 0010 0101 000 1
]
# The canonical NOP has CRm == op2 == 0, but all of the space
# that isn't specifically allocated to an instruction must NOP
Reviewed-by: Gustavo Romero
Cheers,
Gustavo
Hi,
On 7/28/25 16:03, Pierrick Bouvier wrote:
Hi Alex,
On 7/27/25 1:32 AM, Alex Bennée wrote:
As our set of multiarch tests has grown the practice of running every
plugin with every test is becoming unsustainable. If we switch to
ensuring every test gets run with at least one plugin we can spe
Hi Peter,
On 7/25/25 11:47, Peter Maydell wrote:
On Fri, 25 Jul 2025 at 15:38, Gustavo Romero wrote:
Hi Phil,
On 7/25/25 10:18, Philippe Mathieu-Daudé wrote:
Hi Gustavo,
On 25/7/25 03:47, Gustavo Romero wrote:
if (stage2idx == ARMMMUIdx_Stage2_S) {
-s2walk_secure
Hi Phil,
On 7/25/25 10:18, Philippe Mathieu-Daudé wrote:
Hi Gustavo,
On 25/7/25 03:47, Gustavo Romero wrote:
Clean up the definitions of NSW and NSA fields in the VTCR register.
These two fields are already defined properly using FIELD() so they are
actually duplications. Also, define the NSW
-by: Gustavo Romero
---
target/arm/internals.h | 8 +++-
target/arm/ptw.c | 8
2 files changed, 7 insertions(+), 9 deletions(-)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index c4765e4489..052f7b641c 100644
--- a/target/arm/internals.h
+++ b/target/arm
Hi Michael,
On 5/30/25 16:20, Michael Tokarev wrote:
Hi!
For quite some time (almost whole day yesterday) I'm trying to find out
what's going on with mmtcg in qemu. There's apparently a race condition
somewhere, like a use-after-free or something.
It started as an incarnation of
https://gitla
x27;s guidelines about proper commit
messages etc.
+4. Write a descriptive cover later with ``b4 prep --edit-cover``.
Nit: You meant "cover letter" here maybe?
Otherwise:
Reviewed-by: Gustavo Romero
Cheers,
Gustavo
+5. Add maintainer and reviewer CCs with ``b4 prep --auto-to-cc`
Hi Pierrick!
On 7/16/25 02:56, Pierrick Bouvier wrote:
On 7/15/25 8:13 PM, Gustavo Romero wrote:
Hi Pierrick,
On 7/14/25 22:26, Pierrick Bouvier wrote:
On 7/14/25 4:31 PM, Gustavo Romero wrote:
Hi folks,
Richard, thanks for v8. Pierrick, thanks for testing it. :)
On 7/14/25 14:09
Hi Pierrick,
On 7/14/25 22:26, Pierrick Bouvier wrote:
On 7/14/25 4:31 PM, Gustavo Romero wrote:
Hi folks,
Richard, thanks for v8. Pierrick, thanks for testing it. :)
On 7/14/25 14:09, Pierrick Bouvier wrote:
On 7/14/25 8:58 AM, Richard Henderson wrote:
Changes for v8:
- Re-order
Hi folks,
Richard, thanks for v8. Pierrick, thanks for testing it. :)
On 7/14/25 14:09, Pierrick Bouvier wrote:
On 7/14/25 8:58 AM, Richard Henderson wrote:
Changes for v8:
- Re-order SCTLR2 and TCR2 so that they are independent of MEC.
- Enable the SCTLR2 and TCR2 enable bits.
- Squa
Hi Richard,
On 7/14/25 09:58, Richard Henderson wrote:
On 7/14/25 00:21, Pierrick Bouvier wrote:
On 7/13/25 2:59 PM, Richard Henderson wrote:
On 7/11/25 08:08, Gustavo Romero wrote:
Add FEAT_TCR2, which introduces the TCR2_EL1 and TCR2_EL2 registers.
These registers are extensions of the
: Gustavo Romero
Reviewed-by: Richard Henderson
---
target/arm/helper.c | 24
1 file changed, 24 insertions(+)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 973b276d90..ce981191b3 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -5225,6 +5225,18
context is not
possible. An encryption context allow the selection of a memory
encryption engine.
At this point, no real memory encryption is supported, but software
stacks that rely on FEAT_MEC to run should work properly.
Signed-off-by: Gustavo Romero
Reviewed-by: Richard Henderson
---
docs
.
FEAT_MEC also requires two new cache management instructions, not
included in this commit, that will be implemented in a subsequent commit.
Signed-off-by: Gustavo Romero
Reviewed-by: Richard Henderson
---
target/arm/cpu-features.h | 5 +++
target/arm/cpu.c | 3 ++
target/arm/cpu.h
The MECEn bit in SCR_EL3 enables access to the EL2 MECID registers from
EL2, so add it to the SCR mask list to use it later on.
Signed-off-by: Gustavo Romero
Reviewed-by: Richard Henderson
---
target/arm/cpu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/arm/cpu.h b/target/arm
the moment, the FEAT_TCR2 only implements the
AMEC bits for now.
Signed-off-by: Gustavo Romero
---
docs/system/arm/emulation.rst | 1 +
target/arm/cpu-features.h | 5 +++
target/arm/cpu.c | 3 ++
target/arm/cpu.h | 2 ++
target/arm/helper.c | 62
in CTLR2_EL2 and SCTLR2_EL3.
Signed-off-by: Gustavo Romero
Reviewed-by: Richard Henderson
---
docs/system/arm/emulation.rst | 1 +
target/arm/cpu-features.h | 5 +++
target/arm/cpu.c | 3 ++
target/arm/cpu.h | 15 +++
target/arm/helper.c | 80
rently exploring possibilities to support FEAT_MEC encryption (or
obfuscation, for testing purposes) in QEMU for the various translation regimes
on arm64, hence the encryption part of FEAT_MEC will be contributed later and is
not targeted for QEMU 10.1.
Cheers,
Gustavo
Gustavo Romero (6):
tar
.
FEAT_MEC also requires two new cache management instructions, not
included in this commit, that will be implemented in a subsequent commit.
Signed-off-by: Gustavo Romero
Reviewed-by: Richard Henderson
---
target/arm/cpu-features.h | 5 +++
target/arm/cpu.h | 9 +
target/arm
x27;m currently exploring possibilities to support FEAT_MEC encryption (or
obfuscation, for testing purposes) in QEMU for the various translation regimes
on arm64, hence the encryption part of FEAT_MEC will be contributed later and is
not targeted for QEMU 10.1.
Cheers,
Gustavo
Gustavo Romero (6):
in CTLR2_EL2 and SCTLR2_EL3.
Signed-off-by: Gustavo Romero
Reviewed-by: Richard Henderson
---
docs/system/arm/emulation.rst | 1 +
target/arm/cpu-features.h | 5 +++
target/arm/cpu.h | 15 +++
target/arm/helper.c | 80 +++
target
the moment, the FEAT_TCR2 only implements the
AMEC bits for now.
Signed-off-by: Gustavo Romero
---
docs/system/arm/emulation.rst | 1 +
target/arm/cpu-features.h | 5 +++
target/arm/cpu.h | 2 ++
target/arm/helper.c | 62 +++
target/arm
: Gustavo Romero
Reviewed-by: Richard Henderson
---
target/arm/helper.c | 24
1 file changed, 24 insertions(+)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index ecfd53cc5a..c030f0a0da 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6856,6 +6856,18
context is not
possible. An encryption context allow the selection of a memory
encryption engine.
At this point, no real memory encryption is supported, but software
stacks that rely on FEAT_MEC to run should work properly.
Signed-off-by: Gustavo Romero
Reviewed-by: Richard Henderson
---
docs
The MECEn bit in SCR_EL3 enables access to the EL2 MECID registers from
EL2, so add it to the SCR mask list to use it later on.
Signed-off-by: Gustavo Romero
Reviewed-by: Richard Henderson
---
target/arm/cpu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/arm/cpu.h b/target/arm
context is not
possible. An encryption context allow the selection of a memory
encryption engine.
At this point, no real memory encryption is supported, but software
stacks that rely on FEAT_MEC to run should work properly.
Signed-off-by: Gustavo Romero
Reviewed-by: Richard Henderson
---
docs
: Gustavo Romero
---
target/arm/helper.c | 24
1 file changed, 24 insertions(+)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 6f678aceeb..5aab9294bc 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6856,6 +6856,18 @@ static void mecid_write
the moment, the FEAT_TCR2 only implements the
AMEC bits for now.
Signed-off-by: Gustavo Romero
---
docs/system/arm/emulation.rst | 1 +
target/arm/cpu-features.h | 5 +++
target/arm/cpu.h | 2 ++
target/arm/helper.c | 60 +++
target/arm
.
FEAT_MEC also requires two new cache management instructions, not
included in this commit, that will be implemented in a subsequent commit.
Signed-off-by: Gustavo Romero
Reviewed-by: Richard Henderson
---
target/arm/cpu-features.h | 5 +++
target/arm/cpu.h | 9 +
target/arm
in CTLR2_EL2 and SCTLR2_EL3.
Signed-off-by: Gustavo Romero
Reviewed-by: Richard Henderson
---
docs/system/arm/emulation.rst | 1 +
target/arm/cpu-features.h | 5 +++
target/arm/cpu.h | 15 +++
target/arm/helper.c | 78 +++
target
ryption part of FEAT_MEC will be contributed later and is
not targeted for QEMU 10.1.
Cheers,
Gustavo
Gustavo Romero (6):
target/arm: Add the MECEn SCR_EL3 bit
target/arm: Add FEAT_MEC registers
target/arm: Add FEAT_SCTLR2
target/arm: Add FEAT_TCR2
target/arm: Implement FEAT_MEC cache instru
The MECEn bit in SCR_EL3 enables access to the EL2 MECID registers from
EL2, so add it to the SCR mask list to use it later on.
Signed-off-by: Gustavo Romero
Reviewed-by: Richard Henderson
---
target/arm/cpu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/arm/cpu.h b/target/arm
Hi Richard!
On 7/9/25 17:54, Richard Henderson wrote:
On 7/9/25 12:03, Gustavo Romero wrote:
At this point, no real memory encryption is supported, but most software
stacks that rely on FEAT_MEC to run should work properly.
s/most //?
Anyway,
Reviewed-by: Richard Henderson
Thanks a lot
in CTLR2_EL2 and SCTLR2_EL3.
Signed-off-by: Gustavo Romero
---
docs/system/arm/emulation.rst | 1 +
target/arm/cpu-features.h | 5 +++
target/arm/cpu.h | 15 +++
target/arm/helper.c | 78 +++
target/arm/internals.h| 1
context is not
possible. An encryption context allow the selection of a memory
encryption engine.
At this point, no real memory encryption is supported, but most software
stacks that rely on FEAT_MEC to run should work properly.
Signed-off-by: Gustavo Romero
---
docs/system/arm/emulation.rst | 3
the moment, the FEAT_TCR2 only implements the
AMEC bits for now.
Signed-off-by: Gustavo Romero
---
docs/system/arm/emulation.rst | 1 +
target/arm/cpu-features.h | 5 +++
target/arm/cpu.h | 2 ++
target/arm/helper.c | 60 +++
target/arm
management instructions, not
included in this commit, that will be implemented in subsequent commits.
Signed-off-by: Gustavo Romero
---
target/arm/cpu-features.h | 5 +++
target/arm/cpu.h | 11 ++
target/arm/helper.c | 70 +++
3 files changed, 86
The MECEn bit in SCR_EL3 enables access to the EL2 MECID registers from
EL2, so add it to the SCR mask list to use it later on.
Signed-off-by: Gustavo Romero
Reviewed-by: Richard Henderson
---
target/arm/cpu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/arm/cpu.h b/target/arm
: Gustavo Romero
---
target/arm/helper.c | 34 ++
1 file changed, 34 insertions(+)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 34e12bde90..36cf2b6415 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -4996,6 +4996,34 @@ static void
s
not targeted for QEMU 10.1.
Cheers,
Gustavo
Gustavo Romero (6):
target/arm: Add the MECEn SCR_EL3 bit
target/arm: Add FEAT_MEC registers
target/arm: Add FEAT_SCTLR2
target/arm: Add FEAT_TCR2
target/arm: Implement FEAT_MEC cache instructions
target/arm: Advertise FEAT_MEC in cpu max
in CTLR2_EL2 and SCTLR2_EL3.
Signed-off-by: Gustavo Romero
---
docs/system/arm/emulation.rst | 1 +
target/arm/cpu-features.h | 5 +++
target/arm/cpu.h | 15 +++
target/arm/helper.c | 78 +++
target/arm/internals.h| 1
the moment, the FEAT_TCR2 only implements the
AMEC bits for now.
Signed-off-by: Gustavo Romero
---
docs/system/arm/emulation.rst | 1 +
target/arm/cpu-features.h | 5 +++
target/arm/cpu.h | 2 ++
target/arm/helper.c | 60 +++
target/arm
management instructions, not
included in this commit, that will be implemented in subsequent commits.
Signed-off-by: Gustavo Romero
---
target/arm/cpu-features.h | 5 +++
target/arm/cpu.h | 11 ++
target/arm/helper.c | 70 +++
3 files changed, 86
T_MEC encryption (or
obfuscation, for testing purposes) in QEMU for the various translation regimes
used on arm64.
Cheers,
Gustavo
Gustavo Romero (5):
target/arm: Add the MECEn SCR_EL3 bit
target/arm: Add FEAT_MEC registers
target/arm: Add FEAT_SCTLR2
target/arm: Add FEAT_TCR2
targe
The MECEn bit in SCR_EL3 enables access to the EL2 MECID registers from
EL2, so add it to the SCR mask list to use it later on.
Signed-off-by: Gustavo Romero
Reviewed-by: Richard Henderson
---
target/arm/cpu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/arm/cpu.h b/target/arm
Hi Richard,
Thanks a lot for the reviews!
On 7/4/25 19:56, Richard Henderson wrote:
On 7/4/25 09:14, Gustavo Romero wrote:
Advertise FEAT_MEC in AA64MMFR3 ID register for the Arm64 cpu max as a
first step to fully support FEAT_MEC.
The FEAT_MEC is an extension to FEAT_RME that implements
will
be implement in a subsequent commit.
Signed-off-by: Gustavo Romero
---
docs/system/arm/emulation.rst | 1 +
target/arm/tcg/cpu64.c| 1 +
2 files changed, 2 insertions(+)
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
index 1c597d8673..1b47246d2a 100644
moment, the FEAT_TCR2 registers only
implement the bits related to FEAT_MEC for now.
Signed-off-by: Gustavo Romero
---
docs/system/arm/emulation.rst | 1 +
target/arm/cpu-features.h | 5 +
target/arm/cpu.h | 1 +
target/arm/helper.c | 40
The MECEn bit in SCR_EL3 enables access to the EL2 MECID registers from
EL2, so add it to the SCR mask list to use it later on.
Signed-off-by: Gustavo Romero
---
target/arm/cpu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 302c24e232..8ce30ca857
management instructions, not
included in this commit, that will be implemented in subsequent commits.
Signed-off-by: Gustavo Romero
---
target/arm/cpu.h| 14 +++
target/arm/helper.c | 98 +
2 files changed, 112 insertions(+)
diff --git a/target/arm
related to FEAT_MEC in CTLR2_EL2 and SCTLR2_EL3.
Signed-off-by: Gustavo Romero
---
docs/system/arm/emulation.rst | 1 +
target/arm/cpu-features.h | 5
target/arm/cpu.h | 15 +++
target/arm/helper.c | 51 +++
target/arm/tcg
will
be implement in a subsequent commit.
Signed-off-by: Gustavo Romero
---
docs/system/arm/emulation.rst | 1 +
target/arm/cpu-features.h | 5 +
target/arm/tcg/cpu64.c| 1 +
3 files changed, 7 insertions(+)
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm
, most software
stacks that rely on FEAT_MEC should work properly with this minimal support at
the moment.
I'm currently exploring possibilities to support FEAT_MEC encryption (or
obfuscation, for testing purposes) in QEMU for the various translation regimes
used on arm64.
Gustavo Rome
Add FEAT_MEC registers to the arm max cpu.
To work properly, FEAT_MEC also depends on FEAT_SCTLR2 and FEAT_TCR2, which are
not implemented in this commit. The bits in SCTLR2 and TCR2 control which
translation regimes use MECIDs, and determine which MECID is selected.
Signed-off-by: Gustavo
The MECEn bit in SCR_EL3 enables access to the EL2 MECID registers from
EL2, so add it to the SCR mask list to use it later on.
Signed-off-by: Gustavo Romero
---
target/arm/cpu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 302c24e232..8ce30ca857
heers,
Gustavo
Gustavo Romero (3):
target/arm: Add the MECEn SCR_EL3 bit
target/arm: Advertise FEAT_MEC in cpu max
target/arm: Add FEAT_MEC registers
docs/system/arm/emulation.rst | 1 +
target/arm/cpu-features.h | 5 ++
target/arm/cpu.h | 15 ++
target/arm/helper.c
context is not
possible. An encryption context allow the selection of a memory
encryption engine.
Signed-off-by: Gustavo Romero
---
docs/system/arm/emulation.rst | 1 +
target/arm/cpu-features.h | 5 +
target/arm/tcg/cpu64.c| 1 +
3 files changed, 7 insertions(+)
diff --git a/docs
at use the its_class_name() returned
value.
Signed-off-by: Philippe Mathieu-Daudé
Signed-off-by: Gustavo Romero
Reviewed-by: Richard Henderson
Reviewed-by: Eric Auger
---
hw/arm/virt-acpi-build.c | 32 +++---
include/hw/intc/arm_gicv3_its_common.h | 2 +-
2 fil
ITS-related data is correctly pruned from the ACPI tables.
The new blobs for this test will be added in a following commit.
Signed-off-by: Philippe Mathieu-Daudé
Signed-off-by: Gustavo Romero
Reviewed-by: Eric Auger
---
tests/qtest/bios-tables-test-allowed-diff.h | 2 ++
tests/qtest/bios-t
mmu_idmaps and rc_its_idmaps, respectively, to make
it clearer which nodes are involved in the mappings associated with
these variables.
Reported-by: Udo Steinberg
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2886
Signed-off-by: Gustavo Romero
Co-authored-by: Philippe Mathieu-Daudé
-
100
+[0DCh 0220 4] ID Count : FEFF
+[0E0h 0224 4] Output Base : 0100
+[0E4h 0228 4] Output Reference : 0030
+[0E8h 0232 4]Flags (decoded below) : 0000
+ Single Mapping : 0
Signed-off-by: Gustavo
t base :
+[09Ch 0156 4] ID Count : 00FF
+[0A0h 0160 4] Output Base :
+[0A4h 0164 4] Output Reference : 0030
+[0A8h 0168 4]Flags (decoded below) :
Single Mapping : 0
Signed-off-by: Gusta
actually defined in another table (in the SMMUv3 node). So
change the comment to read "RC -> SMMUv3" instead.
Signed-off-by Gustavo Romero
Reviewed-by: Eric Auger
---
hw/arm/virt-acpi-build.c | 25 +++--
1 file changed, 19 insertions(+), 6 deletions(-)
diff --git
Because 'tcg_its' in the machine instance is set based on the machine
class’s negated variable 'no_tcg_its', 'tcg_its' is the opposite of
'no_tcg_its' and hence the code in question can be simplified as:
tcg_its = !no_tcg_its.
Signed-off-by: Gustavo Rome
Factor out a new function, create_its_idmaps(), from the current
build_iort code. Add proper comments to it clarifying how the ID ranges
that go directly to the ITS Group node are computed based on the ones
that are directed to the SMMU node.
Suggested-by: Eric Auger
Signed-off-by: Gustavo
From: Philippe Mathieu-Daudé
No need to strstr() check the class name when we can use
kvm_irqchip_in_kernel() to check if the ITS from the host can be used.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Eric Auger
Reviewed-by: Gustavo Romero
---
hw/arm
/2025-06/msg03793.html
Fix ACPI tables for '-M its=off' CLI option and resolve the issue:
https://gitlab.com/qemu-project/qemu/-/issues/2886
Cheers,
Gustavo
Gustavo Romero (6):
hw/arm/virt: Simplify logic for setting instance's 'tcg_its' variable
hw/arm/virt-acpi-b
Hi Eric,
On 6/27/25 12:44, Eric Auger wrote:
Hi Gustavo,
On 6/23/25 3:57 PM, Gustavo Romero wrote:
Currently, the ITS Group nodes in the IORT table and the GIC ITS Struct
in the MADT table are always generated, even if GIC ITS is not available
on the machine.
This commit fixes it by not
Hi Eric,
Thanks a lot for another round of reviews :)
On 6/27/25 12:28, Eric Auger wrote:
Hi Gustavo,
On 6/23/25 3:57 PM, Gustavo Romero wrote:
Factor out a new function, create_its_idmaps(), from the current
I would call it build_rc_its_idmap() to be clearer on what relationship
we build
Hi Eric,
On 6/17/25 10:26, Eric Auger wrote:
Hi Gustavo,
On 6/17/25 3:01 PM, Gustavo Romero wrote:
Hi Eric,
Thanks a lot for doing a first pass on this series!
On 6/17/25 06:35, Eric Auger wrote:
Hi Gustavo,
On 6/16/25 3:18 PM, Gustavo Romero wrote:
Since v2:
- Fixed no_tcg_its inverted
ned-off-by: Gustavo Romero
Co-authored-by: Philippe Mathieu-Daudé
---
hw/arm/virt-acpi-build.c| 128
tests/qtest/bios-tables-test-allowed-diff.h | 2 +
2 files changed, 80 insertions(+), 50 deletions(-)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm
Factor out a new function, create_its_idmaps(), from the current
build_iort code. Add proper comments to it clarifying how the ID ranges
that go directly to the ITS Group node are computed based on the ones
that go to the SMMU node.
Suggested-by: Eric Auger
Signed-off-by: Gustavo Romero
---
hw
actually defined in another table (in the SMMUv3 node). So
change the comment to read "RC -> SMMUv3" instead.
Signed-off-by Gustavo Romero
---
hw/arm/virt-acpi-build.c | 25 +++--
1 file changed, 19 insertions(+), 6 deletions(-)
diff --git a/hw/arm/virt-acpi-build
t base :
+[09Ch 0156 4] ID Count : 00FF
+[0A0h 0160 4] Output Base :
+[0A4h 0164 4] Output Reference : 0030
+[0A8h 0168 4]Flags (decoded below) :
Single Mapping : 0
Signed-off-by: Gust
ITS-related data is correctly pruned from the ACPI tables.
The new blobs for this test will be added in a following commit.
Signed-off-by: Philippe Mathieu-Daudé
Signed-off-by: Gustavo Romero
---
tests/qtest/bios-tables-test-allowed-diff.h | 2 ++
tests/qtest/bios-tables-test.c | 21
Because 'tcg_its' in the machine instance is set based on the machine
class’s negated variable 'no_tcg_its', 'tcg_its' is the opposite of
'no_tcg_its' and hence the code in question can be simplified as:
tcg_its = !no_tcg_its.
Signed-off-by: Gustavo Rome
06/msg02583.html
Fix ACPI tables for '-M its=off' CLI option and resolve the issue:
https://gitlab.com/qemu-project/qemu/-/issues/2886
Cheers,
Gustavo
Gustavo Romero (6):
hw/arm/virt: Simplify logic for setting instance's 'tcg_its' variable
hw/arm/virt-acpi-build: Impr
100
+[0DCh 0220 4] ID Count : FEFF
+[0E0h 0224 4] Output Base : 0100
+[0E4h 0228 4] Output Reference : 0030
+[0E8h 0232 4]Flags (decoded below) : 0000
+ Single Mapping : 0
Signed-off-by: Gusta
From: Philippe Mathieu-Daudé
No need to strstr() check the class name when we can use
kvm_irqchip_in_kernel() to check if the ITS from the host can be used.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Eric Auger
Reviewed-by: Gustavo Romero
---
hw/arm
at use the its_class_name() returned
value.
Signed-off-by: Philippe Mathieu-Daudé
Signed-off-by: Gustavo Romero
Reviewed-by: Richard Henderson
Reviewed-by: Eric Auger
---
hw/arm/virt-acpi-build.c | 32 +++---
include/hw/intc/arm_gicv3_its_common.h | 2 +-
2 fil
Hi Eric,
On 6/17/25 10:22, Eric Auger wrote:
Hi Gustavo,
On 6/16/25 3:18 PM, Gustavo Romero wrote:
The comment about the mapping from SMMU to ITS is incorrect and it reads
"RC -> ITS". The code in question actually maps SMMU -> ITS, so the
mapping in question is not direct. Th
Hi Eric,
On 6/17/25 12:51, Eric Auger wrote:
On 6/17/25 5:12 PM, Gustavo Romero wrote:
Hi Eric,
On 6/17/25 10:34, Eric Auger wrote:
Hi Gustavo,
On 6/16/25 3:18 PM, Gustavo Romero wrote:
From: Philippe Mathieu-Daudé
Arm64 GIC ITS (Interrupt Translation Service) is an optional piece of
Hi Eric,
On 6/17/25 12:51, Eric Auger wrote:
On 6/17/25 5:12 PM, Gustavo Romero wrote:
Hi Eric,
On 6/17/25 10:34, Eric Auger wrote:
Hi Gustavo,
On 6/16/25 3:18 PM, Gustavo Romero wrote:
From: Philippe Mathieu-Daudé
Arm64 GIC ITS (Interrupt Translation Service) is an optional piece of
Hi Eric,
Thanks a lot for doing a first pass on this series!
On 6/17/25 06:35, Eric Auger wrote:
Hi Gustavo,
On 6/16/25 3:18 PM, Gustavo Romero wrote:
Since v2:
- Fixed no_tcg_its inverted logic (rth)
Since v3:
- Fixed remappings in the IORT table when ITS is no present
- Rebased on master
Hi Alex,
On 6/17/25 06:49, Alex Bennée wrote:
Gustavo Romero writes:
Add a functional test, aarch64_hotplug_pci, to exercise PCI hotplug and
hot-unplug on arm64.
Queued to testing/next, thanks.
Thanks a lot!
Cheers,
Gustavo
Hi Eric,
On 6/17/25 10:34, Eric Auger wrote:
Hi Gustavo,
On 6/16/25 3:18 PM, Gustavo Romero wrote:
From: Philippe Mathieu-Daudé
Arm64 GIC ITS (Interrupt Translation Service) is an optional piece of
hardware introduced in GICv3 and, being optional, it can be disabled
in QEMU aarch64 VMs that
) returned
value.
Signed-off-by: Philippe Mathieu-Daudé
Signed-off-by: Gustavo Romero
Reviewed-by: Richard Henderson
Reviewed-by: Eric Auger
---
hw/arm/virt-acpi-build.c | 32 +++---
include/hw/intc/arm_gicv3_its_common.h | 2 +-
2 files changed, 15 inserti
No need to strstr() check the class name when we can use
kvm_irqchip_in_kernel() to check if the ITS from the host can be used.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Eric Auger
Reviewed-by: Gustavo Romero
---
hw/arm/virt.c | 17 +++--
1
rned
value.
Signed-off-by: Philippe Mathieu-Daudé
Signed-off-by: Gustavo Romero
Reviewed-by: Richard Henderson
Reviewed-by: Eric Auger
---
hw/arm/virt-acpi-build.c | 32 +++---
include/hw/intc/arm_gicv3_its_common.h | 2 +-
2 files changed, 15 insertions(+), 19
t base :
+[09Ch 0156 4] ID Count : 00FF
+[0A0h 0160 4] Output Base :
+[0A4h 0164 4] Output Reference : 0030
+[0A8h 0168 4]Flags (decoded below) :
Single Mapping : 0
Signed-off-by: Gust
Because 'tcg_its' in the machine instance is set based on the machine
class’s negated variable 'no_tcg_its', 'tcg_its' is the opposite of
'no_tcg_its' and hence the code in question can be simplified as:
tcg_its = !no_tcg_its.
Signed-off-by: Gustavo Romero
ned-off-by: Gustavo Romero
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/virt-acpi-build.c| 152
tests/qtest/bios-tables-test-allowed-diff.h | 2 +
2 files changed, 93 insertions(+), 61 deletions(-)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm
lated data is correctly pruned from the ACPI tables.
The new blobs for this test will be added in a following commit.
Signed-off-by: Gustavo Romero
Signed-off-by: Philippe Mathieu-Daudé
---
tests/qtest/bios-tables-test-allowed-diff.h | 2 ++
tests/qtest/bios-tables-test.c | 21
1 - 100 of 477 matches
Mail list logo
