On 7/1/24 7:12 PM, Shiyang Ruan wrote:
>
>
> 在 2024/6/25 21:56, Shiyang Ruan 写道:
>>
>>
>> 在 2024/6/22 1:51, Dan Williams 写道:
>>> Shiyang Ruan wrote:
Background:
Since CXL device is a memory device, while CPU consumes a poison page of
CXL device, it always triggers a MCE by inter
On 6/19/24 2:24 AM, Shiyang Ruan wrote:
>
>
> 在 2024/6/19 7:35, Dave Jiang 写道:
>>
>>
>> On 6/18/24 9:53 AM, Shiyang Ruan wrote:
>>> Background:
>>> Since CXL device is a memory device, while CPU consumes a poison page of
>>> CXL device, it
On 6/18/24 9:53 AM, Shiyang Ruan wrote:
> Background:
> Since CXL device is a memory device, while CPU consumes a poison page of
> CXL device, it always triggers a MCE by interrupt (INT18), no matter
> which-First path is configured. This is the first report. Then
> currently, in FW-First p
On 4/17/24 12:50 AM, Shiyang Ruan wrote:
> Currently driver only traces cxl events, poison creation (for both vmem
> and pmem type) on cxl memdev is silent. OS needs to be notified then it
> could handle poison pages in time. Per CXL spec, the device error event
> could be signaled through FW-
On 3/18/24 5:38 PM, Dan Williams wrote:
> Jonathan Cameron wrote:
>> On Mon, 18 Mar 2024 10:29:28 +0800
>> Yuquan Wang wrote:
>>
>>> The dev_dbg info for Clear Event Records mailbox command would report
>>> the handle of the next record to clear not the current one.
>>>
>>> This was because the
On 2/9/24 4:54 AM, Shiyang Ruan wrote:
> Currently driver only trace cxl events, poison injection on cxl memdev
> is silent. OS needs to be notified then it could handle poison range
> in time. Per CXL spec, the device error event could be signaled through
> FW-First and OS-First methods.
>
>
On 10/9/23 08:47, Jonathan Cameron wrote:
> On Fri, 06 Oct 2023 15:15:56 -0700
> Dave Jiang wrote:
>
>> Add a simple _DSM call support for the ACPI0017 device to return fake QTG
>> ID values of 0 and 1 in all cases. This for _DSM plumbing testing from the
>> OS.
Return (Package (0x02)
{
One,
Package (0x02)
{
Zero,
One
}
})
}
}
}
Signed-off-by: Dave Jiang
Signed-off-
On 10/4/23 20:36, Michael S. Tsirkin wrote:
>
> On Wed, Oct 04, 2023 at 04:09:07PM -0700, Dave Jiang wrote:
>> Add a simple _DSM call support for the ACPI0017 device to return a fake QTG
>> ID value of 0 in all cases. The enabling is for _DSM plumbing testing
>>
{ 0x00, 0x00 }
}
})
}
}
}
Signed-off-by: Dave Jiang
Signed-off-by: Jonathan Cameron
--
v3: Fix output assignment to be BE host friendly. Fix typo in comment.
According to the CXL spec, the DSM output should be 1 WORD to indicate
the max suppoted QTG ID and a package of 0 or more WORDs for
On 9/22/23 13:08, Michael Tokarev wrote:
> 04.09.2023 16:28, Jonathan Cameron:
>> From: Dave Jiang
>>
>> According to ACPI spec 6.5 5.2.28.4 System Locality Latency and Bandwidth
>> Information Structure, if the "Entry Base Unit" is 1024 for BW and the
>
ase without a rationale...)
>>
>
> I've +CC'd the kernel CXL maintainers from Intel a few of whom
> have also contributed some of the QEMU CXL code.
> Hopefully someone can ack.
>
>>> Suggested-by: Philippe Mathieu-Daudé
>>> Signed-off-by: Jonat
On 9/18/23 10:00, Jonathan Cameron wrote:
> On Mon, 18 Sep 2023 17:31:38 +0100
> Peter Maydell wrote:
>
>> On Mon, 18 Sept 2023 at 16:04, Jonathan Cameron
>> wrote:
>>>
>>> This has been missing from the start. Assume it should match
>>> with cxl/cxl-component-utils.c as both were part of ear
On 9/4/23 09:18, Jonathan Cameron wrote:
> Description of change in previous patch.
>
> Signed-off-by: Jonathan Cameron
Reviewed-by: Dave Jiang
> ---
> tests/qtest/bios-tables-test-allowed-diff.h | 1 -
> tests/data/acpi/q35/DSDT.cxl| Bin 9655 ->
On 9/4/23 09:18, Jonathan Cameron wrote:
> Addition of QTG in following patch requires an update to the test
> data.
>
> Signed-off-by: Jonathan Cameron
Reviewed-by: Dave Jiang
> ---
> tests/qtest/bios-tables-test-allowed-diff.h | 1 +
> 1 file changed, 1 insertion
On 5/3/23 3:42 AM, Jonathan Cameron wrote:
On Tue, 18 Apr 2023 15:21:36 -0700
Dave Jiang wrote:
s small RFC patch series is really a hack on what I need from qemu rather
than a proper implementation. I'm hoping to get some guidance from the list on
how to implement this correctly for
On 5/3/23 3:42 AM, Jonathan Cameron wrote:
On Tue, 18 Apr 2023 15:21:36 -0700
Dave Jiang wrote:
s small RFC patch series is really a hack on what I need from qemu rather
than a proper implementation. I'm hoping to get some guidance from the list on
how to implement this correctly for
done
done
Linux kernel support:
https://lore.kernel.org/linux-cxl/168088732996.1441063.10107817505475386072.stgit@djiang5-mobl3/T/#t
---
Dave Jiang (3):
hw/acpi: Add support for Generic Port Affinity Structure to SRAT
genport: Add json support for generic port
acpi: add gen
Signed-off-by: Dave Jiang
---
hw/acpi/genport.c | 61 +++
hw/acpi/meson.build |1 +
hw/i386/acpi-build.c| 32 ++-
include/hw/acpi/aml-build.h |4 +--
softmmu/vl.c| 26
e set to 0 for simplicity to enable Linux kernel
side debugging and usage of the new SRAT sub-tables.
Signed-off-by: Dave Jiang
---
hw/acpi/aml-build.c | 21 +
hw/i386/acpi-build.c| 27 +++
include/hw/acpi/aml-build.h |
Add QOM json update for ACPI generic port object to support HMAT
enumeration.
Signed-off-by: Dave Jiang
---
qapi/machine.json |3 ++-
qapi/qom.json | 12
2 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/qapi/machine.json b/qapi/machine.json
index
-off-by: Jonathan Cameron
Reviewed-by: Dave Jiang
---
hw/cxl/cxl-component-utils.c | 6 +-
hw/mem/cxl_type3.c | 21 -
2 files changed, 25 insertions(+), 2 deletions(-)
diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c
index
On 3/14/23 9:53 AM, Fan Ni wrote:
Replace the magic number 32 with CXL_RAS_ERR_HEADER_NUM for better code
readability and maintainability.
Signed-off-by: Fan Ni
Reviewed-by: Dave Jiang
---
include/hw/cxl/cxl_device.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a
I'm attempting to implement the support of ACPI "generic port" detailed
in the ACPI r6.5 spec in QEMU. The spec section 5.2.16.7 details the
Generi Port Affinity Structure where it ties a Device Handle to a
Proximity Domain. And with section 6.2.28.4 for the HMAT table, the
latency and bandwidt
3,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31]
},
{
"type": "internal",
"header": [ 1, 2, 4]
}
]
}}
...
{ "execute": "cxl-inject-correctable-error",
"arguments": {
"path": "
On 2/17/23 10:29 AM, Jonathan Cameron wrote:
CXL uses PCI AER Internal errors to signal to the host that an error has
occurred. The host can then read more detailed status from the CXL RAS
capability.
For uncorrectable errors: support multiple injection in one operation
as this is needed to r
h big endian. However it is good to avoid making
things worse for that support in the future.
Signed-off-by: Jonathan Cameron
Reviewed-by: Dave Jiang
---
hw/cxl/cxl-component-utils.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/hw/cxl/cxl-comp
On 2/17/23 10:29 AM, Jonathan Cameron wrote:
This infrastructure will be reused for CXL RAS error injection
in patches that follow.
Signed-off-by: Jonathan Cameron
Reviewed-by: Dave Jiang
---
hw/pci/pci-internal.h | 1 -
include/hw/pci/pcie_aer.h | 1 +
2 files changed, 1
On 2/17/23 10:29 AM, Jonathan Cameron wrote:
This enables AER error injection to function as expected.
It is intended as a building block in enabling CXL RAS error injection
in the following patches.
Signed-off-by: Jonathan Cameron
Reviewed-by: Dave Jiang
---
hw/mem/cxl_type3.c | 13
On 2/17/23 10:29 AM, Jonathan Cameron wrote:
Done to avoid fixing ACPI route description of traditional PCI interrupts on q35
and because we should probably move with the times anyway.
Signed-off-by: Jonathan Cameron
Reviewed-by: Dave Jiang
---
hw/pci-bridge/cxl_root_port.c | 61
On 2/17/23 10:29 AM, Jonathan Cameron wrote:
We are missing necessary config write handling for AER emulation in
the CXL root port. Add it based on pcie_root_port.c
Signed-off-by: Jonathan Cameron
Reviewed-by: Dave Jiang
---
hw/pci-bridge/cxl_root_port.c | 3 +++
1 file changed, 3
being set as long as the appropriate per error class bit in the PCIe
Device Control Register is set.
Implement that branch thus enabling routing of ERR_COR, ERR_NONFATAL
and ERR_FATAL under OSes that set these bits appropriately (e.g. Linux)
Signed-off-by: Jonathan Cameron
Reviewed-by: Dave J
On 2/17/23 10:29 AM, Jonathan Cameron wrote:
This register in AER should be both writeable and should
have a default value with a couple of the errors masked
including the Uncorrectable Internal Error used by CXL for
it's error reporting.
Signed-off-by: Jonathan Cameron
Reviewed-by:
On 1/26/23 11:24 AM, Jonathan Cameron wrote:
On Thu, 26 Jan 2023 11:07:37 -0700
Dave Jiang wrote:
Hi Dave,
That was quick!
Add a simple _DSM call support for the ACPI0017 device to return a fake QTG
ID value. Given the current CXL implementation does not involve switches,
I don&#
On 1/26/23 11:24 AM, Jonathan Cameron wrote:
On Thu, 26 Jan 2023 11:07:37 -0700
Dave Jiang wrote:
Hi Dave,
That was quick!
Add a simple _DSM call support for the ACPI0017 device to return a fake QTG
ID value. Given the current CXL implementation does not involve switches,
I don&#
Add a simple _DSM call support for the ACPI0017 device to return a fake QTG
ID value. Given the current CXL implementation does not involve switches,
a faked value of 0 can be returned for the QTG ID. The enabling is for _DSM
plumbing testing from the OS.
Signed-off-by: Dave Jiang
---
hw/acpi
On 1/26/23 11:47 AM, Jonathan Cameron wrote:
On Thu, 26 Jan 2023 11:41:47 -0700
Dave Jiang wrote:
On 1/26/23 11:24 AM, Jonathan Cameron wrote:
On Thu, 26 Jan 2023 11:07:37 -0700
Dave Jiang wrote:
Hi Dave,
That was quick!
Add a simple _DSM call support for the ACPI0017 device to
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