Jonathan Cameron wrote:
> On Wed, 5 Mar 2025 18:35:40 +0800
> Yuquan Wang wrote:
>
> > >
> > > On Tue, 4 Mar 2025 14:22:48 +0800
> > > Yuquan Wang wrote:
> > >
> > > > >
> > > > > On Thu, Feb 20, 2025 at 04:12:13PM +, Jonathan Cameron wrote:
> > > > > > On Mon, 17 Feb 2025 19:20:39
.
thank you,
---
dan tan
power simulation
phone:+1.7373.099.138
email:dan...@linux.ibm.com
On 2025-02-17 14:12, Stefan Berger wrote:
On 2/16/25 5:11 PM, dan tan wrote:
*** BLURB HERE ***
Version 9 summary:
1/3 tpm/tpm_tis_spi: Support TPM for SPI
- rebased with the master, and
Yes, good point, Philippe!
I will send an update in a few days in case there are additional
changes to be made.
thank you,
---
dan tan
power simulation
phone:+1.7373.099.138
email:dan...@linux.ibm.com
On 2025-02-17 01:31, Philippe Mathieu-Daudé wrote:
Hi,
On 16/2/25 23:11, dan tan wrote
-content/uploads/TCG_PCClientTPMInterfaceSpecification_TIS__1-3_27_03212013.pdf
The SPI registers are specific to the PowerNV platform
architecture
Signed-off-by: dan tan
---
v3:
- removed the function prototypes declaration
- fixed code format to comply with convention
- changed function names
Implement support for TPM via SPI interface. The SPI bus master
is provided by PowerNV SPI device which is an SSI peripheral.
It can uses the tpm_emulator driver backend with the external
swtpm.
Signed-off-by: dan tan
---
v3:
- moved variable tis_addr from TPMStateSPI struct to local
- added
The addition to ppc/Kconfig is for building this into the
qemu-system-ppc64 binary. The enablement requires the
following command line argument:
-device tpm-tis-spi,tpmdev=tpm0,bus=pnv-spi-bus.4
Signed-off-by: dan tan
---
hw/ppc/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw
st);
- beefed up the unit test exercising major supported locality
functionality
dan tan (3):
tpm/tpm_tis_spi: Support TPM for SPI (Serial Peripheral Interface)
tpm/tpm_tis_spi: activation for the PowerNV machines
tests/qtest/tpm: add unit test to tis-spi
docs/specs/tpm.rst
From: dan tan
Register RWMR - Region Weighted Mode Register
for privileged access in Power9 and Power10
It controls what the SPURR register produces.
Specs:
- Power9: https://ibm.ent.box.com/s/tmklq90ze7aj8f4n32er1mu3sy9u8k3k
- Power10: https://files.openpower.foundation/s/EgCy7C43p2NSRfR
/170679876639.188422.11634974895844092362.st...@ltc-boston1.aus.stglabs.ibm.com/
On 1/8/25 02:21, dan tan wrote:
From: dan tan
*** BLURB HERE ***
Version 3 summary:
RWMR (Region Weighted Mode Register) -
- change the register to generic read/write from nop/write
Version 2 summary:
(DAWR1,DAWRX1):
- spec
From: dan tan
Register RWMR - Region Weighted Mode Register
for privileged access in Power9 and Power10
It controls what the SPURR register produces.
Specs:
- Power9: https://ibm.ent.box.com/s/tmklq90ze7aj8f4n32er1mu3sy9u8k3k
- Power10: https://files.openpower.foundation/s/EgCy7C43p2NSRfR
From: dan tan
The handling of the following two registers are added to POWER10 -
- DAWR1 (0x0bd, 189) - Data Address Watchpoint 1
- DAWRX1 (0x0b5, 181) - Data Address Watchpoint Extension 1
Signed-off-by: dan tan
---
ver 3 no change
ver 2 summary:
- spec reference: https
From: dan tan
*** BLURB HERE ***
Version 3 summary:
RWMR (Region Weighted Mode Register) -
- change the register to generic read/write from nop/write
Version 2 summary:
(DAWR1,DAWRX1):
- spec reference: https://files.openpower.foundation/s/EgCy7C43p2NSRfR
: dan tan
---
Ver 2 summary:
- corrected the previous definition as ITV1
- spec reference:
https://ibm.ent.box.com/s/tmklq90ze7aj8f4n32er1mu3sy9u8k3k (Power9)
- it appears that part of the previous upstream submission SPRs
(SPR_POWER_MMCR3, SPR_POWER_SIER2, SPR_POWER_SIER3
The handling of the following two registers are added to POWER10 -
- DAWR1 (0x0bd, 189) - Data Address Watchpoint 1
- DAWRX1 (0x0b5, 181) - Data Address Watchpoint Extension 1
Signed-off-by: dan tan
---
ver 2 summary:
- spec reference: https://files.openpower.foundation/s/EgCy7C43p2NSRfR
From: dan tan
*** BLURB HERE ***
Version 2 summary:
(DAWR1,DAWRX1):
- spec reference: https://files.openpower.foundation/s/EgCy7C43p2NSRfR
- corrected commit message format
- combine DAWR(0/1) handling into a single function
- add DAWR1 & DAWRX
On Thu, Dec 19, 2024 at 06:10:56PM +0300, Dan Carpenter wrote:
> > > Mind to test it with KASAN enabled?
> >
>
> Anders is going to try that later and report back.
>
Anders ran it and emailed me. I was going to tell him to respond to
the thread but I dec
After the ext4 crash then random other stuff starts
crashing as well when it allocates memory.
> > Mind to test it with KASAN enabled?
>
Anders is going to try that later and report back.
> Another thing is, how do you enable both 16K and 64K page size at the
> same time?
>
> The Kconfig should only select one page size IIRC.
Right. We tested 4k, 16k and 64k. 4k pages worked.
>
> And for the bisection, does it focus on the test failure or the crash?
>
The crash.
regards,
dan carpenter
The addition to ppc/Kconfig is for building this into the
qemu-system-ppc64 binary. The enablement requires the
following command line argument:
-device tpm-tis-spi,tpmdev=tpm0,bus=pnv-spi-bus.4
Signed-off-by: dan tan
---
hw/ppc/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw
Implement support for TPM via SPI interface. The SPI bus master
is provided by PowerNV SPI device which is an SSI peripheral.
It can uses the tpm_emulator driver backend with the external
swtpm.
Signed-off-by: dan tan
---
v3:
- moved variable tis_addr from TPMStateSPI struct to local
- added
-content/uploads/TCG_PCClientTPMInterfaceSpecification_TIS__1-3_27_03212013.pdf
The SPI registers are specific to the PowerNV platform
architecture
Signed-off-by: dan tan
---
v3:
- removed the function prototypes declaration
- fixed code format to comply with convention
- changed function names
tation support (tpm.rst);
- beefed up the unit test exercising major supported locality
functionality
dan tan (3):
tpm/tpm_tis_spi: Support TPM for SPI (Serial Peripheral Interface)
tpm/tpm_tis_spi: activation for the PowerNV machines
tests/qtest/tpm: add unit test to tis-spi
docs/s
Implement support for TPM via SPI interface. The SPI bus master
is provided by PowerNV SPI device which is an SSI peripheral.
It can uses the tpm_emulator driver backend with the external
swtpm.
Signed-off-by: dan tan
---
v3:
- moved variable tis_addr from TPMStateSPI struct to local
- added
s to the TPMStateSPI struct;
- fixed code formatting (verified by scripts/checkpatch.pl);
- per requests, make the code more readable by using self-
explanatory #defines and adding comments;
- added some documentation support (tpm.rst);
- beefed up the unit test exercising major suppo
Good point, Stefan!
Let me put it through our CI tests, which, in addition to unit tests,
also does both Linux (rhel-9) and AIX (ver7) boot exercises
thank you,
---
dan tan
power simulation
phone:+1.7373.099.138
email:dan...@linux.ibm.com
On 2024-11-08 09:38, Stefan Berger wrote:
On 11/4
MStateSPI struct;
- fixed code formatting (verified by scripts/checkpatch.pl);
- per requests, make the code more readable by using self-
explanatory #defines and adding comments;
- added some documentation support (tpm.rst);
- beefed up the unit test exercising major suppo
-content/uploads/TCG_PCClientTPMInterfaceSpecification_TIS__1-3_27_03212013.pdf
The SPI registers are specific to the PowerNV platform
architecture
Signed-off-by: dan tan
---
v3:
- removed the function prototypes declaration
- fixed code format to comply with convention
- changed function names
Implement support for TPM via SPI interface. The SPI bus master
is provided by PowerNV SPI device which is an SSI peripheral.
It can uses the tpm_emulator driver backend with the external
swtpm.
Signed-off-by: dan tan
---
v3:
- moved variable tis_addr from TPMStateSPI struct to local
- added
The addition to ppc/Kconfig is for building this into the
qemu-system-ppc64 binary. The enablement requires the
following command line argument:
-device tpm-tis-spi,tpmdev=tpm0,bus=pnv-spi-bus.4
Signed-off-by: dan tan
---
hw/ppc/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw
Hi Stefan,
What's the best way to catch these in my own local testing without
submitting it to Travis CI?
thank you,
---
dan tan
power simulation
phone:+1.7373.099.138
email:dan...@linux.ibm.com
On 2024-11-04 09:20, Stefan Berger wrote:
On 11/4/24 1:43 AM, dan tan wrote:
Add qtest
On 2024-11-04 09:14, Stefan Berger wrote:
On 11/4/24 1:43 AM, dan tan wrote:
Implement support for TPM via SPI interface. The SPI bus master
is provided by PowerNV SPI device which is an SSI peripheral.
It can uses the tpm_emulator driver backend with the external
swtpm.
Although the
umentation support (tpm.rst);
- beefed up the unit test exercising major supported locality
functionality
dan tan (3):
tpm/tpm_tis_spi: Support TPM for SPI (Serial Peripheral Interface)
tpm/tpm_tis_spi: activation for the PowerNV machines
tests/qtest/tpm: add unit test to tis-s
supported on the
PowerNV platform, thus, is big endian specific.
Signed-off-by: dan tan
---
v3:
- moved variable tis_addr from TPMStateSPI struct to local
- added the VM suspend/resume support:
- added vmstate_tpm_tis_spi declaration
- added tpm_tis_spi_pre_save() function
- fixed trace formatting
-content/uploads/TCG_PCClientTPMInterfaceSpecification_TIS__1-3_27_03212013.pdf
The SPI registers are specific to the PowerNV platform
architecture
Signed-off-by: dan tan
---
v3:
- removed the function prototypes declaration
- fixed code format to comply with convention
- changed function names
The addition to ppc/Kconfig is for building this into the
qemu-system-ppc64 binary. The enablement requires the
following command line argument:
-device tpm-tis-spi,tpmdev=tpm0,bus=pnv-spi-bus.4
Signed-off-by: dan tan
---
hw/ppc/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw
On 2024-11-02 09:19, Stefan Berger wrote:
On 11/1/24 4:27 PM, dan tan wrote:
Implement support for TPM via SPI interface. The SPI bus master
is provided by PowerNV SPI device which is an SSI peripheral.
It can uses the tpm_emulator driver backend with the external
swtpm.
Although the
The addition to ppc/Kconfig is for building this into the
qemu-system-ppc64 binary. The enablement requires the
following command line argument:
-device tpm-tis-spi,tpmdev=tpm0,bus=pnv-spi-bus.4
Signed-off-by: dan tan
---
hw/ppc/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw
self-
explanatory #defines and adding comments;
- added some documentation support (tpm.rst);
- beefed up the unit test exercising major supported locality
functionality
dan tan (3):
tpm/tpm_tis_spi: Support TPM for SPI (Serial Peripheral Interface)
tpm/tpm_tis_spi: activation fo
- changed function names and variable names to be the same
as the tpm-tis-i2c test.
- change hard coded numbers to #define's with meaningful
names that are identifiable with spec documentation
Signed-off-by: dan tan
---
tests/qtest/tpm-tis-spi-pnv-test.c
formatting string
Signed-off-by: dan tan
---
docs/specs/tpm.rst | 15 ++
include/sysemu/tpm.h | 3 +
hw/tpm/tpm_tis_spi.c | 360 +++
hw/tpm/Kconfig | 6 +
hw/tpm/meson.build | 1 +
hw/tpm/trace-events | 7 +
6 files changed, 392
igned-off-by: dan tan
---
tests/qtest/tpm-tis-spi-pnv-test.c | 220 +++--
tests/qtest/meson.build| 1 +
2 files changed, 116 insertions(+), 105 deletions(-)
diff --git a/tests/qtest/tpm-tis-spi-pnv-test.c
b/tests/qtest/tpm-tis-spi-pnv-test.c
index a3675
The addition to ppc/Kconfig is for building this into the
qemu-system-ppc64 binary. The enablement requires the
following command line argument:
-device tpm-tis-spi,tpmdev=tpm0,bus=pnv-spi-bus.4
Signed-off-by: dan tan
---
hw/ppc/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw
- moved variable tis_addr from TPMStateSPI struct to local
- added the VM suspend/resume support:
- added vmstate_tpm_tis_spi declaration
- added tpm_tis_spi_pre_save() function
- fixed trace formatting string
Signed-off-by: dan tan
---
hw/tpm/tpm_tis_spi.c | 50
://trustedcomputinggroup.org/wp-content/uploads/TCG_PCClientTPMInterfaceSpecification_TIS__1-3_27_03212013.pdf
The SPI registers are specific to the PowerNV platform
architecture
Signed-off-by: dan tan
---
hw/tpm/tpm_tis_spi.c | 2 +-
tests/qtest/tpm-tis-spi-pnv-test.c | 700
supported on the
PowerNV platform, thus, is big endian specific.
Signed-off-by: dan tan
---
docs/specs/tpm.rst | 15 ++
include/sysemu/tpm.h | 3 +
hw/tpm/tpm_tis_spi.c | 328 +++
hw/tpm/Kconfig | 6 +
hw/tpm/meson.build | 1 +
hw/tpm/trace-events
dding comments;
- added some documentation support (tpm.rst);
- beefed up the unit test exercising major supported locality
functionality
dan tan (5):
tpm/tpm_tis_spi: Support TPM for SPI (Serial Peripheral Interface)
tpm/tpm_tis_spi: activation for the PowerNV machines
tests/qtest/tpm
The addition to ppc/Kconfig is for building this into the
qemu-system-ppc64 binary. The enablement requires the
following command line argument:
-device tpm-tis-spi,tpmdev=tpm0,bus=pnv-spi-bus.4
Signed-off-by: dan tan
---
hw/ppc/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw
up the unit test exercising major supported locality
functionality
Tests: 'make check' and 'make check-avocado'
dan tan (3):
tpm/tpm_tis_spi: Support TPM for SPI (Serial Peripheral Interface)
tpm/tpm_tis_spi: activation for the PowerNV machines
tests/qtest/tpm: add
supported on the
PowerNV platform, thus, is big endian specific.
Signed-off-by: dan tan
---
docs/specs/tpm.rst | 15 ++
include/sysemu/tpm.h | 3 +
hw/tpm/tpm_tis_spi.c | 328 +++
hw/tpm/Kconfig | 6 +
hw/tpm/meson.build | 1 +
hw/tpm/trace-events
://trustedcomputinggroup.org/wp-content/uploads/TCG_PCClientTPMInterfaceSpecification_TIS__1-3_27_03212013.pdf
The SPI registers are specific to the PowerNV platform
architecture
Signed-off-by: dan tan
---
tests/qtest/tpm-tis-spi-pnv-test.c | 700 +
tests/qtest/meson.build| 3
Hi Stefan,
Thank you for the review comments! Please see my response below.
thank you,
---
dan tan
power simulation
phone:+1.7373.099.138
email:dan...@linux.ibm.com
On 2024-09-12 13:02, Stefan Berger wrote:
On 9/12/24 12:09 PM, dan tan wrote:
From: dan tan
SPI interface to TPM TIS
Hi Cédric,
Thank you for the review comments. Please see my response below.
thank you,
---
dan tan
power simulation
phone:+1.7373.099.138
email:dan...@linux.ibm.com
On 2024-09-12 12:20, Cédric Le Goater wrote:
Hello Dan,
On 9/12/24 18:09, dan tan wrote:
From: dan tan
SPI interface to TPM
From: dan tan
SPI interface to TPM TIS implementation via swtpm
Signed-off-by: dan tan
---
include/sysemu/tpm.h | 3 +
hw/tpm/tpm_tis_spi.c | 347 +
tests/qtest/pnv-tpm-tis-spi-test.c | 223 ++
hw/ppc/Kconfig
Shiyang Ruan wrote:
> Background:
> Since CXL device is a memory device, while CPU consumes a poison page of
> CXL device, it always triggers a MCE by interrupt (INT18), no matter
> which-First path is configured. This is the first report. Then
> currently, in FW-First path, the poison event i
Shiyang Ruan wrote:
[..]
> >> My expectation is MF_ACTION_REQUIRED is not appropriate for CXL event
> >> reported errors since action is only required for direct consumption
> >> events and those need not be reported through the device event queue.
> > Got it.
>
> I'm not very sure about 'Host wri
Shiyang Ruan wrote:
> Currently driver only traces cxl events, poison creation (for both vmem
> and pmem type) on cxl memdev is silent.
As it should be.
> OS needs to be notified then it could handle poison pages in time.
No, it was always the case that latent poison is an "action optional"
even
e cxl_poison event is
> unaffected.
>
> If userspace was doing its own DPA-to-HPA translation this could lead to
> incorrect page retirement decisions, but there is no known consumer
> (like rasdaemon) of this event today.
>
> Fixes: d54a531a430b ("cxl/mem: Trace General
Shiyang Ruan wrote:
> The transaction types are defined in General Media Event Record/DRAM Event
> per CXL rev 3.0 Section 8.2.9.2.1.1; Table 8-43 and
> Section 8.2.9.2.1.2; Table 8-44. Add them for Event Record handler use.
Combine this patch with the one that uses them so that the use case can
Shiyang Ruan wrote:
> Poison injection from debugfs is silent too. Add calling
> cxl_mem_report_poison() to make it able to do memory_failure().
Why does this needs to be signalled? It is a debug interface, the
debugger can also trigger a read after the injection, or trigger page
soft-offline.
Shiyang Ruan wrote:
> The GMER only has "Physical Address" field, no such one indicates length.
> So, when a poison event is received, we could use GET_POISON_LIST command
> to get the poison list. Now driver has cxl_mem_get_poison(), so
> reuse it and add a parameter 'bool report', report poison
Shiyang Ruan wrote:
> If poison is detected(reported from cxl memdev), OS should be notified to
> handle it. So, introduce this helper function for later use:
> 1. translate DPA to HPA;
> 2. enqueue records into memory_failure's work queue;
>
> Signed-off-by: Shiyang Ruan
This patch is too s
e cxl_poison event is
> unaffected.
>
> If userspace was doing its own DPA-to-HPA translation this could lead to
> incorrect page retirement decisions, but there is no known consumer
> (like rasdaemon) of this event today.
>
> Fixes: d54a531a430b ("cxl/mem: Trace General
Alison Schofield wrote:
> On Fri, Mar 29, 2024 at 11:22:32AM -0700, Dan Williams wrote:
> > Alison Schofield wrote:
> > [..]
> > > Upon receipt of that new poison list, call memory_failture_queue()
> > > on *any* poison in a mapped space. Is that OK? Can we cal
Alison Schofield wrote:
[..]
> Upon receipt of that new poison list, call memory_failture_queue()
> on *any* poison in a mapped space. Is that OK? Can we call
> memory_failure_queue() on any and every poison report that is in
> HPA space regardless of whether it first came to us through a GMER?
>
gt; payload->handles[i++] = gen->hdr.handle;
> > dev_dbg(mds->cxlds.dev, "Event log '%d': Clearing %u\n", log,
> > - le16_to_cpu(payload->handles[i]));
> > + le16_to_cpu(payload->handles[i-1]));
> Trivial bu
Yuquan Wang wrote:
> The dev_dbg info for Clear Event Records mailbox command would report
> the handle of the next record to clear not the current one.
>
> This was because the index 'i' had incremented before printing the
> current handle value.
>
> This fix also adjusts the index variable name
[ add Ira and Davidlohr ]
Shiyang Ruan wrote:
>
>
> 在 2024/2/10 14:34, Dan Williams 写道:
> > Shiyang Ruan wrote:
> >> The length of Physical Address in General Media Event Record/DRAM Event
> >> Record is 64-bit, so the field mask should be defined as such leng
Shiyang Ruan wrote:
> Currently driver only trace cxl events, poison injection on cxl memdev
> is silent. OS needs to be notified then it could handle poison range
> in time. Per CXL spec, the device error event could be signaled through
> FW-First and OS-First methods.
>
> So, add poison event
Shiyang Ruan wrote:
> When a poison event is received, driver uses GET_POISON_LIST command
> to get the poison list. Now driver has cxl_mem_get_poison(), so
> reuse it and add a parameter 'bool report', report poison record to MCE
> if set true.
If the memory error record has the poison event, wh
Shiyang Ruan wrote:
> If poison is detected(reported from cxl memdev), OS should be notified to
> handle it. Introduce this function:
> 1. translate DPA to HPA;
> 2. construct a MCE instance; (TODO: more details need to be filled)
> 3. log it into MCE event queue;
>
> After that, MCE mechan
Shiyang Ruan wrote:
> When a memdev is assigned to a region, its Device Physical Address will be
> mapped to Host Physical Address. Introduce this helper function to
> translate HPA from a given memdev and its DPA.
>
> Signed-off-by: Shiyang Ruan
> ---
> drivers/cxl/core/memdev.c | 12 +
Shiyang Ruan wrote:
> The length of Physical Address in General Media Event Record/DRAM Event
> Record is 64-bit, so the field mask should be defined as such length.
Can you include this user visible side-effect of this change. Looks like
this could cause usages of CXL_DPA_FLAGS_MASK to return an
On Thu, 18 Jan 2024 12:27:12 +1000, Nicholas Piggin wrote:
> On Thu Jan 18, 2024 at 8:34 AM AEST, dan tan wrote:
>>The handling of the following two registers are added -
>>DAWR1 (0x0bd, 189) - Data Address Watchpoint 1
>>DAWRX1 (0x0b5
Control Register 3
Signed-off-by: dan tan
---
target/ppc/cpu.h | 4
target/ppc/cpu_init.c | 17 +
2 files changed, 21 insertions(+)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index f8101ff..de0af02 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1933,6
The handling of the following two registers are added -
DAWR1 (0x0bd, 189) - Data Address Watchpoint 1
DAWRX1 (0x0b5, 181) - Data Address Watchpoint Extension 1
Signed-off-by: dan tan
---
target/ppc/cpu.c | 51
Jason Gunthorpe wrote:
> On Tue, Jan 09, 2024 at 06:02:03PM +0100, David Hildenbrand wrote:
> > > Given that, an alternative proposal that I think would work
> > > for you would be to add a 'placeholder' memory node definition
> > > in SRAT (so allow 0 size explicitly - might need a new SRAT
> > >
Yes, that fixes my issue. I was receiving two errors with the sanitizers:
1. UBsan complaining that the (garbage) value didn't have the required
alignment of the type
2. ASan complaining about some memory failure by read/write/accessing it
On Fri, Nov 24, 2023 at 8:02 AM Markus Armbruster wrote:
I went ahead and wrote a clang-tidy pass that attempts to find other
cases of this behavior (i.e. compile-time short-circuit behavior that
could lead to undefined references). All of these cases should also be
caught by `-Wunreachable-code`, but that uncovers a lot and I'd like a
green light before
bump
On Sat, Nov 18, 2023 at 5:13 PM Daniel Hoffman wrote:
>
> This conversion is pretty straight-forward. Standardized some formatting
> so the +0 and +4 offset cases can recycle the same message.
>
> Signed-off-by: Daniel Hoffman
> ---
> hw/timer/hpet.c | 55 +---
to resolve this patch. If any of you
need anything else, please let me know.
On Tue, Nov 21, 2023 at 12:28 PM Dan Hoffman wrote:
>
> I'm writing a patch to clang's constant folding to address this case
> (doesn't seem too difficult). I'll either follow up with a link
t;
> On Mon, Nov 20, 2023 at 11:20:52AM +0100, Philippe Mathieu-Daudé wrote:
> > (Cc'ing Eric)
> >
> > On 20/11/23 10:28, Michael S. Tsirkin wrote:
> > > On Sun, Nov 19, 2023 at 07:34:58PM -0600, Dan Hoffman wrote:
> > > > As far as I can tell, yes. An
As far as I can tell, yes. Any optimization level above O0 does not have
this issue (on this version of Clang, at least)
On Sun, Nov 19, 2023 at 4:54 PM Philippe Mathieu-Daudé
wrote:
> Hi,
>
> On 19/11/23 21:31, Daniel Hoffman wrote:
> > `kvm_enabled()` is compiled down to `0` and short-circuit
Submitted a v3 with the minimum reproducible build configuration
On Sun, Nov 19, 2023 at 2:25 PM Michael S. Tsirkin wrote:
>
> On Sun, Nov 19, 2023 at 02:19:25PM -0600, Dan Hoffman wrote:
> > Clang 16.0.6
> >
> > I can re-submit with the compiler and version if that hel
Clang 16.0.6
I can re-submit with the compiler and version if that helps.
On Sun, Nov 19, 2023 at 2:02 PM Michael S. Tsirkin wrote:
>
> On Sun, Nov 19, 2023 at 11:03:54AM -0600, Dan Hoffman wrote:
> > On Sun, Nov 19, 2023 at 1:23 AM Michael S. Tsirkin wrote:
> > >
> >
On Sun, Nov 19, 2023 at 1:23 AM Michael S. Tsirkin wrote:
>
> On Sat, Nov 18, 2023 at 10:25:31AM -0800, Daniel Hoffman wrote:
> > `kvm_enabled()` is compiled down to `0` and short-circuit logic is
> > used to remmove references to undefined symbols at the compile stage.
> > Some build configuratio
Jonathan Cameron wrote:
[..]
> > > >
> > > > what does "a WORD" mean is unclear - do you match what hardware does
> > > > when you use aml_buffer? pls mention this in commit log, and
> > > > show actual hardware dump for comparison.
> > > The CXL spec says WORD without much qualification. It's a
Jonathan Cameron wrote:
> On Mon, 20 Mar 2023 23:08:31 -0700
> Dan Williams wrote:
>
> > While it was a reasonable idea to specify no window restricitions at the
> > outset of the CXL emulation support, it turns out that in practice a
> > platform will never follow the
Dan Williams wrote:
> While it was a reasonable idea to specify no window restricitions at the
> outset of the CXL emulation support, it turns out that in practice a
> platform will never follow the QEMU example of specifying simultaneous
> support for HDM-H and HDM-D[B] in a s
memory, move QEMU exclusively to
declaring host-only windows.
Signed-off-by: Dan Williams
---
hw/acpi/cxl.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/acpi/cxl.c b/hw/acpi/cxl.c
index 2bf8c0799359..defb289e2fef 100644
--- a/hw/acpi/cxl.c
+++ b/hw/acpi/cxl.c
Is there interest in this?
On Fri, Nov 11, 2022 at 10:33 PM Daniel Hoffman wrote:
>
> The previous test cases for virtio-serial only tested initialization of
> the device. I've included four new test cases: rx for virtconsole, tx
> for virtconsole, rx for virtserialport, tx for virtserialport. I
Gregory Price wrote:
> On Fri, Jan 20, 2023 at 09:38:13AM -0800, Dan Williams wrote:
> > As it stands currently that dax device and the cxl device are not
> > related since a default dax-device is loaded just based on the presence
> > of an EFI_MEMORY_SP address range in the
Gregory Price wrote:
> On Thu, Jan 19, 2023 at 03:04:49PM +, Jonathan Cameron wrote:
> > Gregory, would you mind checking if
> > cxl_nvb is NULL here...
> > https://elixir.bootlin.com/linux/v6.2-rc4/source/drivers/cxl/pmem.c#L67
> > (printk before it is used should work).
> >
> > Might also be
Jonathan Cameron wrote:
> On Thu, 19 Jan 2023 15:04:49 +
> Jonathan Cameron wrote:
>
> > On Thu, 19 Jan 2023 12:42:44 +
> > Jonathan Cameron via wrote:
> >
> > > On Wed, 18 Jan 2023 14:31:53 -0500
> > > Gregory Price wrote:
> > >
> > > > I apparently forgot an intro lol
> > > >
> >
Jonathan Cameron wrote:
> On Fri, 12 Aug 2022 16:44:03 +0100
> Jonathan Cameron wrote:
>
> > On Thu, 11 Aug 2022 18:08:57 +0100
> > Jonathan Cameron via wrote:
> >
> > > On Tue, 9 Aug 2022 17:08:25 +0100
> > > Jonathan Cameron wrote:
> > >
> > > > On Tue, 9 Aug 2022 21:07:06 +0800
> > > > B
On Tue, Aug 9, 2022 at 10:51 PM Cédric Le Goater wrote:
>
> Hello,
>
> On 8/10/22 04:37, Joel Stanley wrote:
> > Hello Shivi,
> >
> > I've added others to cc who may have some input.
> >
> > On Tue, 9 Aug 2022 at 21:38, Shivi Fotedar wrote:
> >>
> >> Hello, we are looking for support for few feat
Jonathan Cameron wrote:
> On Thu, 11 Aug 2022 18:08:57 +0100
> Jonathan Cameron via wrote:
>
> > On Tue, 9 Aug 2022 17:08:25 +0100
> > Jonathan Cameron wrote:
> >
> > > On Tue, 9 Aug 2022 21:07:06 +0800
> > > Bobo WL wrote:
> > >
> > > > Hi Jonathan
> > > >
> > > > Thanks for your reply!
>
Dan Williams wrote:
> Bobo WL wrote:
> > Hi Dan,
> >
> > Thanks for your reply!
> >
> > On Mon, Aug 8, 2022 at 11:58 PM Dan Williams
> > wrote:
> > >
> > > What is the output of:
> > >
> > > cxl list -MDTu -d dec
Bobo WL wrote:
> Hi Dan,
>
> Thanks for your reply!
>
> On Mon, Aug 8, 2022 at 11:58 PM Dan Williams wrote:
> >
> > What is the output of:
> >
> > cxl list -MDTu -d decoder0.0
> >
> > ...? It might be the case that mem1 cannot be mapped
Bobo WL wrote:
> Hi list
>
> I want to test cxl functions in arm64, and found some problems I can't
> figure out.
>
> My test environment:
>
> 1. build latest bios from https://github.com/tianocore/edk2.git master
> branch(cc2db6ebfb6d9d85ba4c7b35fba1fa37fffc0bc2)
> 2. build latest qemu-system-a
On Thu, Aug 4, 2022 at 4:21 PM Peter Delevoryas wrote:
>
> On Thu, Aug 04, 2022 at 11:07:10AM -0700, Dan Zhang wrote:
> > On Wed, Aug 3, 2022 at 10:30 AM Peter Delevoryas wrote:
> > >
> > > On Wed, Aug 03, 2022 at 10:52:23AM +0200, Cédric Le Goater wrote:
> >
On Wed, Aug 3, 2022 at 10:30 AM Peter Delevoryas wrote:
>
> On Wed, Aug 03, 2022 at 10:52:23AM +0200, Cédric Le Goater wrote:
> > On 8/3/22 04:32, Iris Chen wrote:
> > > From: Iris Chen
> >
> > A commit log telling us about this new device would be good to have.
> >
> >
> > > Signed-off-by: Iris
1 - 100 of 402 matches
Mail list logo
