[PATCH v4 0/2] RISC-V: Add preliminary textra trigger CSR functions

condition between textra.MHVALUE and mcontext CSR is also implemented. Changes from v3: - Simplify the comparison between mcontext and textra.MHVALUE Changes from v2: - Remove redundant log Changes from v1: - Log that mhselect only supports 0 or 4 for now - Simplify writing of tdata3 Alvin Chang (2

[PATCH v4 1/2] target/riscv: Preliminary textra trigger CSR writting support

. For textra.MHSELECT field, the only legal values are 0 (ignore) and 4 (mcontext). Writing 1~3 into textra.MHSELECT will be changed to 0, and writing 5~7 into textra.MHSELECT will be changed to 4. This behavior is aligned to RISC-V SPIKE simulator. Signed-off-by: Alvin Chang Reviewed-by: Alistair

[PATCH v4 2/2] target/riscv: Add textra matching condition for the triggers

textra.MHVALUE with mcontext CSR. The remaining fields, such as textra.SBYTEMASK, textra.SVALUE, and textra.SSELECT, are hardwired to zero for now. Thus, we skip checking them here. Signed-off-by: Alvin Chang --- target/riscv/debug.c | 45 +++- target/riscv

[PATCH] RISC-V: Remove riscv_cpu_claim_interrupts()

ask. It seems the function of riscv_cpu_claim_interrupts() is no longer used. Therefore, we remove it in this commit. Signed-off-by: Alvin Chang --- hw/intc/riscv_aclint.c| 20 hw/intc/riscv_aplic.c | 11 --- hw/intc/riscv_imsic.c | 8 hw/intc/sifive_plic.c

[PATCH v3 1/2] target/riscv: Preliminary textra trigger CSR writting support

. For textra.MHSELECT field, the only legal values are 0 (ignore) and 4 (mcontext). Writing 1~3 into textra.MHSELECT will be changed to 0, and writing 5~7 into textra.MHSELECT will be changed to 4. This behavior is aligned to RISC-V SPIKE simulator. Signed-off-by: Alvin Chang Reviewed-by: Alistair

[PATCH v3 0/2] RISC-V: Add preliminary textra trigger CSR functions

condition between textra.MHVALUE and mcontext CSR is also implemented. Changes from v2: - Remove redundant log Changes from v1: - Log that mhselect only supports 0 or 4 for now - Simplify writing of tdata3 Alvin Chang (2): target/riscv: Preliminary textra trigger CSR writting support target

[PATCH v3 2/2] target/riscv: Add textra matching condition for the triggers

textra.MHVALUE with mcontext CSR. The remaining fields, such as textra.SBYTEMASK, textra.SVALUE, and textra.SSELECT, are hardwired to zero for now. Thus, we skip checking them here. Signed-off-by: Alvin Chang Reviewed-by: Alistair Francis --- target/riscv/debug.c | 63

[PATCH v2 0/2] RISC-V: Add preliminary textra trigger CSR functions

condition between textra.MHVALUE and mcontext CSR is also implemented. Changes from v1: - Log that mhselect only supports 0 or 4 for now - Simplify writing of tdata3 Alvin Chang (2): target/riscv: Preliminary textra trigger CSR writting support target/riscv: Add textra matching condition for the

[PATCH v2 1/2] target/riscv: Preliminary textra trigger CSR writting support

. For textra.MHSELECT field, the only legal values are 0 (ignore) and 4 (mcontext). Writing 1~3 into textra.MHSELECT will be changed to 0, and writing 5~7 into textra.MHSELECT will be changed to 4. This behavior is aligned to RISC-V SPIKE simulator. Signed-off-by: Alvin Chang --- target/riscv

[PATCH v2 2/2] target/riscv: Add textra matching condition for the triggers

textra.MHVALUE with mcontext CSR. The remaining fields, such as textra.SBYTEMASK, textra.SVALUE, and textra.SSELECT, are hardwired to zero for now. Thus, we skip checking them here. Signed-off-by: Alvin Chang Reviewed-by: Alistair Francis --- target/riscv/debug.c | 63

[PATCH 2/2] target/riscv: Add textra matching condition for the triggers

textra.MHVALUE with mcontext CSR. The remaining fields, such as textra.SBYTEMASK, textra.SVALUE, and textra.SSELECT, are hardwired to zero for now. Thus, we skip checking them here. Signed-off-by: Alvin Chang --- target/riscv/debug.c | 63 +++- target/riscv

[PATCH 1/2] target/riscv: Preliminary textra trigger CSR writting support

. For textra.MHSELECT field, the only legal values are 0 (ignore) and 4 (mcontext). Writing 1~3 into textra.MHSELECT will be changed to 0, and writing 5~7 into textra.MHSELECT will be changed to 4. This behavior is aligned to RISC-V SPIKE simulator. Signed-off-by: Alvin Chang --- target/riscv

[PATCH 0/2] RISC-V: Add preliminary textra trigger CSR functions

condition between textra.MHVALUE and mcontext CSR is also implemented. Alvin Chang (2): target/riscv: Preliminary textra trigger CSR writting support target/riscv: Add textra matching condition for the triggers target/riscv/cpu_bits.h | 10 +++ target/riscv/debug.c| 144

[PATCH v6 2/3] target/riscv: Apply modularized matching conditions for watchpoint

nly load/store bits and loaded/stored address should be further checked in riscv_cpu_debug_check_watchpoint(). Signed-off-by: Alvin Chang Acked-by: Alistair Francis --- target/riscv/debug.c | 26 ++ 1 file changed, 6 insertions(+), 20 deletions(-) diff --git a/target/riscv

[PATCH v6 3/3] target/riscv: Apply modularized matching conditions for icount trigger

We have implemented trigger_common_match(), which checks if the enabled privilege levels of the trigger match CPU's current privilege level. We can invoke trigger_common_match() to check the privilege levels of the type 3 triggers. Signed-off-by: Alvin Chang Acked-by: Alistair Fr

[PATCH v6 0/3] RISC-V: Modularize common match conditions for trigger

v2: - Explicitly mention the targeting version of RISC-V Debug Spec. Changes from v1: - Fix typo - Add commit description for changing behavior of looping the triggers when we check type 2 triggers. Alvin Chang (3): target/riscv: Add functions for common matching conditions of trigger

[PATCH v6 1/3] target/riscv: Add functions for common matching conditions of trigger

ases/tag/1.0.0-rc1-asciidoc Signed-off-by: Alvin Chang Reviewed-by: Alistair Francis --- target/riscv/debug.c | 101 +-- 1 file changed, 78 insertions(+), 23 deletions(-) diff --git a/target/riscv/debug.c b/target/riscv/debug.c index b110370e..11125f33 1006

[PATCH v6 1/3] target/riscv: Add functions for common matching conditions of trigger

From: Alvin Chang via According to RISC-V Debug specification version 0.13 [1] (also applied to version 1.0 [2] but it has not been ratified yet), there are several common matching conditions before firing a trigger, including the enabled privilege levels of the trigger. This commit adds

[PATCH v6 3/3] target/riscv: Apply modularized matching conditions for icount trigger

From: Alvin Chang via We have implemented trigger_common_match(), which checks if the enabled privilege levels of the trigger match CPU's current privilege level. We can invoke trigger_common_match() to check the privilege levels of the type 3 triggers. Signed-off-by: Alvin Chang Ack

[PATCH v6 2/3] target/riscv: Apply modularized matching conditions for watchpoint

From: Alvin Chang via We have implemented trigger_common_match(), which checks if the enabled privilege levels of the trigger match CPU's current privilege level. Remove the related code in riscv_cpu_debug_check_watchpoint() and invoke trigger_common_match() to check the privilege levels o

[PATCH v6 0/3] RISC-V: Modularize common match conditions for trigger

v2: - Explicitly mention the targeting version of RISC-V Debug Spec. Changes from v1: - Fix typo - Add commit description for changing behavior of looping the triggers when we check type 2 triggers. Alvin Chang (3): target/riscv: Add functions for common matching conditions of trigger

[PATCH v5 3/4] target/riscv: Apply modularized matching conditions for watchpoint

nly load/store bits and loaded/stored address should be further checked in riscv_cpu_debug_check_watchpoint(). Signed-off-by: Alvin Chang Acked-by: Alistair Francis --- target/riscv/debug.c | 26 ++ 1 file changed, 6 insertions(+), 20 deletions(-) diff --git a/target/riscv

[PATCH v5 4/4] target/riscv: Apply modularized matching conditions for icount trigger

We have implemented trigger_common_match(), which checks if the enabled privilege levels of the trigger match CPU's current privilege level. We can invoke trigger_common_match() to check the privilege levels of the type 3 triggers. Signed-off-by: Alvin Chang Acked-by: Alistair Fr

[PATCH v5 1/4] target/riscv: Add functions for common matching conditions of trigger

https://github.com/riscv/riscv-debug-spec/releases/tag/1.0.0-rc1-asciidoc Signed-off-by: Alvin Chang Reviewed-by: Alistair Francis --- target/riscv/debug.c | 70 1 file changed, 70 insertions(+) diff --git a/target/riscv/debug.c b/target/riscv/debug.c

[PATCH v5 2/4] target/riscv: Apply modularized matching conditions for breakpoint

Only the execution bit and the executed PC should be futher checked in riscv_cpu_debug_check_breakpoint(). Signed-off-by: Alvin Chang Reviewed-by: Alistair Francis --- target/riscv/debug.c | 31 --- 1 file changed, 8 insertions(+), 23 deletions(-) diff --git a/targ

[PATCH v5 0/4] RISC-V: Modularize common match conditions for trigger

Spec. Changes from v1: - Fix typo - Add commit description for changing behavior of looping the triggers when we check type 2 triggers. Alvin Chang (4): target/riscv: Add functions for common matching conditions of trigger target/riscv: Apply modularized matching conditions for breakpoint

[PATCH v4 1/4] target/riscv: Add functions for common matching conditions of trigger

https://github.com/riscv/riscv-debug-spec/releases/tag/1.0.0-rc1-asciidoc Signed-off-by: Alvin Chang --- target/riscv/debug.c | 70 1 file changed, 70 insertions(+) diff --git a/target/riscv/debug.c b/target/riscv/debug.c index e30d99cc2f..3891236b82 100644

[PATCH v4 3/4] target/riscv: Apply modularized matching conditions for watchpoint

nly load/store bits and loaded/stored address should be further checked in riscv_cpu_debug_check_watchpoint(). Signed-off-by: Alvin Chang --- target/riscv/debug.c | 26 ++ 1 file changed, 6 insertions(+), 20 deletions(-) diff --git a/target/riscv/debug.c b/target/riscv

[PATCH v4 0/4] RISC-V: Modularize common match conditions for trigger

description for changing behavior of looping the triggers when we check type 2 triggers. Alvin Chang (4): target/riscv: Add functions for common matching conditions of trigger target/riscv: Apply modularized matching conditions for breakpoint target/riscv: Apply modularized matching conditions

[PATCH v4 4/4] target/riscv: Apply modularized matching conditions for icount trigger

We have implemented trigger_common_match(), which checks if the enabled privilege levels of the trigger match CPU's current privilege level. We can invoke trigger_common_match() to check the privilege levels of the type 3 triggers. Signed-off-by: Alvin Chang --- target/riscv/debug.c | 2

[PATCH v4 2/4] target/riscv: Apply modularized matching conditions for breakpoint

Only the execution bit and the executed PC should be futher checked in riscv_cpu_debug_check_breakpoint(). Signed-off-by: Alvin Chang Reviewed-by: Alistair Francis --- target/riscv/debug.c | 26 ++ 1 file changed, 6 insertions(+), 20 deletions(-) diff --git a/target/riscv/d

[PATCH v3 0/4] RISC-V: Modularize common match conditions for trigger

targeting version of RISC-V Debug Spec. Changes from v1: - Fix typo - Add commit description for changing behavior of looping the triggers when we check type 2 triggers. Alvin Chang (4): target/riscv: Add functions for common matching conditions of trigger target/riscv: Apply modularized matching

[PATCH v3 2/4] target/riscv: Apply modularized matching conditions for breakpoint

Only the execution bit and the executed PC should be futher checked in riscv_cpu_debug_check_breakpoint(). Signed-off-by: Alvin Chang --- target/riscv/debug.c | 26 ++ 1 file changed, 6 insertions(+), 20 deletions(-) diff --git a/target/riscv/debug.c b/target/riscv/debug

[PATCH v3 4/4] target/riscv: Apply modularized matching conditions for icount trigger

We have implemented trigger_common_match(), which checks if the enabled privilege levels of the trigger match CPU's current privilege level. We can invoke trigger_common_match() to check the privilege levels of the type 3 triggers. Signed-off-by: Alvin Chang --- target/riscv/debug.c | 2

[PATCH v3 3/4] target/riscv: Apply modularized matching conditions for watchpoint

nly load/store bits and loaded/stored address should be further checked in riscv_cpu_debug_check_watchpoint(). Signed-off-by: Alvin Chang --- target/riscv/debug.c | 26 ++ 1 file changed, 6 insertions(+), 20 deletions(-) diff --git a/target/riscv/debug.c b/target/riscv

[PATCH v3 1/4] target/riscv: Add functions for common matching conditions of trigger

now, we just implement trigger_priv_match() to check if the enabled privilege levels of the trigger match CPU's current privilege level. [1]: https://github.com/riscv/riscv-debug-spec/releases/tag/1.0.0-rc1-asciidoc Signed-off-by: Alvin Chang --- target/riscv/debug.c

[PATCH v2 1/4] target/riscv: Add functions for common matching conditions of trigger

implement trigger_priv_match() to check if the enabled privilege levels of the trigger match CPU's current privilege level. Signed-off-by: Alvin Chang --- target/riscv/debug.c | 70 1 file changed, 70 insertions(+) diff --git a/target/riscv/debu

[PATCH v2 0/4] RISC-V: Modularize common match conditions for trigger

trigger_priv_match(). Additional match conditions, such as CSR tcontrol and textra, can be further implemented into trigger_common_match() in the future. Changes from v1: - Fix typo - Add commit description for changing behavior of looping the triggers when we check type 2 triggers. Alvin Chang (4

[PATCH v2 4/4] target/riscv: Apply modularized matching conditions for icount trigger

We have implemented trigger_common_match(), which checks if the enabled privilege levels of the trigger match CPU's current privilege level. We can invoke trigger_common_match() to check the privilege levels of the type 3 triggers. Signed-off-by: Alvin Chang --- target/riscv/debug.c | 2

[PATCH v2 3/4] target/riscv: Apply modularized matching conditions for watchpoint

nly load/store bits and loaded/stored address should be further checked in riscv_cpu_debug_check_watchpoint(). Signed-off-by: Alvin Chang --- target/riscv/debug.c | 26 ++ 1 file changed, 6 insertions(+), 20 deletions(-) diff --git a/target/riscv/debug.c b/target/riscv

[PATCH v2 2/4] target/riscv: Apply modularized matching conditions for breakpoint

Only the execution bit and the executed PC should be futher checked in riscv_cpu_debug_check_breakpoint(). Signed-off-by: Alvin Chang --- target/riscv/debug.c | 26 ++ 1 file changed, 6 insertions(+), 20 deletions(-) diff --git a/target/riscv/debug.c b/target/riscv/debug

[PATCH 1/4] target/riscv: Add functions for common matching conditions of trigger

implement trigger_priv_match() to check if the enabled privilege levels of the trigger match CPU's current privilege level. Signed-off-by: Alvin Chang --- target/riscv/debug.c | 70 1 file changed, 70 insertions(+) diff --git a/target/riscv/debu

[PATCH 0/4] RISC-V: Modularize common match conditions for trigger

trigger_priv_match(). Additional match conditions, such as CSR tcontrol and textra, can be further implemented into trigger_common_match() in the future. Alvin Chang (4): target/riscv: Add functions for common matching conditions of trigger target/riscv: Apply modularized matching conditions for

[PATCH 3/4] target/riscv: Apply modularized matching conditions for watchpoint

ype 6 triggers for the watchpoints. Only load/store bits and loaded/stored address should be further checked in riscv_cpu_debug_check_watchpoint(). Signed-off-by: Alvin Chang --- target/riscv/debug.c | 26 ++ 1 file changed, 6 insertions(+), 20 deletions(-) diff --git a/target/

[PATCH 2/4] target/riscv: Apply modularized matching conditions for breakpoint

ype 6 triggers for the breakpoints. Only the execution bit and the executed PC should be futher checked in riscv_cpu_debug_check_breakpoint(). Signed-off-by: Alvin Chang --- target/riscv/debug.c | 26 ++ 1 file changed, 6 insertions(+), 20 deletions(-) diff --git a/target/

[PATCH 4/4] target/riscv: Apply modularized matching conditions for icount trigger

We have implemented trigger_common_match(), which checks if the enabled privilege levels of the trigger match CPU's current privilege level. We can invoke trigger_common_match() to check the privilege levels of the type 3 triggers. Signed-off-by: Alvin Chang --- target/riscv/debug.c | 2

[PATCH 4/4] target/riscv: Set the value of CSR tcontrol when mret is executed

tech-debug/topic/102702615#1461 The debug specification does not mention the operation to tcontrol.MPTE when "mret" is executed. Therefore, we just keep its current value. Signed-off-by: Alvin Chang --- target/riscv/op_helper.c | 6 ++ 1 file changed, 6 insertions(+) diff

[PATCH 1/4] target/riscv: Add CSR tcontrol of debug trigger module

The RISC-V debug specification defines an optional CSR "tcontrol" within the trigger module. This commit adds its read/write operations and related bit-field definitions. Signed-off-by: Alvin Chang --- target/riscv/cpu.h | 1 + target/riscv/cpu_bits.h | 3 +++ target/r

[PATCH 3/4] target/riscv: Set the value of CSR tcontrol when trapping to M-mode

-by: Alvin Chang --- target/riscv/cpu_helper.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index d462d95ee1..037ae21062 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1806,6 +1806,12 @@ v

[PATCH 0/4] RISC-V: Implement CSR tcontrol in debug spec

The RISC-V Debug specification defines CSR "tcontrol" in the trigger module: https://github.com/riscv/riscv-debug-spec This series implements it and the related operations. Alvin Chang (4): target/riscv: Add CSR tcontrol of debug trigger module target/riscv: Reset CSR tcontro

[PATCH 2/4] target/riscv: Reset CSR tcontrol when the trigger module resets

When the trigger module resets, reset the value of CSR tcontrol as zero. Signed-off-by: Alvin Chang --- target/riscv/debug.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/debug.c b/target/riscv/debug.c index e30d99cc2f..e3832a643e 100644 --- a/target/riscv/debug.c +++ b

[PATCH v2] target/riscv: Implement optional CSR mcontext of debug Sdtrig extension

The debug Sdtrig extension defines an CSR "mcontext". This commit implements its predicate and read/write operations into CSR table. Its value is reset as 0 when the trigger module is reset. Signed-off-by: Alvin Chang --- Changes from v1: Remove dedicated cfg, always implement mcontext

[PATCH] target/riscv: Implement optional CSR mcontext of debug Sdtrig extension

are also implemented into CSR table. Its value is reset as 0 when the trigger module is reset. Signed-off-by: Alvin Chang --- target/riscv/cpu.c | 4 target/riscv/cpu.h | 1 + target/riscv/cpu_bits.h | 7 +++ target/riscv/cpu_cfg.h | 1 +

Re: [PATCH v5] target/riscv: update checks on writing pmpcfg for Smepmp to version 1.0

scv: update checks on writing pmpcfg for > Smepmp to version 1.0 > > On Tue, Nov 14, 2023 at 12:24 PM Alvin Chang via > wrote: > > > > Current checks on writing pmpcfg for Smepmp follows Smepmp version > > 0.9.1. However, Smepmp specification has already been ra

RE: [PATCH v5] target/riscv: update checks on writing pmpcfg for Smepmp to version 1.0

of pmpcfg into the index of the Smepmp truth > table, and checks the rules by aforementioned specification changes. > > Signed-off-by: Alvin Chang > --- > Changes from v4: Rebase on master. > > Changes from v3: Modify "epmp_operation" to "smepmp_operation&q

[PATCH v5] target/riscv: update checks on writing pmpcfg for Smepmp to version 1.0

-Region is not possible and such pmpcfg writes are ignored, leaving pmpcfg unchanged. The commit transfers the value of pmpcfg into the index of the Smepmp truth table, and checks the rules by aforementioned specification changes. Signed-off-by: Alvin Chang --- Changes from v4: Rebase on master

[PATCH v4] target/riscv: update checks on writing pmpcfg for Smepmp to version 1.0

-Region is not possible and such pmpcfg writes are ignored, leaving pmpcfg unchanged. The commit transfers the value of pmpcfg into the index of the Smepmp truth table, and checks the rules by aforementioned specification changes. Signed-off-by: Alvin Chang --- Changes from v3: Modify

[PATCH v3] target/riscv: update checks on writing pmpcfg for Smepmp to version 1.0

-Region is not possible and such pmpcfg writes are ignored, leaving pmpcfg unchanged. The commit transfers the value of pmpcfg into the index of the Smepmp truth table, and checks the rules by aforementioned specification changes. Signed-off-by: Alvin Chang --- Changes from v2: Adopt switch case

[PATCH v2] target/riscv: update checks on writing pmpcfg for Smepmp version 1.0

-Region is not possible and such pmpcfg writes are ignored, leaving pmpcfg unchanged. The commit transfers the value of pmpcfg into the index of the Smepmp truth table, and checks the rules by aforementioned specification changes. Signed-off-by: Alvin Chang --- Changes from v1: Convert ePMP over

[PATCH v2] target/riscv: update checks on writing pmpcfg for Smepmp version 1.0

-Region is not possible and such pmpcfg writes are ignored, leaving pmpcfg unchanged. The commit transfers the value of pmpcfg into the index of the Smepmp truth table, and checks the rules by aforementioned specification changes. Signed-off-by: Alvin Chang --- Changes from v1: Convert ePMP over

[PATCH v2] target/riscv: update checks on writing pmpcfg for Smepmp version 1.0

-Region is not possible and such pmpcfg writes are ignored, leaving pmpcfg unchanged. The commit transfers the value of pmpcfg into the index of the Smepmp truth table, and checks the rules by aforementioned specification changes. Signed-off-by: Alvin Chang --- Changes from v1: Convert ePMP over

[PATCH] disas/riscv: Fix the typo of inverted order of pmpaddr13 and pmpaddr14

Fix the inverted order of pmpaddr13 and pmpaddr14 in csr_name(). Signed-off-by: Alvin Chang --- disas/riscv.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/disas/riscv.c b/disas/riscv.c index 3873a69157..8e89e1d115 100644 --- a/disas/riscv.c +++ b/disas/riscv.c

[PATCH] target/riscv: update checks on writing pmpcfg for ePMP to version 1.0

not possible and such pmpcfg writes are ignored, leaving pmpcfg unchanged. The commit transfers the value of pmpcfg into the index of the ePMP truth table, and checks the rules by aforementioned specification changes. Signed-off-by: Alvin Chang --- target/riscv/pmp.c | 51