On 6/24/25 04:22, Kane Chen wrote:
From: Kane-Chen-AS
This patch connects the aspeed.otpmem device to the ASPEED Secure Boot
Controller (SBC) model. It implements OTP memory access via the SBC's
command interface and enables emulation of secure fuse programming flows.
The following OTP command
On 23/06/2025 22.12, jro...@linux.ibm.com wrote:
From: Jared Rossi
Replace a recently introduced legacy API call with the preferred API call.
fixes: 0927875 (hw/s390x: Build an IPLB for each boot device)
Signed-off-by: Jared Rossi
---
hw/s390x/ipl.c | 10 +-
1 file changed, 9 inser
Alex Bennée writes:
> Stefan Hajnoczi writes:
>
>> Any final comments before I merge this?
>
> It's well reviewed lets get it merged.
Stefan, would you like a PR from me?
On 21/12/23 22:19, Salvatore Bonaccorso wrote:
Hi Philippe,
On Wed, Nov 09, 2022 at 08:43:19AM +0100, Philippe Mathieu-Daudé wrote:
On 8/11/22 21:57, Stefan Hajnoczi wrote:
I've dropped the SDHCI CVE fix due to the CI failure.
The rest of the commits are still in the staging tree and I plan t
Hi Eric,
>-Original Message-
>From: Eric Auger
>Subject: Re: [PATCH v2 10/19] intel_iommu: Handle PASID entry removing and
>updating
>
>Hi Zhenzhong,
>
>On 6/20/25 9:18 AM, Zhenzhong Duan wrote:
>I would suggest: Handle PASID entry removal and update instead of verbing.
>> This adds an ne
>-Original Message-
>From: Eric Auger
>Subject: Re: [PATCH v2 09/19] intel_iommu: Introduce two helpers
>vtd_as_from/to_iommu_pasid_locked
>
>Hi Zhenzhong,
>
>On 6/20/25 9:18 AM, Zhenzhong Duan wrote:
>> PCI device supports two request types, Requests-without-PASID and
>> Requests-with-P
From: Kane-Chen-AS
This patch connects the aspeed.otpmem device to the ASPEED Secure Boot
Controller (SBC) model. It implements OTP memory access via the SBC's
command interface and enables emulation of secure fuse programming flows.
The following OTP commands are supported:
- READ: reads a 32
From: Kane-Chen-AS
This patch series introduces a QEMU model for the ASPEED OTP (One-Time
Programmable) memory, along with its integration into the Secure Boot
Controller (SBC) and supported SoC (AST2600).
The OTP model emulates a simple fuse array used for secure boot or
device configuration, i
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
tcg/tcg-op-gvec.c | 61 ---
1 file changed, 36 insertions(+), 25 deletions(-)
diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
index f5edadb992..0e6b42476e 100644
--- a/tcg/tcg-op-gvec.
The following changes since commit 43ba160cb4bbb193560eb0d2d7decc4b5fc599fe:
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
(2025-06-21 10:00:46 -0400)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20250623
From: Daniel P. Berrangé
There are a number of resource leaks in gen-vdso. In theory they are
harmless because this is a short lived process, but when building QEMU
with --extra-cflags="-fsanitize=address" problems ensure. The gen-vdso
program is run as part of the build, and that aborts due to t
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
include/tcg/tcg-op-gvec-common.h | 33 +-
tcg/tcg-op-gvec.c| 102 +++
2 files changed, 95 insertions(+), 40 deletions(-)
diff --git a/include/tcg/tcg-op-gvec-common.h b/include/t
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
include/tcg/tcg-op-gvec-common.h | 4
tcg/tcg-op-gvec.c| 21 +++--
2 files changed, 19 insertions(+), 6 deletions(-)
diff --git a/include/tcg/tcg-op-gvec-common.h b/include/tcg/tcg-op-gvec-comm
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
include/tcg/tcg-op-gvec-common.h | 3 +++
tcg/tcg-op-gvec.c| 10 --
2 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/include/tcg/tcg-op-gvec-common.h b/include/tcg/tcg-op-gvec-common.h
index c
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
tcg/tcg-op-gvec.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
index d32a4f146d..1aad7b0864 100644
--- a/tcg/tcg-op-gvec.c
+++ b/tcg/tcg-op-gvec.c
@@ -483
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
tcg/tcg-op-gvec.c | 36 ++--
1 file changed, 18 insertions(+), 18 deletions(-)
diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
index b100dd66ab..f5edadb992 100644
--- a/tcg/tcg-op-gvec.c
+++ b/tcg
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
tcg/tcg-op-gvec.c | 33 +
1 file changed, 17 insertions(+), 16 deletions(-)
diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
index 1aad7b0864..b100dd66ab 100644
--- a/tcg/tcg-op-gvec.c
+++ b/tcg/tc
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
linux-user/elfload.c | 75 ++--
1 file changed, 72 insertions(+), 3 deletions(-)
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index 82ebf6a212..2add1665c7 100644
--- a/linux-user/
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
include/tcg/tcg-op-gvec-common.h | 14 --
tcg/tcg-op-gvec.c| 85
2 files changed, 64 insertions(+), 35 deletions(-)
diff --git a/include/tcg/tcg-op-gvec-common.h b/include/tcg/tc
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
include/tcg/tcg-op-gvec-common.h | 9 +
tcg/tcg-op-gvec.c| 32 ++--
2 files changed, 35 insertions(+), 6 deletions(-)
diff --git a/include/tcg/tcg-op-gvec-common.h b/include/tcg/
On Mon, Jun 23, 2025 at 4:10 PM Laurent Vivier wrote:
>
> On 23/06/2025 10:03, Jason Wang wrote:
> > On Wed, Jun 18, 2025 at 4:39 PM Laurent Vivier wrote:
> >>
> >> This series introduces support for passt as a new network backend for
> >> QEMU.
> >>
> >> passt is a modern, unprivileged, user-mod
On 6/23/25 13:12, jro...@linux.ibm.com wrote:
From: Jared Rossi
Replace a recently introduced legacy API call with the preferred API call.
fixes: 0927875 (hw/s390x: Build an IPLB for each boot device)
Signed-off-by: Jared Rossi
---
hw/s390x/ipl.c | 10 +-
1 file changed, 9 insertio
Stefan Hajnoczi writes:
> On Mon, Jun 16, 2025 at 5:27 AM Markus Armbruster wrote:
>>
>> More than a year ago, Daniel posted patches to put an AI policy in
>> writing. Reception was mostly positive. A v2 to address feedback
>> followed with some delay. But no pull request.
>>
>> I asked Danie
On 6/13/25 4:46 AM, Sairaj Kodilkar wrote:
On 5/31/2025 3:00 AM, Alejandro Jimenez wrote:
Hey Sairaj,
On 5/29/25 2:16 AM, Sairaj Kodilkar wrote:
On 5/2/2025 7:46 AM, Alejandro Jimenez wrote:
On reset, restore the default address translation mode for all the
address spaces managed by th
On Thu, Jun 19, 2025 at 08:08:28PM -0400, Stefan Hajnoczi wrote:
> The io_uring_prep_readv2/writev2() man pages recommend using the
> non-vectored read/write operations when possible for performance
> reasons.
>
> I didn't measure a significant difference but it doesn't hurt to have
> this optimiz
CC: libvirt devel list
Hi Kevin/Peter,
Thank you so much for addressing this issue. I tried out few more things and
here is my analysis:
Even when I removed the readonly option from guest xml I was still seeing the
issue in migration,In the qemu-commandline I could still see auto-read-only
opti
From: Juraj Marcin
If a virtual machine is paused for an extended period time, for example,
due to an incoming migration, there are also no changes on the screen.
VNC in such case increases the display update interval by
VNC_REFRESH_INTERVAL_INC (50 ms). The update interval can then grow up
to VN
On 6/23/25 18:09, Mark Cave-Ayland wrote:
On 22/06/2025 13:57, Cédric Le Goater wrote:
Hello,
On 6/21/25 14:22, John Levon wrote:
On Fri, Jun 20, 2025 at 10:32:10AM +0200, Cédric Le Goater wrote:
Before merging, I would like to be able to experiment a minimum.
Does a dummy device (server s
On Sun, 22 Jun 2025 at 00:55, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/tcg/translate-sme.c | 93 ++
> target/arm/tcg/sme.decode | 71 ++
> 2 files changed, 164 insertions(+)
Reviewed-by: Peter
On Sun, Jun 22, 2025 at 10:39 PM gaosong wrote:
>
> 在 2025/6/21 上午2:12, Stefan Hajnoczi 写道:
> > On Thu, Jun 19, 2025 at 11:11 PM gaosong wrote:
> >> 在 2025/6/20 上午4:39, Stefan Hajnoczi 写道:
> >>> gpg:using RSA key CA473C44D6A09C189A193FCD452B96852B268216
> >>> gpg: Can't check sign
Hello,
I reviewed a very unintuitive implementation of Sstc in Sail, and QEMU
seems to have a minor bug there, which is addressed [1/2].
[2/2] is just a sanitization.
I only compiled the code, and have no idea how to easily test it, so
feel free to drop the patches, and treat this as a bug report
Hi Radim,
It seems like this patch is breaking 'make check-functional':
12/12 qemu:func-quick+func-riscv64 / func-riscv64-riscv_opensbi TIMEOUT
90.06s killed by signal 15 SIGTERM
Checking the logs I verified that the problem can be reproduced by running the
'spike' machine as follo
From: Chenyi Qiang
Commit 852f0048f3 ("RAMBlock: make guest_memfd require uncoordinated
discard") highlighted that subsystems like VFIO may disable RAM block
discard. However, guest_memfd relies on discard operations for page
conversion between private and shared memory, potentially leading to
th
From: Jaehoon Kim
When the source VM attempts to connect to the destination VM's Unix
domain socket (cpr.sock) during a cpr-transfer test, race conditions can
occur if the socket file isn't ready. This can lead to connection
failures when running tests.
This patch creates and listens on the sock
On 6/21/25 16:50, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate-sme.c | 25 +
target/arm/tcg/sme.decode | 9 +
2 files changed, 34 insertions(+)
diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/transl
On Thu, Jun 19, 2025 at 08:08:24PM -0400, Stefan Hajnoczi wrote:
> io_uring may not be available at runtime due to system policies (e.g.
> the io_uring_disabled sysctl) or creation could fail due to file
> descriptor resource limits.
>
> Handle failure scenarios as follows:
>
> If another AioCont
On 6/23/25 03:06, Peter Maydell wrote:
On Sun, 22 Jun 2025 at 00:58, Richard Henderson
wrote:
Signed-off-by: Richard Henderson
---
tcg/tcg-op-gvec.c | 55 ++-
1 file changed, 31 insertions(+), 24 deletions(-)
diff --git a/tcg/tcg-op-gvec.c b/tcg
riscv_cpu_dump_state() is using the same pattern to print a CSR given
its number. Add a helper to avoid code repetition.
While we're at it fix the identation of the 'flags & CPU_DUMP_VPU'
block.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 54 +++--
On 6/4/25 05:00, Arusekk wrote:
--- a/linux-user/i386/signal.c
+++ b/linux-user/i386/signal.c
@@ -865,3 +865,12 @@ void setup_sigtramp(abi_ulong sigtramp_page)
unlock_user(tramp, sigtramp_page, 2 * 8);
}
#endif
+
+bool is_vdso_sigreturn(abi_ulong pc)
+{
+#ifndef TARGET_X86_64
+if (p
On Sun, 22 Jun 2025 at 00:56, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/tcg/translate-sme.c | 31 +++
> target/arm/tcg/sme.decode | 20
> 2 files changed, 51 insertions(+)
>
> diff --git a/target/arm/tcg
On 6/23/25 4:12 PM, jro...@linux.ibm.com wrote:
> From: Jared Rossi
>
> Replace a recently introduced legacy API call with the preferred API call.
>
> fixes: 0927875 (hw/s390x: Build an IPLB for each boot device)
> Signed-off-by: Jared Rossi
> ---
> hw/s390x/ipl.c | 10 +-
> 1 file cha
On 6/23/25 20:57, Stefan Hajnoczi wrote:
On Mon, Jun 23, 2025 at 9:09 AM Daniel P. Berrangé wrote:
On Mon, Jun 23, 2025 at 09:04:33AM -0400, Stefan Hajnoczi wrote:
On Mon, Jun 23, 2025 at 4:04 AM Daniel P. Berrangé wrote:
On Mon, Jun 23, 2025 at 03:03:19PM +0800, Xiaoyao Li wrote:
On 6/23
zones and page table page monitoring. so
there may be some more bugs when we try to test it out in a simulator.
- https://github.com/michaeljclark/glyph/
- https://metaparadigm.com/~mclark/glyph-20250623.pdf
errata:
- swap the supervisor and physical address space prefixes
to be consistent
On Mon, Jun 23, 2025 at 23:25:28 +0530, Anushree Mathur wrote:
> CC: libvirt devel list
>
> Hi Kevin/Peter,
>
> Thank you so much for addressing this issue. I tried out few more things and
> here is my analysis:
>
> Even when I removed the readonly option from guest xml I was still seeing the
>
On Thu, Jun 19, 2025 at 08:08:17PM -0400, Stefan Hajnoczi wrote:
> When an AioHandler is enqueued on ctx->submit_list for removal, the
> fill_sq_ring() function will submit an io_uring POLL_REMOVE operation to
> cancel the in-flight POLL_ADD operation.
>
> There is a race when another thread enque
From: Jared Rossi
Replace a recently introduced legacy API call with the preferred API call.
fixes: 0927875 (hw/s390x: Build an IPLB for each boot device)
Signed-off-by: Jared Rossi
---
hw/s390x/ipl.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/hw/s390x/ipl.c
From: Jared Rossi
Remediate the use of a legacy API call introduced by a recent patch.
Jared Rossi (1):
hw/s390x: Use preferred API call for IPLB chain write
hw/s390x/ipl.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
--
2.49.0
From: Chenyi Qiang
Update ReplayRamDiscard() function to return the result and unify the
ReplayRamPopulate() and ReplayRamDiscard() to ReplayRamDiscardState() at
the same time due to their identical definitions. This unification
simplifies related structures, such as VirtIOMEMReplayData, which ma
The following changes since commit 43ba160cb4bbb193560eb0d2d7decc4b5fc599fe:
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
(2025-06-21 10:00:46 -0400)
are available in the Git repository at:
https://gitlab.com/peterx/qemu.git tags/migration-staging-pull-request
f
From: Chenyi Qiang
Modify memory_region_set_ram_discard_manager() to return -EBUSY if a
RamDiscardManager is already set in the MemoryRegion. The caller must
handle this failure, such as having virtio-mem undo its actions and fail
the realize() process. Opportunistically move the call earlier to
From: Chenyi Qiang
A new field, attributes, was introduced in RAMBlock to link to a
RamBlockAttributes object, which centralizes all guest_memfd related
information (such as fd and status bitmap) within a RAMBlock.
Create and initialize the RamBlockAttributes object upon ram_block_add().
Meanwhi
From: "Chaney, Ben"
Syncing volatile memory provides no benefit, instead it can cause
performance issues in some cases. Only sync memory that is marked as
non-volatile after migration completes on destination.
Signed-off-by: Ben Chaney
Fixes: bd108a44bc29 (migration: ram: Switch to ram block w
From: Chenyi Qiang
Rename the helper to memory_region_section_intersect_range() to make it
more generic. Meanwhile, define the @end as Int128 and replace the
related operations with Int128_* format since the helper is exported as
a wider API.
Suggested-by: Alexey Kardashevskiy
Reviewed-by: Alex
From: Jaehoon Kim
Extend cpr_transfer_input to handle SOCKET_ADDRESS_TYPE_FD alongside
SOCKET_ADDRESS_TYPE_UNIX. This change supports the use of pre-listened
socket file descriptors for cpr migration channels.
This change is particularly useful in qtest environments, where the
socket may be crea
From: Fabiano Rosas
Commit 407bc4bf90 ("qapi: Move include/qapi/qmp/ to include/qobject/")
brought the migration-helpers.c back by mistake. This file has been
replaced with migration/migration-qmp.c and
migration/migration-util.c.
Fixes: 407bc4bf90 ("qapi: Move include/qapi/qmp/ to include/qobje
From: Yanfei Xu
There won't be any ram sync after the stage of save_complete, therefore
it's unnecessary to do manually protect for dirty pages being sent. Skip
to do this in last round can reduce noticeable downtime.
Signed-off-by: Yanfei Xu
Tested-by: Fabiano Rosas
Reviewed-by: Fabiano Rosas
On Mon, Jun 16, 2025 at 5:27 AM Markus Armbruster wrote:
>
> More than a year ago, Daniel posted patches to put an AI policy in
> writing. Reception was mostly positive. A v2 to address feedback
> followed with some delay. But no pull request.
>
> I asked Daniel why, and he told me he was conce
On 6/23/25 10:00, Peter Maydell wrote:
On Sun, 22 Jun 2025 at 00:53, Richard Henderson
wrote:
Add gen_helper_gvec_sudot_idx_4b as an expander which
swaps arguments and uses helper_gvec_usdot_idx_4b.
Signed-off-by: Richard Henderson
---
target/arm/tcg/helper.h | 2 --
target/arm/tcg/tr
The specification states that menvcfg.STCE=0 prevents both *stimecmp
CSRs from having an effect on the pending interrupts.
henvcfg.STCE=0 disables only vstimecmp.
Make sure that when *envcfg.STCE is not set:
* writing the *stimecmp CSRs doesn't modify the *ip CSRs,
* and that the interrupt timer i
On 5/13/25 08:03, Daniel P. Berrangé wrote:
There are a number of resource leaks in gen-vdso. In theory they are
harmless because this is a short lived process, but when building QEMU
with --extra-cflags="-fsanitize=address" problems ensure. The gen-vdso
program is run as part of the build, and t
Hi Eric,
On 6/17/25 10:26, Eric Auger wrote:
Hi Gustavo,
On 6/17/25 3:01 PM, Gustavo Romero wrote:
Hi Eric,
Thanks a lot for doing a first pass on this series!
On 6/17/25 06:35, Eric Auger wrote:
Hi Gustavo,
On 6/16/25 3:18 PM, Gustavo Romero wrote:
Since v2:
- Fixed no_tcg_its inverted l
On Mon, Jun 23, 2025 at 9:09 AM Daniel P. Berrangé wrote:
>
> On Mon, Jun 23, 2025 at 09:04:33AM -0400, Stefan Hajnoczi wrote:
> > On Mon, Jun 23, 2025 at 4:04 AM Daniel P. Berrangé
> > wrote:
> > >
> > > On Mon, Jun 23, 2025 at 03:03:19PM +0800, Xiaoyao Li wrote:
> > > > On 6/23/2025 2:43 PM, C
Ping.
On 6/3/25 01:08, Richard Henderson wrote:
We already track and use known 0's; do the same for 1's.
This actually simplifies some of the logical operations,
where before required checking for a constant value.
Changes for v2:
- Some simplifications suggested by Paolo.
- Merge affect
This commit may broken the "vendor=" configuration.
For instance, the hypervisor CPU vendor is AMD.
I am going to use "-cpu Skylake-Server,vendor=GenuineIntel".
Because of the commit, the vendor is still AMD.
[root@vm ~]# cpuid -1 -l 0x0
CPU:
vendor_id = "AuthenticAMD"
If I revert this pa
On 6/23/25 12:00 PM, Matthew Rosato wrote:
To improve review coverage, assign additional people as reviewers for
multiple s390 sections.
Signed-off-by: Matthew Rosato
Acked-by: Jason J. Herne
On 6/23/25 09:38, Peter Maydell wrote:
On Sun, 22 Jun 2025 at 00:54, Richard Henderson
wrote:
Signed-off-by: Richard Henderson
---
target/arm/tcg/helper-sme.h| 5
target/arm/tcg/sme_helper.c| 44 ++
target/arm/tcg/translate-sme.c | 18
On 6/23/25 12:00 PM, Matthew Rosato wrote:
> To improve review coverage, assign additional people as reviewers for
> multiple s390 sections.
>
> Signed-off-by: Matthew Rosato
> ---
Acked-by: Collin Walling
> MAINTAINERS | 12
> 1 file changed, 12 insertions(+)
>
> diff --git a/M
At this moment we're printing a small selection of CSRs. There's no
particular reason to not print all of them.
We're ignoring the note about CSR_SSTATUS being ommited because it can
be read via CSR_MSTATUS. There's a huge list of CSRs that would fall in
this category and it would be an extra burd
On 6/23/25 12:00 PM, Matthew Rosato wrote:
To improve review coverage, assign additional people as reviewers for
multiple s390 sections.
Signed-off-by: Matthew Rosato
Acked-by: Jared Rossi
---
MAINTAINERS | 12
1 file changed, 12 insertions(+)
diff --git a/MAINTAINERS b/M
We're missing fflags and frm.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 67e4eda4f9..95d0b88937 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -593,6 +593,8 @@ stat
Hi,
The output of HMP 'info registers', implemented by the cpu_dump_state
callback, returns way less CSRs than what we have available in the
default rv64 CPU with default options.
This series changes the callback to add all available non-vector CSRs
when issuing 'info registers'. The vector CSRs
On 6/23/25 03:44, Peter Maydell wrote:
+static inline bool isar_feature_aa64_sme2_i16i64(const ARMISARegisters *id)
+{
+return isar_feature_aa64_sme2(id) && isar_feature_aa64_sme_i16i64(id);
+}
I think we should put these "utility" functions that are
testing for a combination of architectur
Acked-by: Farhan Ali
On 6/23/2025 9:00 AM, Matthew Rosato wrote:
To improve review coverage, assign additional people as reviewers for
multiple s390 sections.
Signed-off-by: Matthew Rosato
---
MAINTAINERS | 12
1 file changed, 12 insertions(+)
diff --git a/MAINTAINERS b/MAINT
On Sun, 22 Jun 2025 at 00:53, Richard Henderson
wrote:
>
> Add gen_helper_gvec_sudot_idx_4b as an expander which
> swaps arguments and uses helper_gvec_usdot_idx_4b.
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/tcg/helper.h | 2 --
> target/arm/tcg/translate.h | 3 +++
> target/a
On Mon, 23 Jun 2025 12:00:30 -0400
Matthew Rosato wrote:
> To improve review coverage, assign additional people as reviewers for
> multiple s390 sections.
>
> Signed-off-by: Matthew Rosato
Acked-by: Halil Pasic
On Sun, 22 Jun 2025 at 00:51, Richard Henderson
wrote:
>
> Emphasize that these are 4-way dot products.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
thanks
-- PMM
There is no need to keep the timer running when writing a past value to
the *stimecmp. The behavior was correct before, but I think it makes a
bit more sense like this.
Signed-off-by: Radim Krčmář
---
target/riscv/time_helper.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/
On Sun, 22 Jun 2025 at 00:53, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
Reviewed-by: Peter Maydell
thanks
-- PMM
On Sun, 22 Jun 2025 at 00:55, Richard Henderson
wrote:
>
> Indicate whether to use FPST_FPCR or FPST_ZA via bit 2 of
> simd_data(desc). For SVE, this bit remains zero.
> For do_FMLAL_zzzw, this requires no change.
> For do_FMLAL_zzxw, move the index up one bit.
>
> Read fz16 directly from env->fp
On Sun, 22 Jun 2025 at 00:54, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/tcg/translate-sme.c | 17 +
> target/arm/tcg/sme.decode | 9 +
> 2 files changed, 26 insertions(+)
>
Reviewed-by: Peter Maydell
thanks
-- PMM
On Sun, 22 Jun 2025 at 00:54, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/tcg/helper-sme.h| 5
> target/arm/tcg/sme_helper.c| 44 ++
> target/arm/tcg/translate-sme.c | 18 ++
> target/arm/tcg/translate
On Sun, 22 Jun 2025 at 00:57, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/tcg/translate.h | 2 ++
> target/arm/tcg/translate-sme.c | 29 +
> target/arm/tcg/sme.decode | 15 +++
> 3 files changed, 46 insertions
On 23/06/2025 09:36, John Levon wrote:
On Sun, Jun 22, 2025 at 02:57:57PM +0200, Cédric Le Goater wrote:
PCI enumeration work but the kernel module won't load on ubuntu 24.04
Sorry, I forgot - there's a kernel bug in the Ubuntu LTS kernel for this driver.
Mark has a fix - Mark, can you share
On 6/23/25 12:00 PM, Matthew Rosato wrote:
> To improve review coverage, assign additional people as reviewers for
> multiple s390 sections.
>
> Signed-off-by: Matthew Rosato
Acked-by: Zhuoying Cai
> ---
> MAINTAINERS | 12
> 1 file changed, 12 insertions(+)
>
> diff --git a/MAI
On 22/06/2025 13:57, Cédric Le Goater wrote:
Hello,
On 6/21/25 14:22, John Levon wrote:
On Fri, Jun 20, 2025 at 10:32:10AM +0200, Cédric Le Goater wrote:
Before merging, I would like to be able to experiment a minimum.
Does a dummy device (server side) implementation exist ? and a
GH repo I
On Mon, 2025-06-23 at 12:00 -0400, Matthew Rosato wrote:
> To improve review coverage, assign additional people as reviewers for
> multiple s390 sections.
>
> Signed-off-by: Matthew Rosato
Acked-by: Eric Farman
> ---
> MAINTAINERS | 12
> 1 file changed, 12 insertions(+)
>
> dif
On Sun, 22 Jun 2025 at 00:58, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/tcg/translate-sme.c | 65 ++
> target/arm/tcg/sme.decode | 36 +++
> 2 files changed, 101 insertions(+)
Reviewed-by: Peter Maydell
Philippe Mathieu-Daudé writes:
> On 23/6/25 17:04, Alex Bennée wrote:
>> Philippe Mathieu-Daudé writes:
>>
>>> Signed-off-by: Philippe Mathieu-Daudé
>>> ---
>>> tests/functional/test_aarch64_smmu.py | 12 +---
>>> 1 file changed, 9 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/
To improve review coverage, assign additional people as reviewers for
multiple s390 sections.
Signed-off-by: Matthew Rosato
---
MAINTAINERS | 12
1 file changed, 12 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 94c4076127..3ce6fce8ce 100644
--- a/MAINTAINERS
+++ b/MAIN
On 6/23/25 08:25, Peter Maydell wrote:
On Sun, 22 Jun 2025 at 00:58, Richard Henderson
wrote:
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate-sme.c | 65 ++
target/arm/tcg/sme.decode | 36 +++
2 files changed, 101 insertio
On 6/23/25 07:20, Peter Maydell wrote:
On Sun, 22 Jun 2025 at 00:54, Richard Henderson
wrote:
Signed-off-by: Richard Henderson
---
+static bool do_mova_tile_n(DisasContext *s, arg_mova_t *a, int n, bool to_vec)
+{
+static gen_helper_gvec_2 * const cz_fns[] = {
+gen_helper_sme
On 6/23/25 05:21, Peter Maydell wrote:
+TRANS_FEAT(LDR_zt0, aa64_sme2, do_ldst_zt0, a, gen_sve_ldr)
+TRANS_FEAT(STR_zt0, aa64_sme2, do_ldst_zt0, a, gen_sve_str)
The alignment check the pseudocode requires happens inside
gen_sve_ldr/str, right? I don't entirely understand why, though,
because th
On Sun, 22 Jun 2025 at 00:58, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/tcg/translate-sme.c | 65 ++
> target/arm/tcg/sme.decode | 36 +++
> 2 files changed, 101 insertions(+)
>
> diff --git a/target/arm/
On Sun, 22 Jun 2025 at 00:55, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/tcg/helper-sme.h| 13
> target/arm/tcg/vec_internal.h | 4 ++
> target/arm/tcg/helper-a64.c| 2 +
> target/arm/tcg/translate-sme.c | 115 +
On 23/6/25 17:04, Alex Bennée wrote:
Philippe Mathieu-Daudé writes:
Signed-off-by: Philippe Mathieu-Daudé
---
tests/functional/test_aarch64_smmu.py | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/tests/functional/test_aarch64_smmu.py
b/tests/functional/tes
Hi Jonathan,
On 6/20/25 12:31 PM, Jonathan Cameron wrote:
> On Mon, 16 Jun 2025 11:46:56 +0200
> Eric Auger wrote:
>
>> From: Gustavo Romero
>>
>> Soon we will introduce a new test related to ACPI PCI hotplug that
>> will use a new reference blob:
>>
>> tests/data/acpi/aarch64/virt/DSDT.acpipcih
Philippe Mathieu-Daudé writes:
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> tests/functional/test_aarch64_smmu.py | 12 +---
> 1 file changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/tests/functional/test_aarch64_smmu.py
> b/tests/functional/test_aarch64_smmu.py
> index c65
On Sun, 22 Jun 2025 at 00:52, Richard Henderson
wrote:
>
> To be used by both SVE2 and SME2.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
thanks
-- PMM
Commit b84694defb added the CPU_DUMP_VPU to allow vector registers to be
logged by log_cpu_exec() in TCG. This flag was then used in commit
b227f6a8a7 to print RISC-V vector registers using this flag. Note that
this change was done in riscv_cpu_dump_state(), the cpu_dump_state()
callback for RISC-V
On Sun, 22 Jun 2025 at 00:55, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/tcg/helper-sme.h| 4
> target/arm/tcg/sme_helper.c| 37 +-
> target/arm/tcg/translate-sme.c | 2 ++
> target/arm/tcg/sme.decode | 2
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