Update the python tests to also check qapi. No idea why I didn't do this
before. I guess I was counting on moving it under python/ and then just
forgot after that was NACKed. Oops, this turns out to be really easy.
flake8, isort and mypy use the tool configuration from the existing
python director
Currently resetting the leads to resynchronizing the Goldfish RTC with the
system clock of the host. In real hardware an RTC reset would not change
the wall time. Other RTCs like pl031 do not show this behavior.
Move the synchronization of the RTC with the system clock to the instance
realization.
RISC-V IO Mapping Table (RIMT) is a new static ACPI table used to
communicate IOMMU information to the OS. Add support for creating this
table when the IOMMU is present. The specification is frozen and
available at [1].
[1] -
https://github.com/riscv-non-isa/riscv-acpi-rimt/releases/download/v0.9
RISC-V IO Mapping Table (RIMT) is a new static ACPI table used to
communicate IOMMU and topology information to the OS. Add support for
creating this table when the IOMMU is present. The specification is
frozen and available at [1].
[1] -
https://github.com/riscv-non-isa/riscv-acpi-rimt/releases/
Add the TCGCPUOps::guest_default_memory_order field and have
each target initialize it.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Anton Johansson
Reviewed-by: Richard Henderson
Reviewed-by: Pierrick Bouvier
---
include/accel/tcg/cpu-ops.h | 8
target/alpha/cpu.c | 2
From: Pierrick Bouvier
This identifier is poisoned, so it can't be used from common code
anyway. We replace all occurrences with its definition directly.
Signed-off-by: Pierrick Bouvier
Link:
https://lore.kernel.org/r/20250320223002.2915728-2-pierrick.bouv...@linaro.org
Signed-off-by: Paolo Bo
qemu_tcg_mttcg_enabled() is specific to 1/ TCG and
2/ system emulation. Move the prototype declaration
to "system/tcg.h", reducing 'mttcg_enabled' variable
scope.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Pierrick Bouvier
---
include/hw/core/cpu.h | 9 -
include/system/tc
The HACE models in AST2600 and AST2700 are nearly identical. Based on the
AST2600 test cases, new tests have been added for AST2700.
Implemented test functions for SHA-256, SHA-384, SHA-512, and MD5.
Added scatter-gather and accumulation test variants.
For AST2700, the HACE controller base address
This patch changes the qapidoc transmogrifier to generate Return value
documentation for any command that has a return value but hasn't
explicitly documented that return value.
Signed-off-by: John Snow
---
docs/sphinx/qapidoc.py | 14 --
scripts/qapi/parser.py | 11 +++
scrip
Well, I tried. Maybe not very hard. Sorry!
Signed-off-by: John Snow
---
qapi/block-core.json | 6 +++---
qapi/block-export.json | 2 +-
qapi/block.json | 2 +-
qapi/control.json| 5 ++---
qapi/dump.json | 5 ++---
qapi/introspect.json | 6 +++---
qapi/job.jso
Basically RFC quality, I'm sure there's going to be a ton of back and
forth on the doc phrasing changes. Ah well.
John Snow (4):
docs/qapi-domain: add return-nodesc
docs, qapi: generate undocumented return sections
qapi: remove trivial "Returns:" sections
qapi: rephrase return docs to avoi
This form is used to annotate a return type without an accompanying
description, for when there is no "Returns:" information in the source
doc, but we have a return type we want to generate a cross-reference to.
The syntax is:
:return-nodesc: TypeName
It's primarily necessary because Sphinx alwa
The new qapidoc transmogrifier can generate "Returns" statements with
type information just fine, so we can remove it from the source where it
doesn't add anything particularly novel or helpful and just repeats the
type info.
This patch does not touch Returns: lines that add some information
(pote
On 3/21/25 17:01, Pierrick Bouvier wrote:
On 3/21/25 15:19, Richard Henderson wrote:
On 3/21/25 13:11, Pierrick Bouvier wrote:
On 3/21/25 12:27, Richard Henderson wrote:
On 3/21/25 11:09, Pierrick Bouvier wrote:
Mmm, ok I guess. Yesterday I would have suggested merging this with
page-vary.h
On 3/21/25 15:19, Richard Henderson wrote:
On 3/21/25 13:11, Pierrick Bouvier wrote:
On 3/21/25 12:27, Richard Henderson wrote:
On 3/21/25 11:09, Pierrick Bouvier wrote:
Mmm, ok I guess. Yesterday I would have suggested merging this with
page-vary.h, but
today I'm actively working on making
From: Zhao Liu
Remove the `unsafe` block of vmsd, because vmsd (passed to
vmstate_struct) is defined in Rust side now, and it doesn't need
`unsafe`.
Signed-off-by: Zhao Liu
Link: https://lore.kernel.org/r/20250318130219.1799170-2-zhao1@intel.com
Signed-off-by: Paolo Bonzini
---
rust/qemu-
On 3/20/25 15:29, Pierrick Bouvier wrote:
We introduce later a mechanism to skip cpu definitions inclusion, so we
can detect it here, and call the correct runtime function instead.
Signed-off-by: Pierrick Bouvier
---
include/exec/target_page.h | 3 +++
1 file changed, 3 insertions(+)
diff -
Directly condition associated calls in target/arm/helper.c for now.
Signed-off-by: Pierrick Bouvier
---
target/arm/cpu.h| 8
target/arm/helper.c | 6 ++
2 files changed, 6 insertions(+), 8 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index b1c3e463267..c1a0faed
A few transitive dependencies were left floating; as a result, pip's
dependency solver can pull in newer dependencies, which we don't
want. Pin them down.
Signed-off-by: John Snow
---
python/tests/minreqs.txt | 4
1 file changed, 4 insertions(+)
diff --git a/python/tests/minreqs.txt b/pyth
This restores the linting baseline in QAPI.
Signed-off-by: John Snow
---
scripts/qapi/backend.py | 2 ++
1 file changed, 2 insertions(+)
diff --git a/scripts/qapi/backend.py b/scripts/qapi/backend.py
index 14e60aa67af..49ae6ecdd33 100644
--- a/scripts/qapi/backend.py
+++ b/scripts/qapi/backend.
This restores the linting baseline in qapidoc. The order of some imports
have changed slightly due to configuring isort a little better: isort
was having difficulty understanding that "compat" and "qapidoc_legacy"
were local modules because docs/sphinx "isn't a python package".
Signed-off-by: John
The pylint config is being left in place because the settings differ
enough from the python/ directory settings that we need a chit-chat on
how to merge them O:-)
Everything else can go.
Signed-off-by: John Snow
---
scripts/qapi/.flake8| 3 ---
scripts/qapi/.isort.cfg | 7 ---
scripts/q
On 3/19/25 13:21, Joao Martins wrote:
On 18/03/2025 09:54, Cédric Le Goater wrote:
Rename these routines :
vfio_devices_all_device_dirty_tracking_started ->
vfio_dirty_tracking_devices_is_started_all
vfio_devices_all_dirty_tracking_started->
vfio_dirty_tracking_devices_is_starte
On 3/21/25 13:11, Pierrick Bouvier wrote:
On 3/21/25 12:27, Richard Henderson wrote:
On 3/21/25 11:09, Pierrick Bouvier wrote:
Mmm, ok I guess. Yesterday I would have suggested merging this with
page-vary.h, but
today I'm actively working on making TARGET_PAGE_BITS_MIN a global constant.
W
From: Zhao Liu
The VMState type bound is not used in with_varray_flag().
And for vmstate_struct, Rust cannot infer the type of `num` from the
call_func_with_field(), so this causes the compiling error because it
complains "cannot satisfy `_: VMState`" in with_varray_flag().
Note Rust can infer
On 3/20/25 15:29, Pierrick Bouvier wrote:
Signed-off-by: Pierrick Bouvier
---
include/exec/cpu-all.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index d4705210370..d4d05d82315 100644
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all
On Tue, Mar 11 2025, Richard Henderson wrote:
> On 3/11/25 09:28, Cornelia Huck wrote:
>> +/* read a sysreg value and store it in the idregs */
>> +static int get_host_cpu_reg(int fd, ARMHostCPUFeatures *ahcf,
>> ARMIDRegisterIdx index)
>
> This still isn't used, and so must Werror.
Hm, I guess
Add the TCGCPUOps::guest_default_memory_order field and have
each target initialize it.
Use it to set TCGContext::guest_mo in tb_gen_code(), removing
the need for the TCG_GUEST_DEFAULT_MO definition.
Signed-off-by: Philippe Mathieu-Daudé
---
include/accel/tcg/cpu-ops.h | 8
target/a
Pierrick Bouvier writes:
> On 3/19/25 11:22, Alex Bennée wrote:
>> The aim of this work is to get rid of the endian aware helpers in
>> gdbstub/helpers.h which due to their use of tswap() mean target
>> gdbstubs need to be built multiple times. While this series doesn't
>> actually build each stu
From: Zhao Liu
Add a unit test to cover some patterns accepted by vmstate_of and
vmstate_struct macros, which correspond to the following C version
macros:
* VMSTATE_BOOL_V
* VMSTATE_U64
* VMSTATE_STRUCT_VARRAY_UINT8
* (no C version) MULTIPLY variant of VMSTATE_STRUCT_VARRAY_UINT32
* VMSTAT
Now that TCG_GUEST_DEFAULT_MO is always defined,
simplify the tcg_req_mo() macro.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Anton Johansson
Reviewed-by: Richard Henderson
Reviewed-by: Pierrick Bouvier
---
accel/tcg/internal-target.h | 9 +
accel/tcg/tcg-all.c | 3 ---
On Fri, Mar 21, 2025 at 11:33:31AM +0530, Manish wrote:
> Hi Daniel, Peter,
>
> Please let me know if this latest patch looks good?
>
>
> On 17/03/25 7:22 am, Manish Mishra wrote:
> > We allocate extra metadata SKBs in case of a zerocopy send. This metadata
> > memory is accounted for in the OPT
On 21/03/25, Philippe Mathieu-Daudé wrote:
> Instead of having a compile-time TARGET_SUPPORTS_MTTCG definition,
> have each target set the 'mttcg_supported' field in the TCGCPUOps
> structure.
>
> Since so far we only emulate one target architecture at a time,
> tcg_init_machine() gets whether MTT
On 3/21/25 12:27, Richard Henderson wrote:
On 3/21/25 11:09, Pierrick Bouvier wrote:
Mmm, ok I guess. Yesterday I would have suggested merging this with
page-vary.h, but
today I'm actively working on making TARGET_PAGE_BITS_MIN a global constant.
When you mention this, do you mean "constant
On 3/21/25 11:34, Philippe Mathieu-Daudé wrote:
Use the OnOffAuto type as 3-state.
Since the TCGState instance is zero-initialized, the
mttcg_enabled is initialzed as AUTO (ON_OFF_AUTO_AUTO).
In tcg_init_machine(), if mttcg_enabled is still AUTO,
set a default value (effectively inlining the
de
From: Zhao Liu
At present, Rust side has a timer binding "timer::Timer", so the vmstate
for timer should base on that binding instead of the raw
"binding::QEMUTimer".
It's possible to apply impl_vmstate_transparent for cell::Opaque and
then impl_vmstate_forward for timer::Timer. But binding::QEM
From: Zhao Liu
Array type vmstate has the VMStateField with `num` equals its length.
When the varray vmstate is built based a array type, the `num` field
should be cleaned to 0, because varray uses `num_offset` instead of
`num` to store elements number information.
Signed-off-by: Zhao Liu
Link
From: Zhao Liu
`num_offset` is a member of `VMStateField`, and there's no need to use
"." to access this field in a `VMStateField` instance.
Signed-off-by: Zhao Liu
Link: https://lore.kernel.org/r/20250318130219.1799170-3-zhao1@intel.com
Signed-off-by: Paolo Bonzini
---
rust/qemu-api/src/
From: Zhao Liu
The use of "bindings::*" masks incomplete path of VMStateFlags.
Include complete crate path of VMStateFlags in vmstate_clock, and clean
up "bindings::*" in device_class.rs of pl011.
Signed-off-by: Zhao Liu
Link: https://lore.kernel.org/r/20250318130219.1799170-16-zhao1@intel
From: Zhao Liu
The `size` field of the VMStateField with VMS_ARRAY_OF_POINTER flag
should stores the size of pointer, which depends on platform.
Currently, `*const`, `*mut`, `NonNull`, `Box<>` and their wrapper are
supported, and they have the same size as `usize`.
Store the size (of `usize`) w
On 3/21/25 11:09, Pierrick Bouvier wrote:
Mmm, ok I guess. Yesterday I would have suggested merging this with
page-vary.h, but
today I'm actively working on making TARGET_PAGE_BITS_MIN a global constant.
When you mention this, do you mean "constant accross all architectures", or a global
(c
In order to use TCG with multiple targets, replace the
compile time use of TCG_GUEST_DEFAULT_MO by a runtime access
to TCGCPUOps::guest_default_memory_order via CPUState.
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/internal-target.h | 9 -
1 file changed, 4 insertions(+), 5 delet
(forgot to Cc Alex!)
On 21/3/25 16:59, Philippe Mathieu-Daudé wrote:
In this series we replace the TARGET_SUPPORTS_MTTCG (Makefile)
definition by a 'mttcg_supported' field in TCGCPUOps.
Based-on: <20250321125737.72839-1-phi...@linaro.org>
Philippe Mathieu-Daudé (4):
target/riscv: Restrict R
On 21/3/25 13:57, Philippe Mathieu-Daudé wrote:
Add the TCGCPUOps::guest_default_memory_order field and have
each target initialize it.
Use it to set TCGContext::guest_mo in tb_gen_code(), removing
the need for the TCG_GUEST_DEFAULT_MO definition.
Signed-off-by: Philippe Mathieu-Daudé
---
in
From: Zhao Liu
Add a unit test for vmstate_validate, which corresponds to the C version
macro: VMSTATE_VALIDATE.
Signed-off-by: Zhao Liu
Link: https://lore.kernel.org/r/20250318130219.1799170-15-zhao1@intel.com
Signed-off-by: Paolo Bonzini
---
rust/qemu-api/tests/vmstate_tests.rs | 82 +++
From: Zhao Liu
Add a unit test to cover some patterns accepted by vmstate_of macro,
which correspond to the following C version macros:
* VMSTATE_POINTER
* VMSTATE_ARRAY_OF_POINTER
Note: Currently, vmstate_struct can't handle the pointer to structure
case. Leave this case as a FIXME and use vm
From: Peter Maydell
We have some users of the PL011 struct which embed it directly into
their own state structs. This means that the Rust version of the
device must have a state struct that is the same size or smaller
than the C struct.
In commit 9b642097d6b7 ("rust: pl011: switch to safe charde
The CPU_RESOLVING_TYPE definition was added in commit
0dacec874fa ("cpu: add CPU_RESOLVING_TYPE macro"), but
then added again in commit d3ae32d4d20. Remove the
duplication.
Fixes: d3ae32d4d20 ("target/hppa: Implement cpu_list")
Signed-off-by: Philippe Mathieu-Daudé
---
target/hppa/cpu.h | 2 --
From: Zhao Liu
In C version, VMSTATE_VALIDATE accepts the function pointer, which is
used to check if some conditions of structure could meet, although the
C version macro doesn't accept any structure as the opaque type.
But it's hard to integrate VMSTATE_VALIDAE into vmstate_struct, a new
macro
Due to a missing "& 0x18", timer registers are not decoded correctly.
This breaks the tests/functional/test_x86_64_tuxrun.py functional
test.
Fixes: 519088b7cf6 ("rust: hpet: decode HPET registers into enums", 2025-03-06)
Reported-by: Peter Maydell
Tested-by: Peter Maydell
Reviewed-by: Peter May
From: Zhao Liu
The varry of structure created by vmstate_struct is different with
vmstate_of. This is because vmstate_struct uses the `vmsd` to traverse
the vmstates of structure's fields, rather than treating the structure
directly as a well-defined vmstate.
Therefore, there's no need to check
Targets know whether they are big-endian more than they know if
the endianness is different from the host: the former is mostly
a constant, at least in machine creation code, while the latter
has to be computed with TARGET_BIG_ENDIAN != HOST_BIG_ENDIAN or
something like that.
load_aout, however, t
From: Zhao Liu
The vmstate has too many combinations of VMStateFlags and VMStateField.
Currently, the best way to test is to ensure that the Rust vmstate
definition is consistent with the (possibly corresponding) C version.
Add a unit test to cover some patterns accepted by vmstate_of macro,
whi
From: Zhao Liu
When pass a varray to vmstate_struct, the `type` parameter should be the
type of the element in the varray, for example:
vmstate_struct!(HPETState, timers, [0 .. num_timers], VMSTATE_HPET_TIMER,
BqlRefCell).with_version_id(0)
But this breaks current type check, be
Add a new assertion that is similar to "const { assert!(...) }" but can be used
outside functions and with older versions of Rust. A similar macro is found in
Linux, whereas the "static_assertions" crate has a const_assert macro that
produces worse error messages.
Suggested-by: Peter Maydell
Sig
From: Peter Maydell
Currently we require everywhere that wants to know if there
is an HPET device to check for "CONFIG_HPET || CONFIG_X_HPET_RUST".
Factor out whether the HPET device is Rust or C into a separate
Kconfig stanza, so that CONFIG_HPET means "there is an HPET",
and whether this has pu
The following changes since commit 1dae461a913f9da88df05de6e2020d3134356f2e:
Update version for v10.0.0-rc0 release (2025-03-18 10:18:14 -0400)
are available in the Git repository at:
https://gitlab.com/bonzini/qemu.git tags/for-upstream
for you to fetch changes up to 64acc23c9793e86f281134
On 21/03/2025 16.58, Peter Maydell wrote:
The arm_aspeed_bletchley timeout takes more than its
current 120s timeout on a debug Rust config:
$ time (cd build/rust; PYTHONPATH=../../python:../../tests/functional
QEMU_TEST_QEMU_BINARY=./qemu-system-arm ./pyvenv/bin/python3
../../tests/functional/
Since v1:
- Update TCGState::mttcg_enabled (Anton)
- Better describe change in patch 3 (Pierrick)
In this series we replace the TARGET_SUPPORTS_MTTCG (Makefile)
definition by a 'mttcg_supported' field in TCGCPUOps.
Based-on: <20250321181549.3331-1-phi...@linaro.org>
Philippe Mathieu-Daudé (4):
Use TCGCPUOps::guest_default_memory_order to set TCGContext::guest_mo.
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/translate-all.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index fb9f83dbba3..26442e83776 1006
On 3/21/25 11:26, Philippe Mathieu-Daudé wrote:
On 21/3/25 18:36, Pierrick Bouvier wrote:
On 3/21/25 08:59, Philippe Mathieu-Daudé wrote:
Use the OnOffAuto type as 3-state.
Since the TCGState instance is zero-initialized, the
mttcg_enabled is initialzed as AUTO (ON_OFF_AUTO_AUTO).
In tcg_init
On 21/3/25 18:36, Pierrick Bouvier wrote:
On 3/21/25 08:59, Philippe Mathieu-Daudé wrote:
Use the OnOffAuto type as 3-state.
Since the TCGState instance is zero-initialized, the
mttcg_enabled is initialzed as AUTO (ON_OFF_AUTO_AUTO).
In tcg_init_machine(), if mttcg_enabled is still AUTO,
set a
On 3/21/25 08:59, Philippe Mathieu-Daudé wrote:
Use the OnOffAuto type as 3-state.
Since the TCGState instance is zero-initialized, the
mttcg_enabled is initialzed as AUTO (ON_OFF_AUTO_AUTO).
In tcg_init_machine(), if mttcg_enabled is still AUTO,
set a default value (effectively inlining the
de
In preparation of having tcg_req_mo() access CPUState in
the next commit, pass it to cpu_req_mo(), its single caller.
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/internal-target.h | 3 ++-
accel/tcg/cputlb.c | 20 ++--
accel/tcg/user-exec.c | 20 ++
By directly using TCGCPUOps::guest_default_memory_order,
we don't need the TCG_GUEST_DEFAULT_MO definition anymore.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Anton Johansson
Reviewed-by: Richard Henderson
Reviewed-by: Pierrick Bouvier
---
docs/devel/multi-thread-tcg.rst | 4 ++--
ta
Since v1:
- Do not use tcg_ctx in tcg_req_mo (rth)
Hi,
In this series we replace the TCG_GUEST_DEFAULT_MO definition
from "cpu-param.h" by a 'guest_default_memory_order' field in
TCGCPUOps.
Since tcg_req_mo() now accesses tcg_ctx, this impact the
cpu_req_mo() calls in accel/tcg/{cputlb,user-exec
On 3/21/25 11:05, Richard Henderson wrote:
On 3/20/25 15:29, Pierrick Bouvier wrote:
We introduce later a mechanism to skip cpu definitions inclusion, so we
can detect it here, and call the correct runtime function instead.
Signed-off-by: Pierrick Bouvier
---
include/exec/target_page.h | 3
On 3/20/25 15:29, Pierrick Bouvier wrote:
Signed-off-by: Pierrick Bouvier
---
include/exec/cpu-all.h | 2 --
include/exec/cpu_ldst.h | 1 +
target/alpha/cpu.h | 1 +
target/arm/cpu.h| 1 +
target/avr/cpu.h| 1 +
target/hexagon/cpu.h| 1 +
target/hppa/cpu.h
On 3/20/25 17:48, Richard Henderson wrote:
On 3/18/25 17:23, Pierrick Bouvier wrote:
uint64_t translator_ldq(CPUArchState *env, DisasContextBase *db, vaddr pc)
{
- uint64_t raw, tgt;
+ uint64_t val;
- if (translator_ld(env, db, &raw, pc, sizeof(raw))) {
- tgt = tswap64(raw)
On 06.03.2025 09:46, Deepak Gupta wrote:
Commit:8205bc1 ("target/riscv: introduce ssp and enabling controls for
zicfiss") introduced CSR_SSP but it mis-interpreted the spec on access
to CSR_SSP in M-mode. Gated to CSR_SSP is not gated via `xSSE`. But
rather rules clearly specified in section "22.
On 3/20/25 15:29, Pierrick Bouvier wrote:
We prepare to remove cpu.h from cpu-all.h, which will transitively
remove it from accel/tcg/tb-internal.h, and thus from most of tcg
compilation units.
Note: this was caught by a test regression for s390x-softmmu.
Signed-off-by: Pierrick Bouvier
---
i
On 3/20/25 15:29, Pierrick Bouvier wrote:
We prepare to remove cpu.h from cpu-all.h, which will transitively
remove it from accel/tcg/tb-internal.h, and thus from most of tcg
compilation units.
Signed-off-by: Pierrick Bouvier
---
accel/tcg/internal-target.h | 1 +
include/exec/poison.h
On 3/21/25 05:57, Philippe Mathieu-Daudé wrote:
Add the TCGCPUOps::guest_default_memory_order field and have
each target initialize it.
Use it to set TCGContext::guest_mo in tb_gen_code(), removing
the need for the TCG_GUEST_DEFAULT_MO definition.
Signed-off-by: Philippe Mathieu-Daudé
---
in
On 21/3/25 18:01, Anton Johansson wrote:
On 21/03/25, Philippe Mathieu-Daudé wrote:
Use the OnOffAuto type as 3-state.
Since the TCGState instance is zero-initialized, the
mttcg_enabled is initialzed as AUTO (ON_OFF_AUTO_AUTO).
In tcg_init_machine(), if mttcg_enabled is still AUTO,
set a defau
On 3/21/25 06:02, Philippe Mathieu-Daudé wrote:
On 20/3/25 21:16, Pierrick Bouvier wrote:
On 3/20/25 12:52, Pierrick Bouvier wrote:
On 3/19/25 11:22, Alex Bennée wrote:
The aim of this work is to get rid of the endian aware helpers in
gdbstub/helpers.h which due to their use of tswap() mean ta
On 3/21/25 05:57, Philippe Mathieu-Daudé wrote:
Now that TCG_GUEST_DEFAULT_MO is always defined,
simplify the tcg_req_mo() macro.
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/internal-target.h | 9 +
accel/tcg/tcg-all.c | 3 ---
2 files changed, 1 insertion(+), 11 del
On 3/21/25 05:57, Philippe Mathieu-Daudé wrote:
We only require the TCG_GUEST_DEFAULT_MO for MTTCG-enabled
frontends, otherwise we use a default value of TCG_MO_ALL.
In order to simplify, require the definition for all targets,
defining it for hexagon, m68k, rx, sh4 and tricore.
Signed-off-by:
On 3/21/25 08:59, Philippe Mathieu-Daudé wrote:
qemu_tcg_mttcg_enabled() is specific to 1/ TCG and
2/ system emulation. Move the prototype declaration
to "system/tcg.h", reducing 'mttcg_enabled' variable
scope.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/core/cpu.h | 9
On 3/21/25 08:59, Philippe Mathieu-Daudé wrote:
Multi-threaded TCG only concerns system emulation.
Signed-off-by: Philippe Mathieu-Daudé
---
target/riscv/tcg/tcg-cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
On 3/21/25 04:46, Alex Bennée wrote:
Pierrick Bouvier writes:
On 3/19/25 11:22, Alex Bennée wrote:
The aim of this work is to get rid of the endian aware helpers in
gdbstub/helpers.h which due to their use of tswap() mean target
gdbstubs need to be built multiple times. While this series does
On 3/21/25 04:36, Alex Bennée wrote:
Pierrick Bouvier writes:
On 3/20/25 12:30, Pierrick Bouvier wrote:
On 3/19/25 11:22, Alex Bennée wrote:
The current helper.h functions rely on hard coded assumptions about
target endianess to use the tswap macros. We also end up double
swapping a bunch of
xen_bus_realize() reports a failure to set up a watch as error, but it
doesn't treat it as one: it simply continues. Report a warning
instead.
Signed-off-by: Markus Armbruster
Message-ID: <20250314143500.2449658-3-arm...@redhat.com>
Reviewed-by: Stefano Stabellini
---
hw/xen/xen-bus.c | 7 +++-
From: Bibo Mao
Temporary variable ret is assigned at last line and return, it can
be removed and return directly.
Signed-off-by: Bibo Mao
Reviewed-by: Markus Armbruster
Reviewed-by: Philippe Mathieu-Daudé
Message-ID: <20250320032158.1762751-6-maob...@loongson.cn>
Signed-off-by: Markus Armbrus
The Error ** argument must be NULL, &error_abort, &error_fatal, or a
pointer to a variable containing NULL. Passing an argument of the
latter kind twice without clearing it in between is wrong: if the
first call sets an error, it no longer points to NULL for the second
call.
xen_bus_realize() is
On 21/03/25, Philippe Mathieu-Daudé wrote:
> In order to use TCG with multiple targets, replace the
> compile time use of TCG_GUEST_DEFAULT_MO by a runtime
> access to tcg_ctx->guest_mo.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> accel/tcg/internal-target.h | 4 +---
> 1 file changed, 1 i
Facility interrupt checks in general should come after the ISA version
check, because the facility interrupt and facility type themselves are
ISA dependent and should not appear on CPUs where the instruction does
not exist at all.
This resolves a QEMU crash booting NetBSD/macppc due to
qemu: fa
On 21/03/25, Philippe Mathieu-Daudé wrote:
> Use the OnOffAuto type as 3-state.
>
> Since the TCGState instance is zero-initialized, the
> mttcg_enabled is initialzed as AUTO (ON_OFF_AUTO_AUTO).
>
> In tcg_init_machine(), if mttcg_enabled is still AUTO,
> set a default value (effectively inlining
On 3/20/2025 12:17 PM, Stefan Hajnoczi wrote:
On Thu, Mar 20, 2025 at 11:13:04AM -0700, Farhan Ali wrote:
Hi,
I have been experimenting with the QEMU Userspace NVMe driver on s390x
architecture. I have noticed an issue when assigning multiple virtqueues and
multiple iothreads to the block dev
On Fri, Mar 21, 2025 at 2:42 PM Marc-André Lureau <
marcandre.lur...@redhat.com> wrote:
> Hi
>
> On Fri, Mar 21, 2025 at 7:40 AM wrote:
> >
> > From: Hyman Huang
> >
> > Our goal is to migrate VMs that are configured with qemu-vdagent-typed
> > chardev while allowing the agent to continue workin
On 3/20/25 15:29, Pierrick Bouvier wrote:
Signed-off-by: Pierrick Bouvier
---
include/exec/cpu-all.h | 2 --
linux-user/qemu.h | 3 +++
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index d2895fb55b1..74017a5ce7c 100644
--
On 3/20/25 15:29, Pierrick Bouvier wrote:
Signed-off-by: Pierrick Bouvier
---
include/exec/cpu-all.h | 1 -
1 file changed, 1 deletion(-)
Reviewed-by: Richard Henderson
r~
On 3/20/25 15:29, Pierrick Bouvier wrote:
Signed-off-by: Pierrick Bouvier
---
include/exec/cpu-all.h | 1 -
target/ppc/mmu-hash64.h | 2 ++
target/i386/tcg/system/excp_helper.c | 1 +
target/i386/xsave_helper.c | 1 +
target/riscv/vector_helper.c
On 3/20/25 15:29, Pierrick Bouvier wrote:
We include this header where needed. When includes set already have
ifdef CONFIG_USER_ONLY, we add it here, else, we don't condition the
include.
Signed-off-by: Pierrick Bouvier
---
hw/s390x/ipl.h | 1 +
include/exec/cpu-all.h
Now that TCG_GUEST_DEFAULT_MO is always defined,
simplify the tcg_req_mo() macro.
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/internal-target.h | 9 +
accel/tcg/tcg-all.c | 3 ---
2 files changed, 1 insertion(+), 11 deletions(-)
diff --git a/accel/tcg/internal-target.h b
Instead of having a compile-time TARGET_SUPPORTS_MTTCG definition,
have each target set the 'mttcg_supported' field in the TCGCPUOps
structure.
Since so far we only emulate one target architecture at a time,
tcg_init_machine() gets whether MTTCG is supported via the
&first_cpu global.
Signed-off-
qemu_tcg_mttcg_enabled() is specific to 1/ TCG and
2/ system emulation. Move the prototype declaration
to "system/tcg.h", reducing 'mttcg_enabled' variable
scope.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/core/cpu.h | 9 -
include/system/tcg.h | 8
accel/
Multi-threaded TCG only concerns system emulation.
Signed-off-by: Philippe Mathieu-Daudé
---
target/riscv/tcg/tcg-cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index fb903992faa..60a26acc503 100644
--- a/target/r
The arm_aspeed_bletchley timeout takes more than its
current 120s timeout on a debug Rust config:
$ time (cd build/rust; PYTHONPATH=../../python:../../tests/functional
QEMU_TEST_QEMU_BINARY=./qemu-system-arm ./pyvenv/bin/python3
../../tests/functional/test_arm_aspeed_bletchley.py)
TAP version 13
On Thu, Mar 20 2025, Sebastian Ott wrote:
> On Tue, 11 Mar 2025, Cornelia Huck wrote:
>> +++ b/scripts/gen-cpu-sysregs-header.awk
> [...]
>> +BEGIN {
>> +print ""
>> +} END {
>> +print ""
>> +}
>> +
>> +# skip blank lines and comment lines
>> +/^$/ { next }
>> +/^[\t ]*#/ { next }
>> +
>>
The AST2700 CPU, based on the Cortex-A35, is a 64-bit processor, and its DRAM
address space is also 64-bit. To support future AST2700 updates, the source
hash buffer address data type is being updated to 64-bit.
Signed-off-by: Jamin Lin
---
hw/misc/aspeed_hace.c | 8 +---
1 file changed, 5 i
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