From: Matias Ezequiel Vara Larsen
Use virtio_get_config_size() rather than sizeof(struct
virtio_snd_config) for the config_size in the vhost-user-snd frontend.
The frontend shall rely on device features for the size of the device
configuration space. The presence of `controls` in the config space
From: Peter Maydell
In the gicv3_{irq,fiq,irqfiq}_access() functions, there is a check
which downgrades a CP_ACCESS_TRAP_EL3 to CP_ACCESS_TRAP if EL3 is not
AArch64. This has been there since the GIC was first implemented,
but it isn't right: if we are trapping because of SCR.IRQ or SCR.FIQ
then
Add testcases for testing fadump with PSeries and PSeries+KVM
combinations
It tests if fadump is successfully detected and registered in the first
kernel boot. Then crashes the kernel, and verifies whether we have a
/proc/vmcore in the 2nd boot
Also introduce 'wait_for_regex_console_pattern' to c
Implement the register command of "ibm,configure-kernel-dump" RTAS call.
The register just verifies the structure of the fadump memory structure
passed by kernel, and set fadump_registered in spapr state to true.
We also store the passed fadump memory structure, which will later be
used for preser
Kernel expects CPU states/register states in the format mentioned in
"Register Save Area" in PAPR.
The platform (in our case, QEMU) saves each CPU register in the form of
an array of "register entries", the start and end of this array is
signified by "CPUSTRT" and "CPUEND" register entries respect
Overview
=
Implemented Firmware Assisted Dump (fadump) on PSeries machine in QEMU.
Fadump is an alternative dump mechanism to kdump, in which we the firmware
does a memory preserving boot, and the second/crashkernel is booted fresh
like a normal system reset, instead of the crashed kernel
From: Joelle van Dyne
macOS 15.2's Hypervisor.framework exposes SME feature on M4 Macs.
However, QEMU's hvf accelerator code does not properly support it
yet, causing QEMU to fail to start when hvf accelerator is used on
these systems, with the error message:
qemu-aarch64-softmmu: cannot disab
From: Alex Bennée
Signed-off-by: Alex Bennée
Signed-off-by: Peter Maydell
Reviewed-by: Peter Maydell
Message-id: 20250204125009.2281315-9-peter.mayd...@linaro.org
Cc: qemu-sta...@nongnu.org
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
(cherry picked from commit 5dcaea8bcd82972add2
From: Peter Maydell
The CNTVOFF_EL2 offset register should only be applied for accessses
to CNTVCT_EL0 and for the EL1 virtual timer (CNTV_*). We were
incorrectly applying it for the EL2 virtual timer (CNTHV_*).
Cc: qemu-sta...@nongnu.org
Signed-off-by: Peter Maydell
Reviewed-by: Alex Bennée
From: Akihiko Odaki
When an eBPF program cannot be attached, virtio_net_load_ebpf() returns
false, and virtio_net_device_realize() enters the code path to handle
errors because of this, but it causes NULL dereference because no error
is generated.
Change virtio_net_load_ebpf() to return false on
From: Greg Kurz
This was missed at the time.
Fixes: 812b31d3f91 ("configs: rename default-configs to configs and reorganise")
Signed-off-by: Greg Kurz
Reviewed-by: Philippe Mathieu-Daudé
Message-ID: <20250306174113.427116-1-gr...@kaod.org>
Signed-off-by: Thomas Huth
(cherry picked from commit
From: Rodrigo Dias Correa
Instead of migrating the raw tick_offset, goldfish_rtc migrates a
recalculated value based on QEMU_CLOCK_VIRTUAL. As QEMU_CLOCK_VIRTUAL
stands still across a save-and-restore cycle, the guest RTC becomes out
of sync with the host RTC when the VM is restored.
As describe
From: Alex Bennée
When FEAT_SEL2 was implemented the SEL2 timers were missed. This
shows up when building the latest Hafnium with SPMC_AT_EL=2. The
actual implementation utilises the same logic as the rest of the
timers so all we need to do is:
- define the timers and their access functions
From: Eugenio Pérez
This change is used in later commits so we can avoid the removal of the
netclient if it is delayed.
No functional change intended.
Reviewed-by: Si-Wei Liu
Acked-by: Jason Wang
Signed-off-by: Eugenio Pérez
Signed-off-by: Jason Wang
(cherry picked from commit db0d4017f9b9e
From: Peter Maydell
Currently we call icount_start_warp_timer() from timerlist_rearm().
This produces incorrect behaviour, because timerlist_rearm() is
called, for instance, when a timer callback modifies its timer. We
cannot decide here to warp the timer forwards to the next timer
deadline mere
From: Nicholas Piggin
The commit to fix the OCC common area sensor mappings didn't update the
register offsets to match.
Before this change, skiboot reports:
[0.347100086,3] OCC: Chip 0 sensor data invalid
Afterward, there is no error and the sensor_groups directory appears
under /sys/firm
From: Eugenio Pérez
Commit a0d7215e33 ("vhost-vdpa: do not cleanup the vdpa/vhost-net
structures if peer nic is present") effectively delayed the backend
cleanup, allowing the frontend or the guest to access it resources as
long as the frontend is still visible to the guest.
However it does not
From: Kevin Wolf
Block drivers assume in their .bdrv_open() implementation that their
state in bs->opaque has been zeroed; it is initially allocated with
g_malloc0() in bdrv_open_driver().
bdrv_snapshot_goto() needs to make sure that it is zeroed again before
calling drv->bdrv_open() to avoid th
From: Bibo Mao
Write operation with R32 (orig_a0) and R34 (CSR_BADV) is discarded on
gdbstub implementation for LoongArch system. And return value should
be register size rather than 0, since it is used to calculate offset of
next register such as R33 (PC) in function handle_write_all_regs().
Cc
From: Sairaj Kodilkar
Interrupt passthrough is determine by the bits 191,190,187-184.
These bits are part of the 3rd quad word (i.e. index 2) in DTE. Hence
replace dte[3] by dte[2].
Fixes: b44159fe0 ("x86_iommu/amd: Add interrupt remap support when VAPIC is not
enabled")
Signed-off-by: Sairaj K
From: Peter Maydell
The access pseudocode for the CNTPS_TVAL_EL1, CNTPS_CTL_EL1 and
CNTPS_CVAL_EL1 secure timer registers says that they are UNDEFINED
from EL2 or NS EL1. We incorrectly return CP_ACCESS_TRAP from the
access function in these cases, which means that we report the wrong
syndrome v
From: Alex Bennée
Signed-off-by: Alex Bennée
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
Message-id: 20250204125009.2281315-10-peter.mayd...@linaro.org
Cc: qemu-sta...@nongnu.org
Signed-off-by: Peter Maydell
(cherry picked from commit 9a9d9e82093efa22e3e2bdaac0f24c823f8786f7)
Sign
The following patches are queued for QEMU stable v9.2.3:
https://gitlab.com/qemu-project/qemu/-/commits/staging-9.2
Patch freeze is 2025-03-24, and the release is planned for 2025-03-26:
https://wiki.qemu.org/Planning/9.2
Please respond here or CC qemu-sta...@nongnu.org on any additional pa
We already call env_archcpu() multiple times within the
exception_return helper function, and we're about to want to
add another use of the ARMCPU pointer. Add a local variable
cpu so we can call env_archcpu() just once.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm
From: Peter Maydell
Our LDRD implementation is wrong in two respects:
* if the address is 4-aligned and the load crosses a page boundary
and the second load faults and the first load was to the
base register (as in cases like "ldrd r2, r3, [r2]", then we
must not update the base regist
From: Peter Maydell
Our STRD implementation doesn't correctly implement the requirement:
* if the address is 8-aligned the access must be a 64-bit
single-copy atomic access, not two 32-bit accesses
Rewrite the handling of STRD to use a single tcg_gen_qemu_st_i64()
of a value produced by conc
From: Thomas Huth
QEMU currently crashes when you try to inspect the properties of the
microvm machine:
$ echo '{ "execute": "qmp_capabilities" }
{ "execute": "qom-list-properties","arguments":
{ "typename": "microvm-machine"}}' | \
./qemu-system-x86_64 -qmp stdio
{"QMP"
From: Daniel Henrique Barboza
In the RISC-V privileged ISA section 3.1.15 table 15, it is determined
that a debug exception that is triggered from a load/store has a higher
priority than a possible fault that this access might trigger.
This is not the case ATM as shown in [1]. Adding a breakpoin
From: Patrick Venture
The reg isn't validated to be a possible register before
it's dereferenced for one case. The mmio space registered
for the gpio device is 4KiB but there aren't that many
registers in the struct.
Cc: qemu-sta...@nongnu.org
Fixes: 526dbbe0874 ("hw/gpio: Add GPIO model for Nu
From: Joelle van Dyne
In the syndrome value for a data abort, bit 21 is SSE, which is
set to indicate that the abort was on a sign-extending load. When
we handle the data abort from the guest via address_space_read(),
we forgot to handle this and so would return the wrong value if
the guest did a
From: Peter Maydell
The code for WFI/WFE trapping has several errors:
* it wasn't using arm_sctlr(), so it would look at SCTLR_EL1
even if the CPU was in the EL2&0 translation regime
* it was raising UNDEF, not Monitor Trap, for traps to
AArch32 EL3 because of SCR.{TWE,TWI}
* it was not
From: Peter Maydell
When we are calculating timer deadlines, the correct definition of
whether or not to apply an offset to the physical count is described
in the Arm ARM DDI4087 rev L.a section D12.2.4.1. This is different
from when the offset should be applied for a direct read of the
counter
From: Stefano Garzarella
The function `vhost_dev_init()` expects the `struct vhost_dev`
(passed as a parameter) to be fully initialized. This is important
because some parts of the code check whether `vhost_dev->config_ops`
is NULL to determine if it has been set (e.g. later via
`vhost_dev_set_co
From: Max Chou
In prop_vlen_set function, there is an incorrect comparison between
vlen(bit) and vlenb(byte).
This will cause unexpected error when user applies the `vlen=1024` cpu
option with a vendor predefined cpu type that the default vlen is
1024(vlenb=128).
Fixes: 4f6d036ccc ("target/riscv
From: Peter Maydell
There are not many traps in AArch32 which should trap to Monitor
mode, but these trap bits should trap not just lower ELs to Monitor
mode but also the non-Monitor modes running at EL3 (i.e. Secure
System, Secure Undef, etc).
We get this wrong because the relevant access func
From: Konstantin Shkolnyy
VDPA didn't work on a big-endian machine due to missing/incorrect
CPU<->LE data format conversions.
Signed-off-by: Konstantin Shkolnyy
Message-Id: <20250212164923.1971538-1-k...@linux.ibm.com>
Fixes: 10857ec0ad ("vhost: Add VhostShadowVirtqueue")
Acked-by: Eugenio Pére
From: Paolo Bonzini
It is possible to start QEMU with a confidential-guest-support object
even in TCG mode. While there is already a check in qemu_machine_creation_done:
if (machine->cgs && !machine->cgs->ready) {
error_setg(errp, "accelerator does not support confidential guest %s"
From: Alexander Graf
When we return a response packet from NSM, we need to indicate its
length according to the content of the response. Prior to this patch, we
returned the length of the source buffer, which may confuse guest code
that relies on the response size.
Fix it by returning the respon
From: Max Chou
According to the Vector Reduction Operations section in the RISC-V "V"
Vector Extension spec,
"If vl=0, no operation is performed and the destination register is not
updated."
The vd should be updated when vl is larger than 0.
Fixes: fe5c9ab1fc ("target/riscv: vector single-width
From: Sairaj Kodilkar
AMD IOMMU provides the base address of control registers through
IVRS table and PCI capability. Since this base address is of 64 bit,
use 32 bits mask (instead of 16 bits) to set BAR low and high.
Fixes: d29a09ca68 ("hw/i386: Introduce AMD IOMMU")
Signed-off-by: Sairaj Kodi
From: Peter Maydell
In system register access pseudocode the common pattern for
AArch32 registers with access traps to EL3 is:
at EL1 and EL2:
if HaveEL(EL3) && !ELUsingAArch32(EL3) && (SCR_EL3.TERR == 1) then
AArch64.AArch32SystemAccessTrap(EL3, 0x03);
elsif HaveEL(EL3) && ELUsingAArch
From: Thomas Huth
QEMU currently crashes when you try to inspect the machines based on
TYPE_PC_MACHINE for their properties:
$ echo '{ "execute": "qmp_capabilities" }
{ "execute": "qom-list-properties","arguments":
{ "typename": "pc-q35-10.0-machine"}}' \
| ./q
From: Peter Maydell
The pseudocode for the accessors for the LOR sysregs says they
are UNDEFINED if SCR_EL3.NS is 0. We were reporting the wrong
syndrome value here; use CP_ACCESS_TRAP_UNCATEGORIZED.
Cc: qemu-sta...@nongnu.org
Fixes: 2d7137c10faf ("target/arm: Implement the ARMv8.1-LOR extension
From: Peter Maydell
The pseudocode for AT S1E2R and AT S1E2W says that they should be
UNDEFINED if executed at EL3 when EL2 is not enabled. We were
incorrectly using CP_ACCESS_TRAP and reporting the wrong exception
syndrome as a result. Use CP_ACCESS_TRAP_UNCATEGORIZED.
Cc: qemu-sta...@nongnu.or
On Fri, Mar 14, 2025 at 8:47 PM Jörg Rödel wrote:
>
> On Fri, Mar 14, 2025 at 03:08:43PM +0100, Gerd Hoffman wrote:
> > If your input firmware image already is an IGVM (say coconut), what is
> > supposed to happen?
>
> The COCONUT igvmbuilder has the ability to take another IGVM file as
> input an
:13 +0800)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20250314-1
for you to fetch changes up to a019e15edfd62beae1e2f6adc0fa7415ba20b14c:
meson.build: Set RUST_BACKTRACE for all tests (2025-03-14
On 3/14/25 08:24, Philippe Mathieu-Daudé wrote:
On 14/3/25 08:41, Nicholas Piggin wrote:
Debugger-driven invalid memory accesses are not guest errors, so should
not cause these error logs.
Debuggers can access memory wildly, including access to addresses not
specified by the user (e.g., gdb it
On 3/14/25 06:35, Anthony PERARD wrote:
On Thu, Mar 13, 2025 at 09:38:58AM -0700, Pierrick Bouvier wrote:
Those functions are used by system/physmem.c, and are called only if
xen is enabled (which happens only if CONFIG_XEN is not set).
You mean, 's/is not set/is set/'?
Right, I'll update th
On 3/14/25 14:14, Alex Bennée wrote:
Pierrick Bouvier writes:
On 3/14/25 08:38, Paolo Bonzini wrote:
-gsplit-dwarf is reported to produce broken binaries on Windows.
The linker produces warnings but exits successfully:
/usr/lib/gcc/x86_64-w64-mingw32/14.2.0/../../../../x86_64-w64-mingw32/bin/
Needed so compilation units including it can be common.
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
include/exec/memory-internal.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/include/exec/memory-internal.h b/include/exec/memory-internal.h
index 100c1237ac2..b729f
On 3/14/25 11:36, Pierrick Bouvier wrote:
On 3/14/25 11:13, Richard Henderson wrote:
On 3/13/25 14:00, Pierrick Bouvier wrote:
diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
index 89fe8aedaa..7b9964fe7e 100644
--- a/include/hw/intc/armv7m_nvic.h
+++ b/include/hw/intc
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
include/exec/ram_addr.h | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/include/exec/ram_addr.h b/include/exec/ram_addr.h
index f5d574261a3..92e8708af76 100644
--- a/include/exec/ram_addr.h
+++ b/inclu
Needed so compilation units including it can be common.
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
include/exec/ram_addr.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/exec/ram_addr.h b/include/exec/ram_addr.h
index e4c28fbec9b..f5d574261
On 3/14/25 13:59, Richard Henderson wrote:
On 3/14/25 13:34, Pierrick Bouvier wrote:
On 3/14/25 13:03, Richard Henderson wrote:
I'm not quite sure what you're arguing for here.
A build-time error is vastly preferable to a run-time error.
Even though this specific patch is safe (code calling
From: Steve Sistare
During normal migration, new QEMU creates and initializes memory regions,
then loads the preserved contents of the region from vmstate.
During CPR, memory regions are preserved in place, then the realize
method initializes the regions contents, losing the old contents. To
fi
On 14.03.25 08:41, Nicholas Piggin wrote:
This adds .debug=1 attribute for GDB's phys mem access mode, adds
memory transaction error handling for it so it reports cannot access
memory instead of silent success, and silences warning logs for
invalid memory access coming from the debugger.
Nothin
On 3/14/25 14:14, Alex Bennée wrote:
Pierrick Bouvier writes:
On 3/14/25 08:38, Paolo Bonzini wrote:
-gsplit-dwarf is reported to produce broken binaries on Windows.
The linker produces warnings but exits successfully:
/usr/lib/gcc/x86_64-w64-mingw32/14.2.0/../../../../x86_64-w64-mingw32/bin/
On 3/14/25 00:41, Nicholas Piggin wrote:
Add an accessor for gdb physical memory access mode which sets the
the .debug attribute for the MemTxAttribute, and also returns success
to the caller.
GDB with PhyMemMode will now report failure from memory accesses outside
valid system memory addresses,
Pierrick Bouvier writes:
> On 3/14/25 08:38, Paolo Bonzini wrote:
>> -gsplit-dwarf is reported to produce broken binaries on Windows.
>> The linker produces warnings but exits successfully:
>> /usr/lib/gcc/x86_64-w64-mingw32/14.2.0/../../../../x86_64-w64-mingw32/bin/ld:
>> qga/qemu-ga.exe:/4: sec
On 3/14/25 13:34, Pierrick Bouvier wrote:
On 3/14/25 13:03, Richard Henderson wrote:
I'm not quite sure what you're arguing for here.
A build-time error is vastly preferable to a run-time error.
Even though this specific patch is safe (code calling those functions should be under
system anyw
In linux-user/arm/cpu_loop.c we define a full set of get/put
macros for both code and data (since the endianness handling
is different between the two). However the only one we actually
use is get_user_code_u32(). Remove the rest.
We leave a comment noting how data-side accesses should be handled
On 3/13/25 20:31, Yao Zi wrote:
Clang on LoongArch only accepts fp register names in the dollar-prefixed
form, while GCC allows omitting the dollar. Change registers in ASM
clobbers to the dollar-prefixed form to make user emulators buildable
with Clang on loongarch64. No functional change invovl
On Fri, 14 Mar 2025, Markus Armbruster wrote:
> The Error ** argument must be NULL, &error_abort, &error_fatal, or a
> pointer to a variable containing NULL. Passing an argument of the
> latter kind twice without clearing it in between is wrong: if the
> first call sets an error, it no longer poin
The variable holding default env is not supposed to be written.
Signed-off-by: BALATON Zoltan
---
hw/ppc/amigaone.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ppc/amigaone.c b/hw/ppc/amigaone.c
index 5d787c3059..e9407a51b5 100644
--- a/hw/ppc/amigaone.c
+++ b/hw/ppc/a
Coverity reported that return value of blk_pwrite() maybe should not
be ignored. We can't do much if this happens other than report an
error but let's do that to silence this report.
Resolves: Coverity CID 1593725
Signed-off-by: BALATON Zoltan
---
hw/ppc/amigaone.c | 14 --
1 file ch
On 3/14/25 08:38, Paolo Bonzini wrote:
-gsplit-dwarf is reported to produce broken binaries on Windows.
The linker produces warnings but exits successfully:
/usr/lib/gcc/x86_64-w64-mingw32/14.2.0/../../../../x86_64-w64-mingw32/bin/ld:
qga/qemu-ga.exe:/4: section below image base
/usr/lib/gcc/x86
On 2025/3/14 下午5:11, Markus Armbruster wrote:
Bibo Mao writes:
There is NULL pointer checking function error_propagate() already,
it is not necessary to add checking for function parameter. Here remove
NULL pointer checking with function parameter.
Signed-off-by: Bibo Mao
---
hw/loongar
Thank you Ben. I appreciate you testing CPR and shaking out the bugs.
I will study these and propose patches.
My initial reaction to the pidfile issue is that the orchestration layer must
pass a different filename when starting the destination qemu instance. When
using live update without conta
On Fri, Mar 07, 2025 at 11:55:11AM -0800, Wei Liu wrote:
> Hi,
>
> Microsoft's Linux Systems Group developed a Linux driver for the Microsoft
> Hypervisor (MSHV for short). The driver is being upstreamed. The first
> supported VMM is Cloud Hypervisor. We want to add QEMU as the second supported
>
On Fri, Mar 14, 2025 at 10:33:08AM -0700, Pierrick Bouvier wrote:
> Hi,
>
> one patch is missing review:
> [PATCH v5 12/17] hw/xen: add stubs for various functions.
My "Acked-by" wasn't enough? Feel free try change it to "Reviewed-by"
instead.
Cheers,
--
Anthony Perard | Vates XCP-ng Develope
Deriving from TYPE_SYS_BUS_DEVICE fixes the SoC object to be reset upon machine
reset. It also makes the SoC implementation not user-creatable which can trigger
the following crash:
$ ./qemu-system-aarch64 -M virt -device fsl-imx8mp
**
ERROR:../../devel/qemu/tcg/tcg.c:1006:tcg_register_thre
On 3/14/25 11:34, Anthony PERARD wrote:
On Fri, Mar 14, 2025 at 10:33:08AM -0700, Pierrick Bouvier wrote:
Hi,
one patch is missing review:
[PATCH v5 12/17] hw/xen: add stubs for various functions.
My "Acked-by" wasn't enough? Feel free try change it to "Reviewed-by"
instead.
Those are diff
On 3/14/25 11:13, Richard Henderson wrote:
On 3/13/25 14:00, Pierrick Bouvier wrote:
diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
index 89fe8aedaa..7b9964fe7e 100644
--- a/include/hw/intc/armv7m_nvic.h
+++ b/include/hw/intc/armv7m_nvic.h
@@ -189,21 +189,7 @@ int arm
Hello,
While testing CPR transfer I encountered two issues. The first is that the
transfer fails when running with pidfiles due to the destination qemu process
attempting to create the pidfile while it is still locked by the source
process. The second is that the transfer fails when running wit
Previous commit changed files relying transitively on it.
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
include/exec/exec-all.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index dd5c40f2233..19b0eda44a7 100644
--- a/i
The SoC has three SPI controllers, not four. Remove the extra define of an SPI
IRQ.
Fixes: 06908a84f036 "hw/arm/fsl-imx8mp: Add SPI controllers"
Signed-off-by: Bernhard Beschow
---
include/hw/arm/fsl-imx8mp.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/include/hw/arm/fsl-imx8mp.h b/includ
On 3/13/25 14:00, Pierrick Bouvier wrote:
diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
index 89fe8aedaa..7b9964fe7e 100644
--- a/include/hw/intc/armv7m_nvic.h
+++ b/include/hw/intc/armv7m_nvic.h
@@ -189,21 +189,7 @@ int armv7m_nvic_raw_execution_priority(NVICState *s
This function is used by system/physmem.c will be turn into common code
in next commit.
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
include/system/kvm.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/include/system/kvm.h b/include/system/kvm.h
i
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
system/meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/system/meson.build b/system/meson.build
index eec07a94513..bd82ef132e7 100644
--- a/system/meson.build
+++ b/system/meson.build
@@ -3,7 +3,6 @
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
system/ioport.c| 1 -
system/meson.build | 2 +-
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/system/ioport.c b/system/ioport.c
index 55c2a752396..89daae9d602 100644
--- a/system/ioport.c
+++ b/system/ioport.
Hi,
one patch is missing review:
[PATCH v5 12/17] hw/xen: add stubs for various functions.
Regards,
Pierrick
On 3/14/25 10:31, Pierrick Bouvier wrote:
The main goal of this series is to be able to call any memory ld/st function
from code that is *not* target dependent. As a positive side effec
Defining functions allows to use them from common code, by not depending
on TARGET_BIG_ENDIAN.
Remove previous macros from exec/cpu-all.h.
By moving them out of cpu-all.h, we'll be able to break dependency on
cpu.h for memory related functions coming in next commits.
Reviewed-by: Richard Henderson
On 03.03.25 17:33, Juraj Marcin wrote:
The default idle period for TCP connection could be even 2 hours.
However, in some cases, the application needs to be aware of a
connection issue much sooner.
This is the case, for example, for postcopy live migration. If there is
no traffic from the migrat
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
system/memory.c| 17 +
system/meson.build | 2 +-
2 files changed, 6 insertions(+), 13 deletions(-)
diff --git a/system/memory.c b/system/memory.c
index 4c829793a0a..eddd21a6cdb 100644
--- a/system/memory.c
Those symbols are used by system/physmem.c, and are called only if
xen_enabled() (which happens only if CONFIG_XEN is set and xen is
available).
So we can crash the stubs in case those are called, as they are linked
only when CONFIG_XEN is not set.
Acked-by: Richard Henderson
Acked-by: Anthony P
we'll use it in system/memory.c.
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
include/exec/memory.h | 18 --
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/include/exec/memory.h b/include/exec/memory.h
index 069021ac3ff..70177304a92 100644
-
Will allow to make system/memory.c common later.
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
include/exec/memory.h | 16
1 file changed, 4 insertions(+), 12 deletions(-)
diff --git a/include/exec/memory.h b/include/exec/memory.h
index da21e9150b5..069021
Only system/physmem.c and system/memory.c use those functions, so we can
move then to internal header.
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
include/exec/memory-internal.h | 19 +++
include/exec/memory.h | 18 --
2 files chan
They are now accessible through exec/memory.h instead, and we make sure
all variants are available for common or target dependent code.
Move stl_phys_notdirty function as well.
Cached endianness agnostic version rely on st/ld*_p, which is available
through tswap.h.
Reviewed-by: Richard Henderson
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
include/exec/tswap.h | 11 ++-
cpu-target.c | 1 +
2 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/include/exec/tswap.h b/include/exec/tswap.h
index ecd4faef015..2683da0adb7 100644
--- a/include/ex
On Fri, Mar 07, 2025 at 09:13:39AM +0800, Bibo Mao wrote:
> Float register name f0 - f31 is not recognized with clang compiler
> with LoongArch64 target, its name should be $f0 - $f31. It is ok
> for both gcc and clang compiler.
Sorry I didn't search the list carefully and sent a similar patch[1].
Kernel expects CPU states/register states in the format mentioned in
"Register Save Area" in PAPR.
The platform (in our case, QEMU) saves each CPU register in the form of
an array of "register entries", the start and end of this array is
signified by "CPUSTRT" and "CPUEND" register entries respect
On 04.03.25 12:17, Raman Dzehtsiar wrote:
This patch extends the blockdev-backup QMP command to allow users to specify
how to behave when IO errors occur during copy-before-write operations.
Previously, the behavior was fixed and could not be controlled by the user.
The new 'on-cbw-error' option
On 3/14/25 17:54, Daniel P. Berrangé wrote:
Same remark as on the other patch: can we have a comment
explaining why we disable this on Windows, please, ideally
with a URL of a bug report against the toolchain ?
Two likely candidates open a long time
https://gcc.gnu.org/bugzilla/show_bug
On Fri, Mar 14, 2025 at 04:44:01PM +, Peter Maydell wrote:
> On Fri, 14 Mar 2025 at 15:39, Paolo Bonzini wrote:
> >
> > -gsplit-dwarf is reported to produce broken binaries on Windows.
> > The linker produces warnings but exits successfully:
> >
> > /usr/lib/gcc/x86_64-w64-mingw32/14.2.0/../..
On Fri, 14 Mar 2025 at 15:39, Paolo Bonzini wrote:
>
> -gsplit-dwarf is reported to produce broken binaries on Windows.
> The linker produces warnings but exits successfully:
>
> /usr/lib/gcc/x86_64-w64-mingw32/14.2.0/../../../../x86_64-w64-mingw32/bin/ld:
> qga/qemu-ga.exe:/4: section below image
On 3/13/25 03:39, Philippe Mathieu-Daudé wrote:
--- /dev/null
+++ b/common-user/watchpoint-stub.c
@@ -0,0 +1,28 @@
+/*
+ * CPU watchpoint stubs
+ *
+ * Copyright (c) 2003 Fabrice Bellard
+ * SPDX-License-Identifier: LGPL-2.1-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "hw/core/cpu.h"
+
+in
On Fri, Mar 14, 2025 at 02:44:35PM +, Simon Glass wrote:
> Hi Tom,
>
> On Fri, 7 Mar 2025 at 14:23, Tom Rini wrote:
> >
> > On Thu, Mar 06, 2025 at 09:03:27AM -0700, Simon Glass wrote:
> >
> > > U-Boot can start and boot an OS in both qemu-x86 and qemu-x86_64 but it
> > > is not perfect.
> >
Jonathan Cameron wrote:
> On Wed, 5 Mar 2025 18:35:40 +0800
> Yuquan Wang wrote:
>
> > >
> > > On Tue, 4 Mar 2025 14:22:48 +0800
> > > Yuquan Wang wrote:
> > >
> > > > >
> > > > > On Thu, Feb 20, 2025 at 04:12:13PM +, Jonathan Cameron wrote:
> > > > > > On Mon, 17 Feb 2025 19:20:39
-gsplit-dwarf is reported to produce broken binaries on Windows.
The linker produces warnings but exits successfully:
/usr/lib/gcc/x86_64-w64-mingw32/14.2.0/../../../../x86_64-w64-mingw32/bin/ld:
qga/qemu-ga.exe:/4: section below image base
/usr/lib/gcc/x86_64-w64-mingw32/14.2.0/../../../../x86_64
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