Report hashing capability so that virtio-net can deliver the correct
capability information to the guest.
Signed-off-by: Akihiko Odaki
---
include/net/net.h | 3 +++
net/net.c | 9 +
net/vhost-vdpa.c | 28
3 files changed, 40 insertions(+)
diff --
This is necessary to offload hashing to tap.
Signed-off-by: Akihiko Odaki
---
hw/net/virtio-net.c | 77 -
1 file changed, 64 insertions(+), 13 deletions(-)
diff --git a/hw/net/virtio-net.c b/hw/net/virtio-net.c
index b0f2ad78cb39..e125478ae834
This allows offloading virtio-net hashing to tap on Linux.
Signed-off-by: Akihiko Odaki
---
net/tap-linux.h | 1 +
net/tap_int.h | 1 +
net/tap-bsd.c | 5 +
net/tap-linux.c | 13 +
net/tap-solaris.c | 5 +
net/tap-stub.c| 5 +
net/tap.c | 8 +
This adds set_vnet_hash() to configure virtio hashing and implements it
for Linux's tap. vDPA will have an empty function as configuring virtio
hashing is done with the load().
Signed-off-by: Akihiko Odaki
---
include/net/net.h | 17 +
net/tap-linux.h | 1 +
net/tap_int.h
This is necessary to offload hashing to tap.
Signed-off-by: Akihiko Odaki
---
hw/net/virtio-net.c | 18 --
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/hw/net/virtio-net.c b/hw/net/virtio-net.c
index e125478ae834..edfc76a5308e 100644
--- a/hw/net/virtio-net.c
++
DEFINE_PROP_ON_OFF_AUTO_BIT64() corresponds to DEFINE_PROP_ON_OFF_AUTO()
as DEFINE_PROP_BIT64() corresponds to DEFINE_PROP_BOOL(). The difference
is that DEFINE_PROP_ON_OFF_AUTO_BIT64() exposes OnOffAuto instead of
bool.
Signed-off-by: Akihiko Odaki
---
include/hw/qdev-properties.h | 18
It is no longer used.
Signed-off-by: Akihiko Odaki
---
net/vhost-vdpa.c | 8
1 file changed, 8 deletions(-)
diff --git a/net/vhost-vdpa.c b/net/vhost-vdpa.c
index 0e9f4482ce7a..d35348b1e742 100644
--- a/net/vhost-vdpa.c
+++ b/net/vhost-vdpa.c
@@ -238,12 +238,6 @@ static void vhost_vdpa
I'm proposing to add a feature to offload virtio-net RSS/hash report to
Linux. This series contain patches to utilize the proposed Linux feature.
The patches for Linux are available at:
https://lore.kernel.org/r/20250307-rss-v9-0-df7662402...@daynix.com/
This work was presented at LPC 2024:
https:
John Snow writes:
> This also creates the `qapi-qsd-index` and `qapi-qga-index` QMP indices.
>
> Signed-off-by: John Snow
[...]
> diff --git a/qga/qapi-schema.json b/qga/qapi-schema.json
> index 995594aaf43..35ec0e7db31 100644
> --- a/qga/qapi-schema.json
> +++ b/qga/qapi-schema.json
> @@ -3,6
John Snow writes:
> This patch does three things:
>
> 1. Record the current namespace context in pending_xrefs so it can be
>used for link resolution later,
> 2. Pass that recorded namespace context to find_obj() when resolving a
>reference, and
> 3. Wildly and completely rewrite find_obj
On 12/03/2025 13:54, Yi Liu wrote:
> Caution: External email. Do not open attachments or click links, unless
> this email comes from a known sender and you know the content is safe.
>
>
> On 2025/3/12 18:03, Philippe Mathieu-Daudé wrote:
>> Hi Markus,
>>
>> (Cc'ing Yi, Clément and Zhenzhong fo
John Snow writes:
> Akin to the :module: override option, the :namespace: options allows you
> to forcibly override the contextual namespace associatied with a
> definition.
>
> We don't necessarily actually need this, but I felt compelled to stick
> close to how the Python domain works that offe
For the s390x target, it's possible to build the QEMU binary without
CONFIG_VIRTIO_PCI and only have the virtio-mem device via the ccw
transport. In that case, QEMU currently fails to link correctly:
/usr/bin/ld: libqemu-s390x-softmmu.a.p/hw_s390x_s390-virtio-ccw.c.o: in
function `s390_machine_d
Maps following unimplemented devices in SoC memory
- dpmcu
- iomem
- iomem0
- iomem1
- ltpi
Iomem, Iomem0 and Iomem1 include unimplemented controllers in the
memory ranges 0x0 - 0x100, 0x12000 - 0x12100 and
0x1400 - 0x14100.
For instance:
- USB hub at 0x1201
- eSPI at 0x14
AST2700 SSP(Secondary Service Processor) is a Cortex-M4 coprocessor
The patch adds support for SSP with following update:
- Introduce Aspeed27x0SSPSoCState structure in aspeed_soc.h
- Define memory map and IRQ map for AST27x0 A0 SSP SoC
- Implement initialization and realization functions
- Add su
bibo mao writes:
> Ah, It is a pity and bad news that I contribute almost 30% of it :(
> LoongArch system actually needs more people participation and I need notice
> this also. It should happens in future again in LoongArch subsystem.
>
> Any reviewing comments is welcome and I will slow down f
On 13/03/2025 03.34, Stefan Hajnoczi wrote:
On Tue, Mar 11, 2025 at 8:59 PM Nicholas Piggin wrote:
The following changes since commit 825b96dbcee23d134b691fc75618b59c5f53da32:
Merge tag 'migration-20250310-pull-request' of
https://gitlab.com/farosas/qemu into staging (2025-03-11 09:32:07
Add namespaces, turn on QGA and QSD.
John Snow (11):
docs/qapi_domain: isolate TYPE_CHECKING imports
docs/qapi-domain: always store fully qualified name in signode
docs/qapi_domain: add namespace support to FQN
docs/qapi-domain: add :namespace: override option
docs/qapi-domain: add qapi:
The AST2700 SSP (Secondary Service Processor) is a Cortex-M4 coprocessor.
This patch adds support for A1 SSP with the following updates:
- Defined IRQ maps for AST27x0 A1 SSP SoC
- Implemented initialization functions
The IRQ mapping is similar to AST2700 CA35 SoC, featuring a two-level
interrupt
- Define new types for ast2700tsp INTC and INTCIO
- Add register definitions for TSP INTC and INTCIO
- Implement write handlers for TSP INTC and INTCIO
- Register new types in aspeed_intc_register_types
The design of the TSP INTC and INTCIO controllers is similar to
AST2700, with the following dif
Introduce a new functional test for AST2700 multi-SoCs.
The test includes booting ast2700 with bmc image on
ca35 cores and booting ssp/tsp firmware on cm4 cores.
Assets for SDK and SSP/TSP images are downloaded from
AspeedTech-BMC's OpenBmc release page.
Signed-off-by: Steven Lee
Change-Id: I9580
Corrected the hexadecimal notation for several device addresses in the
aspeed_soc_ast2700_memmap array by changing the uppercase 'X' to
lowercase 'x'.
Signed-off-by: Steven Lee
Change-Id: I45426e18ea8e68d7ccdf9b60c4ea235c4da33cc3
---
hw/arm/aspeed_ast27x0.c | 28 ++--
1 f
On 13/03/2025 03.22, Stefan Hajnoczi wrote:
Hi,
CI jobs that run test_arm_orangepi.py are failing:
https://gitlab.com/qemu-project/qemu/-/jobs/9390048284#L1138
Please consider how to resolve this so the CI job passes again. If you
are in contact with the archive.netbsd.org administrators, maybe
The AST2700 TSP (Tertiary Service Processor) is a Cortex-M4 coprocessor.
This patch adds support for A1 TSP with the following updates:
- Defined IRQ maps for AST27x0 A1 TSP SoC
- Implemented initialization functions
The IRQ mapping is similar to AST2700 CA35 SoC, featuring a two-level
interrupt
- Added new machine type `ast2700fc-a1` with full core support.
- Defined `Ast2700a1FCState` structure for the new machine type.
- Implemented initialization functions for CA35, SSP, and TSP components.
- Updated `ast2700fc_types` to include the new machine type.
- Set machine class properties for
- Updated Aspeed family boards list to include `ast2700fc`.
- Added boot instructions for the `ast2700fc` machine.
- Detailed the configuration and loading of firmware for the
Cortex-A35 and Cortex-M4 processors.
Signed-off-by: Steven Lee
Change-Id: I48d90589d29ae6bb70a172e1798f18c0c38e6e22
---
- Define new types for ast2700ssp INTC and INTCIO
- Add register definitions for SSP INTC and INTCIO
- Implement write handlers for SSP INTC and INTCIO
- Register new types in aspeed_intc_register_types
The design of the SSP INTC and INTCIO controllers is similar to
AST2700, with the following dif
This patch series introduces full core support for the AST27x0 SoC, along with
necessary updates to the ASPEED AST27x0 SOC.
The AST27x0 SoC is a new family of ASPEED SoCs featuring 4 Cortex-A35 cores and
2 Cortex-M4 cores.
v1:
- Map unimplemented devices in SoC memory
- Intruduce AST2700 CM4
This patchset adds DRM native context support to VirtIO-GPU on Qemu.
Contarary to Virgl and Venus contexts that mediates high level GFX APIs,
DRM native context [1] mediates lower level kernel driver UAPI, which
reflects in a less CPU overhead and less/simpler code needed to support it.
DRM contex
Add a new directive that marks the beginning of a QAPI "namespace", for
example; "QMP", "QGA" or "QSD". This directive will associate all
subsequent QAPI directives in a document with the specified
namespace. This does not change the visual display of any of the
definitions or index entries, but do
On 3/12/25 15:50, Harsh Prateek Bora wrote:
On 3/12/25 15:39, Philippe Mathieu-Daudé wrote:
On 12/3/25 06:58, Harsh Prateek Bora wrote:
When POWER10 CPU was made as default, we missed keeping POWER9 as
default for older pseries releases (pre-10.0) at that time.
This caused breakge in defau
Before we enable the QGA and QSD namespaces, we need to disambiguate
some of the references that would become ambiguous as a result!
Signed-off-by: John Snow
---
docs/devel/qapi-domain.rst | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/docs/devel/qapi-domain.r
This patch adds a namespace component to the "Fully Qualified Name", in
the form of "domain:module.name". As there are no namespace directives
or options yet, this component will simply be empty as of this patch.
Signed-off-by: John Snow
---
docs/sphinx/qapi_domain.py | 35 ++
Akin to the :module: override option, the :namespace: options allows you
to forcibly override the contextual namespace associatied with a
definition.
We don't necessarily actually need this, but I felt compelled to stick
close to how the Python domain works that offers context overrides.
As of th
This patch does three things:
1. Record the current namespace context in pending_xrefs so it can be
used for link resolution later,
2. Pass that recorded namespace context to find_obj() when resolving a
reference, and
3. Wildly and completely rewrite find_obj().
cross-reference support is e
This also creates the `qapi-qsd-index` and `qapi-qga-index` QMP indices.
Signed-off-by: John Snow
---
docs/conf.py | 2 ++
docs/interop/qemu-ga-ref.rst | 2 ++
docs/interop/qemu-storage-daemon-qmp-ref.rst | 2 ++
qga/qapi-schema.json
Currently, only the definition name is stored in the tree metadata; but
the node property is confusingly called "fullname". Rectify this by
always storing the FQN in the tree metadata.
... While we're here, re-organize the code in preparation for namespace
support to make it a bit easier to add ad
This also creates the qapi-qmp-index.html index and cross-reference
target.
Signed-off-by: John Snow
---
docs/conf.py | 4 +++-
docs/interop/qemu-qmp-ref.rst | 1 +
qapi/qapi-schema.json | 2 +-
3 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/docs/conf.py
Add a :namespace: option to the qapi-doc directive, which inserts a
qapi:namespace directive into the start of the generated document. This,
in turn, associates all auto-generated definitions by this directive
with the specified namespace.
The source info for these generated lines are credited to
When using the annotations feature, type hints do not need to be
imported at runtime, only at type check time. Move type-check-only
imports into a conditional to reduce the number of imports needed at
runtime.
Signed-off-by: John Snow
---
docs/sphinx/qapi_domain.py | 18 +++---
1 fil
Semihosting is not enabled for user-only.
Avoid the test for that case.
Signed-off-by: Richard Henderson
---
target/xtensa/translate.c | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index 4f02cefde3..d13d058
On Sat, Mar 08, 2025 at 06:16:17PM +0800, zoudongjie wrote:
> From: Zhu Yangyang
>
> The bdrv_drained_begin() function is a blocking function. In scenarios where
> network storage
> is used and network links fail, it may block for a long time.
> Therefore, we add a timeout parameter to control t
We were hiding a number of declarations from user-only,
although it hurts nothing to allow them.
Signed-off-by: Richard Henderson
---
include/hw/core/cpu.h | 10 --
1 file changed, 10 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 2fdb115b19..59394212fa 10
Poison CONFIG_USER_ONLY and CONFIG_SOFTMMU unless
the compilation unit is in specific_ss, libuser_ss,
or libsystem_ss. This is intended to prevent files
being incorrectly added to common_ss.
Remove #ifndef CONFIG_USER_ONLY / #error / #endif blocks.
All they do is trigger the poison error.
Signed
We assert that env immediately follows CPUState in cpu-all.h.
Change the offsetof expressions to be based on CPUState instead
of ArchCPU.
Signed-off-by: Richard Henderson
---
accel/tcg/plugin-gen.c | 13 +
accel/tcg/meson.build | 7 ---
2 files changed, 9 insertions(+), 11 dele
All this is working toward building accel/tcg/translator.c once,
but it got late and I decided to stop at a convenient milestone.
In the process, I discovered that we have already added files to
common_ss which indirectly depend on CONFIG_USER_ONLY. Sometimes
this is harmless, and sometimes it re
Cache the mmu index in DisasContextBase.
Perform the read on host endianness, which lets us
share code with the translator_ld fast path.
Signed-off-by: Richard Henderson
---
include/exec/translator.h | 1 +
accel/tcg/translator.c| 57 ++-
2 files changed,
Convert the existing includes with sed.
Signed-off-by: Richard Henderson
---
hw/net/i82596.h | 2 +-
hw/s390x/ipl.h| 2 +-
include/hw/misc/lasi.h| 2 +-
include/hw/nubus/nubus.h | 2 +-
include/hw/ppc/vof.
CONFIG_USER_ONLY == !CONFIG_SYSTEM_ONLY.
Therefore it's cleaner to just add to user_ss.
Signed-off-by: Richard Henderson
---
accel/tcg/meson.build | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build
index 38ff227eb0..14bf797fda 10
We were hiding a number of declarations from user-only,
although it hurts nothing to allow them. The inlines
for user-only are unused.
Signed-off-by: Richard Henderson
---
include/hw/intc/armv7m_nvic.h | 14 --
1 file changed, 14 deletions(-)
diff --git a/include/hw/intc/armv7m_nvi
These expand inline to the *_mmuidx_ra api with
a lookup of the target's cpu_mmu_index().
Signed-off-by: Richard Henderson
---
include/exec/cpu_ldst.h | 144 +---
accel/tcg/ldst_common.c.inc | 108 ---
2 files changed, 118 insertions(+)
Split out the *_mmu api, which no longer uses
target specific argument types.
Signed-off-by: Richard Henderson
---
include/exec/cpu-ldst-common.h | 122 +
include/exec/cpu_ldst.h| 108 +
2 files changed, 123 insertions(+), 107 d
While setup_post and has_memory will not be used for
CONFIG_USER_ONLY, let the struct have constant layout.
Signed-off-by: Richard Henderson
---
include/qemu/accel.h | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/include/qemu/accel.h b/include/qemu/accel.h
index 9
While RISCVCPUConfig.satp_mode is unused for user-only,
this header is used from disas/riscv.h, whose users are
only built once. The savings of 4 bytes isn't worth it.
Signed-off-by: Richard Henderson
---
target/riscv/cpu_cfg.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/target/riscv/c
Add a new family of translator load functions which take
an absolute endianness value in the form of MO_BE/MO_LE.
Expand the other translator_ld* functions on top of this.
Remove exec/tswap.h from translator.c.
Signed-off-by: Richard Henderson
---
include/exec/translator.h | 49 +
Some of the headers used require CONFIG_USER_ONLY.
Signed-off-by: Richard Henderson
---
system/meson.build | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/system/meson.build b/system/meson.build
index c83d80fa24..2aab3e97f4 100644
--- a/system/meson.build
+++ b/system/mes
We were hiding a number of declarations from user-only,
although it hurts nothing to allow them.
Signed-off-by: Richard Henderson
---
include/exec/cpu-common.h | 6 --
1 file changed, 6 deletions(-)
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index be032e1a49..9b83fd7
This is include/system, so CONFIG_USER_ONLY will never be true.
Signed-off-by: Richard Henderson
---
include/system/cpu-timers.h | 2 +-
include/system/qtest.h | 2 --
2 files changed, 1 insertion(+), 3 deletions(-)
diff --git a/include/system/cpu-timers.h b/include/system/cpu-timers.h
ind
Convert the existing includes with sed.
Signed-off-by: Richard Henderson
---
include/system/ram_addr.h | 2 +-
include/{exec => system}/ramblock.h | 9 -
hw/display/virtio-gpu-udmabuf.c | 2 +-
hw/hyperv/hv-balloon.c | 2 +-
hw/virtio/vhost-user.c
Perform aligned atomic reads in translator_ld, if possible.
According to
https://lore.kernel.org/qemu-devel/20240607101403.1109-1-jim@sifive.com/
this is required for RISC-V Ziccif.
Signed-off-by: Richard Henderson
---
accel/tcg/translator.c | 42 ++
We already have two subdirectories for which we need
to build files twice, for user vs system modes.
Move this handling to the top level.
This cannot be combined with user_ss or system_ss,
because the formulation has not been extended to support
configuration symbols.
Signed-off-by: Richard Hende
Avoid testing CONFIG_USER_ONLY in semihost.h.
Signed-off-by: Richard Henderson
---
include/semihosting/semihost.h | 29 ++---
semihosting/user.c | 30 ++
semihosting/meson.build| 2 ++
3 files changed, 34 insertions(+), 27
These expand inline to the *_mmu api with trivial
massaging of the arguments.
Signed-off-by: Richard Henderson
---
include/exec/cpu_ldst.h | 163
accel/tcg/ldst_common.c.inc | 118 --
2 files changed, 129 insertions(+), 152 deletio
Convert the existing includes with sed.
Signed-off-by: Richard Henderson
---
hw/display/vga_int.h | 2 +-
include/hw/char/parallel-isa.h| 2 +-
include/hw/dma/i8257.h| 2 +-
include/hw/ide/ide-bus.h | 2 +-
include/hw/isa/isa.h | 2 +-
include/{
While some of these files are built exactly once, due
to being in only libuser_ss or libsystem_ss, some of
the includes that they depend on require CONFIG_USER_ONLY.
So make use of the common infrastructure to allow that.
Signed-off-by: Richard Henderson
---
accel/tcg/meson.build | 17 ++
These expand inline to the *_mmu api with a lookup of
the target's cpu_mmu_index() and ra == 0.
Signed-off-by: Richard Henderson
---
include/exec/cpu_ldst.h | 31 +++
accel/tcg/cputlb.c | 28
accel/tcg/user-exec.c | 40 -
The implementation of cpu_mmu_index was split between
cpu-common.h and cpu-all.h, depending on CONFIG_USER_ONLY.
Unify within a new header and include only where needed.
Signed-off-by: Richard Henderson
---
include/exec/cpu-all.h| 6 --
include/exec/cpu-common.h | 20 ---
Convert the existing includes with sed.
Signed-off-by: Richard Henderson
---
include/{exec => system}/ram_addr.h | 7 +++
accel/kvm/kvm-all.c | 2 +-
accel/tcg/cputlb.c | 2 +-
accel/tcg/translate-all.c | 2 +-
hw/ppc/spapr.c |
Semihosting is not enabled for user-only.
Avoid the test for that case.
Signed-off-by: Richard Henderson
---
target/mips/cpu.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index b207106dd7..1ca182c1a2 100644
--- a/target/mips/cpu.c
+
The mmap_lock is user-only, whereas watchpoint.c
is only compiled for system mode.
Signed-off-by: Richard Henderson
---
accel/tcg/watchpoint.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/accel/tcg/watchpoint.c b/accel/tcg/watchpoint.c
index 65b21884ce..cfb37a49e7 100644
--- a/accel/tcg
We were hiding a number of declarations from user-only,
although it hurts nothing to allow them.
Signed-off-by: Richard Henderson
---
include/hw/s390x/css.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/include/hw/s390x/css.h b/include/hw/s390x/css.h
index cd97e2b707..965545ce73 100644
--
Uninline the user-only stubs from hw/core/cpu.h.
Signed-off-by: Richard Henderson
---
include/hw/core/cpu.h | 23 ---
common-user/watchpoint-stub.c | 28
common-user/meson.build | 1 +
3 files changed, 29 insertions(+), 23 deletions
Many of the headers used by these require CONFIG_USER_ONLY.
Signed-off-by: Richard Henderson
---
hw/core/meson.build | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/core/meson.build b/hw/core/meson.build
index b5a545a0ed..547de6527c 100644
--- a/hw/core/meson.build
+++
Copy to libuser_ss and libsystem_ss.
This file uses semihosting/semihost.h, which has separate
implementations with and without CONFIG_USER_ONLY.
Signed-off-by: Richard Henderson
---
gdbstub/meson.build | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/gdbstub/meson.build b
Headers used by these files require CONFIG_USER_ONLY.
Signed-off-by: Richard Henderson
---
plugins/meson.build | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/plugins/meson.build b/plugins/meson.build
index 3be8245a69..5383c7b88b 100644
--- a/plugins/meson.build
+++ b/plu
Convert the existing includes with
sed -i ,exec/memory.h,system/memory.h,g
Move the include within cpu-all.h into a !CONFIG_USER_ONLY block.
Signed-off-by: Richard Henderson
---
hw/arm/strongarm.h| 2 +-
hw/display/apple-gfx.h| 2 +-
hw/display/fra
These expand inline to the *_data_ra api with ra == 0.
Signed-off-by: Richard Henderson
---
include/exec/cpu_ldst.h | 123 ++--
accel/tcg/ldst_common.c.inc | 89 --
2 files changed, 104 insertions(+), 108 deletions(-)
diff --git a/inc
Split out mmap_lock, et al from page-protection.h
to a new header.
Signed-off-by: Richard Henderson
---
accel/tcg/internal-target.h| 1 +
include/exec/mmap-lock.h | 33 +
include/exec/page-protection.h | 22 --
accel/tcg/cpu-exec.c
According to the commit below, configure qemu like this:
$ ./configure --enable-debug --enable-slirp
and even before configure, i did:
$ meson subprojects download
but qemu still builded with native libslirp,
then how can I build with slirp.wrap? even when libslirp is installed on
the system.
*c
On Tue, Mar 11, 2025 at 8:59 PM Nicholas Piggin wrote:
>
> The following changes since commit 825b96dbcee23d134b691fc75618b59c5f53da32:
>
> Merge tag 'migration-20250310-pull-request' of
> https://gitlab.com/farosas/qemu into staging (2025-03-11 09:32:07 +0800)
>
> are available in the Git repo
Hi,
CI jobs that run test_arm_orangepi.py are failing:
https://gitlab.com/qemu-project/qemu/-/jobs/9390048284#L1138
Please consider how to resolve this so the CI job passes again. If you
are in contact with the archive.netbsd.org administrators, maybe
contacting them will lead to a fix. Otherwise
On 3/6/25 04:27, Alex Bennée wrote:
Pierrick Bouvier writes:
Signed-off-by: Pierrick Bouvier
---
include/hw/hyperv/hyperv.h | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/include/hw/hyperv/hyperv.h b/include/hw/hyperv/hyperv.h
index d717b4e13d4..c6f7039447f 100644
-
Ah, It is a pity and bad news that I contribute almost 30% of it :(
LoongArch system actually needs more people participation and I need
notice this also. It should happens in future again in LoongArch subsystem.
Any reviewing comments is welcome and I will slow down for deeper
considerations.
When cryptodev_lkcf_set_op_desc() fails, we report an error, but
continue anyway. This is wrong. We then pass a non-null @local_error
to various functions, which could easily fail error_setv()'s assertion
on failure.
Fail the function instead.
When qcrypto_akcipher_new() fails, we fail the func
If the IOMMU granularity is smaller than the TARGET_PAGE size, there may be
multiple entries within the same page. To obtain the correct result, pass
the original address to the IOMMU.
Similar to the RISC-V PMP solution, the TLB_INVALID_MASK will be set when
there are multiple entries in the same
On Wed, 12 Mar 2025, Bernhard Beschow wrote:
Fixes a crash when creating the SoC object on the command line:
$ ./qemu-system-aarch64 -M virt -device fsl-imx8mp
**
ERROR:../../devel/qemu/tcg/tcg.c:1006:tcg_register_thread: assertion failed:
(n < tcg_max_ctxs)
Bail out! ERROR:../../devel/qem
Hi Thomas,
(patch merged as commit 4f7689f0817)
On 16/8/23 23:07, Thomas Huth wrote:
When starting a guest via libvirt with "virsh start --console ...",
the first second of the console output is missing. This is especially
annoying on s390x that only has a text console by default and no graphic
On 12/3/25 22:26, Bernhard Beschow wrote:
Fixes a crash when creating the SoC object on the command line:
$ ./qemu-system-aarch64 -M virt -device fsl-imx8mp
**
ERROR:../../devel/qemu/tcg/tcg.c:1006:tcg_register_thread: assertion failed:
(n < tcg_max_ctxs)
Bail out! ERROR:../../de
On 13/3/25 00:10, Brian Cain wrote:
On 3/12/2025 2:19 PM, Philippe Mathieu-Daudé wrote:
On 1/3/25 06:26, Brian Cain wrote:
From: Brian Cain
Signed-off-by: Brian Cain
---
target/hexagon/cpu.c | 8
1 file changed, 8 insertions(+)
diff --git a/target/hexagon/cpu.c b/target/hexagon
On 12/3/25 22:15, Sid Manning wrote:
-Original Message-
From: Philippe Mathieu-Daudé
Sent: Wednesday, March 12, 2025 2:20 PM
To: Brian Cain ; qemu-devel@nongnu.org
Cc: richard.hender...@linaro.org; Matheus Bernardino (QUIC)
; a...@rev.ng; a...@rev.ng; Marco Liebel
(QUIC) ; ltaylorsimp
On 3/12/2025 2:19 PM, Philippe Mathieu-Daudé wrote:
On 1/3/25 06:26, Brian Cain wrote:
From: Brian Cain
Signed-off-by: Brian Cain
---
target/hexagon/cpu.c | 8
1 file changed, 8 insertions(+)
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index 36a93cc22f..2b6a707fca
Signed-off-by: Changzhi Xie
---
block/export/fuse.c | 167 ++--
1 file changed, 114 insertions(+), 53 deletions(-)
diff --git a/block/export/fuse.c b/block/export/fuse.c
index 465cc9891d..f47117a00d 100644
--- a/block/export/fuse.c
+++ b/block/export/fuse.
Hi Zhao,
On 3/12/25 1:30 AM, Zhao Liu wrote:
>> +/*
>> + * If KVM_CAP_PMU_CAPABILITY is not supported, there is no way to
>> + * disable the AMD pmu virtualization.
>> + *
>> + * If KVM_CAP_PMU_CAPABILITY is supported !cpu->enable_pmu
>> + * indicate
gs/hw-misc-20250312
for you to fetch changes up to 7f2a5272ff3893ef412c093aae66b7ed34ab3dfc:
hw/sd/sdhci: Remove need for SDHCI_VENDOR_IMX definition (2025-03-12 11:11:42
+0100)
Since v1:
- Fixed typo in last patch subject (Zoltan)
--
Hello,
I was recently trying to boot up a q35 machine with some custom PCIe
Devices that require 4Gb of BAR Space, and ran into an issue where I
cannot declare the BAR Space of a device to be above 512Mb or the q35
machine will not boot correctly. This is true even if I try to
increase the BAR spa
As discussed in [1], this series fixes the SoC class to be not user-creatable
to prevent a crash, and to be derived from TYPE_SYS_BUS_DEVICE to make reset
work properly. It also removes an unused define.
[1]
https://lore.kernel.org/qemu-devel/1cdb6643-8fcc-4bd8-93fc-fcc93589c...@redhat.com/
Bern
Fixes a crash when creating the SoC object on the command line:
$ ./qemu-system-aarch64 -M virt -device fsl-imx8mp
**
ERROR:../../devel/qemu/tcg/tcg.c:1006:tcg_register_thread: assertion failed:
(n < tcg_max_ctxs)
Bail out! ERROR:../../devel/qemu/tcg/tcg.c:1006:tcg_register_thread:
as
The SoC has three SPI controllers, not four. Remove the extra define of an SPI
IRQ.
Fixes: 06908a84f036 "hw/arm/fsl-imx8mp: Add SPI controllers"
Signed-off-by: Bernhard Beschow
---
include/hw/arm/fsl-imx8mp.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/include/hw/arm/fsl-imx8mp.h b/includ
> -Original Message-
> From: Philippe Mathieu-Daudé
> Sent: Wednesday, March 12, 2025 2:20 PM
> To: Brian Cain ; qemu-devel@nongnu.org
> Cc: richard.hender...@linaro.org; Matheus Bernardino (QUIC)
> ; a...@rev.ng; a...@rev.ng; Marco Liebel
> (QUIC) ; ltaylorsimp...@gmail.com;
> alex.ben.
> -Original Message-
> From: Brian Cain
> Sent: Friday, February 28, 2025 11:26 PM
> To: qemu-devel@nongnu.org
> Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org;
> phi...@linaro.org; Matheus Bernardino (QUIC)
> ; a...@rev.ng; a...@rev.ng; Marco Liebel
> (QUIC) ; ltaylorsimp
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