[PATCH] tests/qtest/cpu-plug-test: Add cpu hotplug support for LoongArch

Add cpu hotplug testcase support for LoongArch system, it passes to run with command "make check-qtest-loongarch64" as following: qemu:qtest+qtest-loongarch64 / qtest-loongarch64/cpu-plug-test OK 0.64s 1 subtests passed Signed-off-by: Bibo Mao --- tests/qtest/cpu-plug-test.c | 28

Re: [PATCH v2 07/10] target/i386/kvm: query kvm.enable_pmu parameter

On Sun, Mar 02, 2025 at 02:00:15PM -0800, Dongli Zhang wrote: > Date: Sun, 2 Mar 2025 14:00:15 -0800 > From: Dongli Zhang > Subject: [PATCH v2 07/10] target/i386/kvm: query kvm.enable_pmu parameter > X-Mailer: git-send-email 2.43.5 > > There is no way to distinguish between the following scenari

Re: [PULL 00/31] testing, plugin and maintainer updates

On Mon, Mar 10, 2025 at 5:02 AM Alex Bennée wrote: > > Stefan Hajnoczi writes: > > > On Sun, Mar 9, 2025 at 5:54 AM Alex Bennée wrote: > >> > >> The following changes since commit > >> 98c7362b1efe651327385a25874a73e008c6549e: > >> > >> Merge tag 'accel-cpus-20250306' of https://github.com/ph

[PATCH 08/16] exec/exec-all: remove dependency on cpu.h

Signed-off-by: Pierrick Bouvier --- include/exec/exec-all.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index dd5c40f2233..19b0eda44a7 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -20,7 +20,6 @@ #ifndef EXEC_ALL_H

[PATCH 01/16] exec/memory_ldst: extract memory_ldst declarations from cpu-all.h

They are now accessible through exec/memory.h instead, and we make sure all variants are available for common or target dependent code. Signed-off-by: Pierrick Bouvier --- include/exec/cpu-all.h | 12 include/exec/memory_ldst.h.inc | 13 + 2 files changed, 5 inse

Re: [PATCH v2 13/14] pnv/xive: Fix problem with treating NVGC as a NVP

On Tue Dec 10, 2024 at 10:05 AM AEST, Michael Kowal wrote: > From: Glenn Miles > > When booting with PHYP, the blk/index for a NVGC was being > mistakenly treated as the blk/index for a NVP. Renamed > nvp_blk/nvp_idx throughout the code to nvx_blk/nvx_idx to prevent > confusion in the future and

Re: [PATCH v2 11/14] pnv/xive: Only support crowd size of 0, 2, 4 and 16

This one got folded back into the crowd matching patch, so I will take that version but LGTM. Thanks, Nick On Tue Dec 10, 2024 at 10:05 AM AEST, Michael Kowal wrote: > From: Glenn Miles > > XIVE crowd sizes are encoded into a 2-bit field as follows: > 0: 0b00 > 2: 0b01 > 4: 0b10 > 16: 0b1

[PATCH 06/16] exec/cpu-all.h: we can now remove ld/st macros

Functions declared in bswap.h will be used instead. At this point, we finished to extract memory API from cpu-all.h, and it can be called from any common or target dependent code. Signed-off-by: Pierrick Bouvier --- include/exec/cpu-all.h | 25 - 1 file changed, 25 delet

[PATCH v7 2/7] hw/char/pl011: Introduce pl011_xmit()

Extract pl011_xmit() from pl011_write_txdata(). Use the FIFO to pass the single character to be transmitted. Update flags appropriately. Reviewed-by: Peter Maydell Signed-off-by: Philippe Mathieu-Daudé --- hw/char/pl011.c | 43 --- hw/char/trace-even

Re: [PATCH v2 09/14] ppc/xive2: Add support for MMIO operations on the NVPG/NVC BAR

On Tue Dec 10, 2024 at 10:05 AM AEST, Michael Kowal wrote: > From: Frederic Barrat > > Add support for the NVPG and NVC BARs. Access to the BAR pages will > cause backlog counter operations to either increment or decriment > the counter. > > Also added qtests for the same. > > Signed-off-by: Fred

[PULL 23/38] target/loongarch: Move has_work() from CPUClass to SysemuCPUOps

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20250125170125.32855-11-phi...@linaro.org> --- target/loongarch/cpu.c | 8 +++- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 49f603149dc..e

[PATCH 10/16] exec/ram_addr: remove dependency on cpu.h

Signed-off-by: Pierrick Bouvier --- include/exec/ram_addr.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/exec/ram_addr.h b/include/exec/ram_addr.h index 3d8df4edf15..7c011fadd11 100644 --- a/include/exec/ram_addr.h +++ b/include/exec/ram_addr.h @@ -20,13 +20,14 @@

[PATCH 11/16] system/kvm: make kvm_flush_coalesced_mmio_buffer() accessible for common code

This function is used by system/physmem.c will be turn into common code in next commit. Signed-off-by: Pierrick Bouvier --- include/system/kvm.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/include/system/kvm.h b/include/system/kvm.h index ab17c09a551..21da3b8b052 10

[PATCH 13/16] hw/xen: add stubs for various functions

Those functions are used by system/physmem.c, and are called only if xen is enabled (which happens only if CONFIG_XEN is not set). So we can crash in case those are called. Signed-off-by: Pierrick Bouvier --- hw/xen/xen_stubs.c | 56 ++ hw/xen/meson.b

[PATCH 09/16] exec/memory-internal: remove dependency on cpu.h

Signed-off-by: Pierrick Bouvier --- include/exec/memory-internal.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/include/exec/memory-internal.h b/include/exec/memory-internal.h index 100c1237ac2..b729f3b25ad 100644 --- a/include/exec/memory-internal.h +++ b/include/exec/memory-internal.h @

[PATCH 07/16] codebase: prepare to remove cpu.h from exec/exec-all.h

Signed-off-by: Pierrick Bouvier --- include/tcg/tcg-op.h | 1 + target/ppc/helper_regs.h | 2 ++ hw/ppc/spapr_nested.c | 1 + hw/sh4/sh7750.c| 1 + page-vary-target.c | 3 ++- target/riscv/bitmanip_helper.c | 1 + 6 files changed, 8 insertions(

[PATCH 02/16] exec/memory_ldst_phys: extract memory_ldst_phys declarations from cpu-all.h

They are now accessible through exec/memory.h instead, and we make sure all variants are available for common or target dependent code. To allow this, we need to implement address_space_st{*}_cached, simply forwarding the calls to _cached_slow variants. Signed-off-by: Pierrick Bouvier --- inclu

[PATCH 05/16] qemu/bswap: implement {ld,st}.*_p as functions

For now, they are duplicate of the same macros in cpu-all.h that we eliminate in next commit. Keep code readable by not defining them with macros, but simply their implementation. Signed-off-by: Pierrick Bouvier --- include/qemu/bswap.h | 70 1 file

[PATCH 00/16] make system memory API available for common code

The main goal of this series is to be able to call any memory ld/st function from code that is *not* target dependent. As a positive side effect, we can turn related system compilation units into common code. The first 6 patches remove dependency of memory API to cpu headers and remove dependency

[PATCH 04/16] exec/memory.h: make devend_memop target agnostic

Will allow to make system/memory.c common later. Signed-off-by: Pierrick Bouvier --- include/exec/memory.h | 12 +--- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/include/exec/memory.h b/include/exec/memory.h index 7c20f36a312..698179b26d2 100644 --- a/include/exec/memor

Re: [PATCH v2 07/14] ppc/xive2: Process group backlog when updating the CPPR

On Tue Dec 10, 2024 at 10:05 AM AEST, Michael Kowal wrote: > From: Frederic Barrat > > When the hypervisor or OS pushes a new value to the CPPR, if the LSMFB > value is lower than the new CPPR value, there could be a pending group > interrupt in the backlog, so it needs to be scanned. > > Signed-o

Re: [PATCH v2 08/14] qtest/xive: Add group-interrupt test

On Tue Dec 10, 2024 at 10:05 AM AEST, Michael Kowal wrote: > From: Frederic Barrat > > Add XIVE2 tests for group interrupts and group interrupts that have > been backlogged. > > Signed-off-by: Frederic Barrat > Signed-off-by: Michael Kowal Reviewed-by: Nicholas Piggin > --- > tests/qtest/pnv

RE: [PATCH v2 15/21] hw/vfio/pci: Check CONFIG_IOMMUFD at runtime using iommufd_builtin()

Hi Philippe, >-Original Message- >From: Philippe Mathieu-Daudé >Subject: [PATCH v2 15/21] hw/vfio/pci: Check CONFIG_IOMMUFD at runtime >using iommufd_builtin() > >Convert the compile time check on the CONFIG_IOMMUFD definition >by a runtime one by calling iommufd_builtin(). > >Reviewed-by

Re: [PATCH v2 05/14] ppc/xive2: Add undelivered group interrupt to backlog

On Tue Dec 10, 2024 at 10:05 AM AEST, Michael Kowal wrote: > From: Frederic Barrat > > When a group interrupt cannot be delivered, we need to: > - increment the backlog counter for the group in the NVG table > (if the END is configured to keep a backlog). > - start a broadcast operation to set t

Re: [PULL 00/23] tcg patch queue

Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/10.0 for any user-visible changes. signature.asc Description: PGP signature

Re: [PULL 0/2] loongarch tcg queue

Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/10.0 for any user-visible changes. signature.asc Description: PGP signature

RE: [PATCH rfcv2 06/20] host_iommu_device: Define two new capabilities HOST_IOMMU_DEVICE_CAP_[NESTING|FS1GP]

Hi Eric, Nicolin, >-Original Message- >From: Nicolin Chen >Subject: Re: [PATCH rfcv2 06/20] host_iommu_device: Define two new >capabilities HOST_IOMMU_DEVICE_CAP_[NESTING|FS1GP] > >On Thu, Mar 06, 2025 at 04:59:39PM +0100, Eric Auger wrote: >> >>> +++ b/include/system/host_iommu_device.h

Re: [PATCH v2 05/10] target/i386/kvm: extract unrelated code out of kvm_x86_build_cpuid()

> How about we still wrap in another new function with &cpuid_data.cpuid as > an argument? > > 1. In current patch, we need cpuid(0xa) to query Intel PMU info. > > 2. In PATCH 08/10 (AMD), we need cpuid(0x8001) to determine PERFCORE. > > https://lore.kernel.org/all/20250302220112.17653-9-don

Re: [PATCH v2 02/14] ppc/xive2: Add grouping level to notification

On Tue Dec 10, 2024 at 10:05 AM AEST, Michael Kowal wrote: > From: Frederic Barrat > > The NSR has a (so far unused) grouping level field. When a interrupt > is presented, that field tells the hypervisor or OS if the interrupt > is for an individual VP or for a VP-group/crowd. This patch reworks >

[PATCH v7 1/7] hw/char/pl011: Add transmit FIFO to PL011State

In order to make the next commit easier to review, introduce the transmit FIFO, but do not yet use it. We only migrate the TX FIFO if it is in use. When migrating from new to old VM: - if the fifo is empty, migration will still work because of the subsection. - if the fifo is not empty, the su

[PATCH v4 0/2] Enhanced VSTART and VL checks for vector instructions

Hi, Alistair: I rebase both patches based on the riscv-to-apply.next branch and tested them. https://github.com/alistair23/qemu/tree/riscv-to-apply.next Only the first patch had two conflicts, which were resolved nicely, and the second patch rebased fine, so you can review it again if necessary,

Re: [PATCH] hw/elf_ops: Use physical address about kernel entry

Gently ping :) On 2025/2/19 上午10:17, Bibo Mao wrote: With load_elf() API, if input parameter translate_fn is set, loading address is converted to physical address. It should be the same for entry address, since MMU is disabled when system power on, the first instruction of PC should be physical

[PATCH v4 2/2] target/riscv: fix handling of nop for vstart >= vl in some vector instruction

Recently, when I was writing a RISCV test, I found that when VL is set to 0, the instruction should be nop, but when I tested it, I found that QEMU will treat all elements as tail elements, and in the case of VTA=1, write all elements to 1. After troubleshooting, it was found that the vext_vx_rm_1

[PATCH v4 1/2] target/riscv: refactor VSTART_CHECK_EARLY_EXIT() to accept vl as a parameter

Some vector instructions are special, such as the vlm.v instruction, where setting its vl actually sets evl = (vl + 7) >> 3. To improve maintainability, we will uniformly use VSTART_CHECK_EARLY_EXIT() to check for the condition vstart >= vl. This function will also handle cases involving evl. Fixe

Re: [PATCH v4 0/7] hw/hyperv: remove duplication compilation units

On 3/9/25 17:14, Philippe Mathieu-Daudé wrote: On 10/3/25 00:33, Pierrick Bouvier wrote: Hi Maciej, On 3/7/25 14:31, Maciej S. Szmigiero wrote: Hi Philippe, On 7.03.2025 23:25, Philippe Mathieu-Daudé wrote: Hi Maciej, On 7/3/25 22:56, Pierrick Bouvier wrote: Work towards having a single bi

[PATCH v7 7/7] hw/char/pl011: Implement TX FIFO

If the UART back-end chardev doesn't drain data as fast as stdout does or blocks, buffer in the TX FIFO to try again later. This avoids having the IO-thread busy waiting on chardev back-ends, reported recently when testing the Trusted Reference Stack and using the socket backend. Implement regist

Re: [PATCH] hw/net/smc91c111: Don't allow data register access to overrun buffer

On 28/2/25 20:16, Peter Maydell wrote: For accesses to the 91c111 data register, the address within the packet's data frame is determined by a combination of the pointer register and the offset used to access the data register, so that you can access data at effectively wider than byte width. Th

[PATCH v7 6/7] hw/char/pl011: Drain TX FIFO when no backend connected

When no character backend is connected, the PL011 frontend just drains the FIFO. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell --- hw/char/pl011.c | 13 + hw/char/trace-events | 1 + 2 files changed, 14 insertions(+) diff --git a/hw/char/pl011.c b/hw/char/p

[PATCH v7 4/7] hw/char/pl011: Trace FIFO enablement

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell --- hw/char/pl011.c | 3 ++- hw/char/trace-events | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/char/pl011.c b/hw/char/pl011.c index 18ea03a52f4..34a5cb3af5d 100644 --- a/hw/char/pl011.c +++ b/hw/char

[PATCH v7 5/7] hw/char/pl011: Consider TX FIFO overrun error

When transmission is disabled, characters are still queued to the FIFO which eventually overruns. Report that error condition in the status register. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell --- hw/char/pl011.c | 22 ++ hw/char/trace-events | 2

[PATCH v7 3/7] hw/char/pl011: Factor pl011_xmit_cb() out as GSource

Implement pl011_xmit_cb() using the FEWatchFunc prototype to register it as GSource. While the return value is not yet used, we return G_SOURCE_REMOVE, meaning the GSource is removed from the main loop (because we only send one char). Reviewed-by: Peter Maydell Signed-off-by: Philippe Mathieu-Dau

[PATCH v7 0/7] hw/char/pl011: Implement TX (async) FIFO to avoid blocking the main loop

Hi, This series add support for (async) FIFO on the transmit path of the PL011 UART. Since v6: - Incorporated Peter's fixes in corresponding patches Since v5: - Rebased (few patches already merged) - Do not forbid disabled UART/receiver (Peter) - Use fifo8_peek API for wrapped buffer (Mark) Sin

Re: [PULL 09/41] hw/vmapple/vmapple: Add vmapple machine type

On 5/3/25 02:21, Philippe Mathieu-Daudé wrote: From: Alexander Graf Apple defines a new "vmapple" machine type as part of its proprietary macOS Virtualization.Framework vmm. This machine type is similar to the virt one, but with subtle differences in base devices, a few special vmapple device a

[PATCH v2] QIOChannelSocket: Flush zerocopy socket error queue on ENOBUF failure for sendmsg

We allocate extra metadata SKBs in case of a zerocopy send. This metadata memory is accounted for in the OPTMEM limit. If there is any error while sending zerocopy packets or if zerocopy is skipped, these metadata SKBs are queued in the socket error queue. This error queue is freed when userspace r

Re: [PATCH v2] meson.build: default to -gsplit-dwarf for debug info

Il gio 6 mar 2025, 11:53 Alex Bennée ha scritto: > -option_cflags = (get_option('debug') ? ['-g'] : []) > +option_cflags = [] > +if get_option('debug') > + option_cflags += get_option('split_debug') ? ['-gsplit-dwarf'] : ['-g'] > +endif > option_cflags does nothing, it's only for clarity in the

[PATCH v5 07/14] hw/sd/sdhci: Make quirks a class property

Allow to enforce implementations quirks by the class. All TYPE_IMX_USDHC instances use the quirk: move it to the class layer. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/sd/sdhci.h | 2 ++ hw/sd/sdhci.c | 12 +++- 2 files changed, 13 insertions(+), 1 deletion(-) diff

[PATCH v5 05/14] hw/sd/sdhci: Include 'pending-insert-quirk' property in quirk bitmask

Import Linux's SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET quirk definition. Replace 'pending_insert_quirk' boolean (originally introduce in commit 0a7ac9f9e72 "sdhci: quirk property for card insert interrupt status on Raspberry Pi") by a bit in quirk bitmask. Signed-off-by: Philippe Mathieu-Daudé ---

[PATCH v5 14/14] hw/sd/sdhci: Remove unnecessary 'endianness' property

The previous commit removed the single use of instance setting the "endianness" property. Since classes can register their io_ops with correct endianness, no need to support different ones. Remove the code related to SDHCIState::endianess field. Remove the now unused SDHCIState::io_ops field, si

Re: [PATCH v4 0/7] hw/hyperv: remove duplication compilation units

On 10/3/25 00:33, Pierrick Bouvier wrote: Hi Maciej, On 3/7/25 14:31, Maciej S. Szmigiero wrote: Hi Philippe, On 7.03.2025 23:25, Philippe Mathieu-Daudé wrote: Hi Maciej, On 7/3/25 22:56, Pierrick Bouvier wrote: Work towards having a single binary, by removing duplicated object files. Pi

[PATCH v9 01/10] ui/sdl2: Restore original context after new context creation

SDL API changes GL context to a newly created GL context, which differs from other GL providers that don't switch context. Change SDL backend to restore the original GL context. This allows Qemu's virtio-gpu to support new virglrenderer async-fencing feature for Virgl contexts, otherwise virglrende

[PATCH v5 10/14] hw/sd/sdhci: Allow SDHCI classes to register their own read-only regs

Some registers are read-only. Since we allow instances to clear/set extra bits of capareg, log when read-only bits normally set by hardware are cleared at board level. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/sd/sdhci.h | 7 +++ hw/sd/sdhci.c | 10 +- 2 files ch

Re: [PATCH v5 08/29] hw/arm/aspeed: Rename IRQ table and machine name for AST2700 A0

On 3/6/25 11:38, Jamin Lin wrote: Currently, AST2700 SoC only supports A0. To support AST2700 A1, rename its IRQ table and machine name. To follow the machine deprecation rule, the initial machine "ast2700-evb" is aliased to "ast2700a0-evb." In the future, we will alias "ast2700-evb" to new SoCs

Re: [PATCH v2 15/62] docs/qapi-domain: add "Arguments:" field lists

John Snow writes: > This adds special rendering for Sphinx's typed field lists. > > This patch does not add any QAPI-aware markup, rendering, or > cross-referencing for the type names, yet. That feature requires a > subclass to TypedField which will happen in its own commit quite a bit > later in

[PATCH v5 03/14] hw/sd/sdhci: Redefine SDHCI_QUIRK_NO_BUSY_IRQ bitmask as bit

Signed-off-by: Philippe Mathieu-Daudé --- include/hw/sd/sdhci.h | 8 hw/sd/sdhci.c | 4 ++-- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h index 48247e9a20f..096d607f4b7 100644 --- a/include/hw/sd/sdhci.h +++ b/includ

[PATCH v5 06/14] hw/sd/sdhci: Introduce SDHCIClass stub

TYPE_SYSBUS_SDHCI is a bit odd because it uses an union to work with both SysBus / PCI parent. For this reason, we can not use the OBJECT_DECLARE_TYPE() macro twice (on SYSBUS_SDHCI & PCI_SDHCI) and we must keep a pair of lower DECLARE_INSTANCE_CHECKER) and DECLARE_CLASS_CHECKERS() for PCI, in ord

[PATCH v5 09/14] hw/sd/sdhci: Allow SDHCI classes to register their own MemoryRegionOps

Add MemoryRegionOps as a class property. For now it is only used by TYPE_IMX_USDHC. Otherwise the default remains in little endian. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/sd/sdhci.h | 1 + hw/sd/sdhci.c | 22 -- 2 files changed, 9 insertions(+), 14 dele

[PATCH v5 11/14] hw/sd/sdhci: Allow SDHCI classes to have different register reset values

For the registers which are not zeroed at reset, allow the different implementations to set particular reset values. Remove the misleading values commented in sdhci-internal.h. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: BALATON Zoltan --- hw/sd/sdhci-internal.h | 24 ---

[PATCH v5 12/14] hw/sd/sdhci: Implement Freescale eSDHC as TYPE_FSL_ESDHC

Per the MPC8569E reference manual, its SDHC I/O range is 4KiB wide, mapped in big endian order, and it only accepts 32-bit aligned access. Set the default register reset values. Reported-by: BALATON Zoltan Signed-off-by: Philippe Mathieu-Daudé --- include/hw/sd/sdhci.h | 2 ++ hw/sd/sdhci.c

[PATCH v5 08/14] hw/sd/sdhci: Make I/O region size a class property

Be ready to have SDHC implementations to cover a wider I/O address range. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: BALATON Zoltan --- include/hw/sd/sdhci.h | 1 + hw/sd/sdhci.c | 10 -- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/include/hw/sd/sdhci

[PATCH v5 13/14] hw/ppc/e500: Replace generic SDHCI by Freescale eSDHC

Zoltan reported some U-Boot versions seem to want registers to be initialized correctly before expecting interrupts. Now than we have a proper Freescale eSDHC implementation, use it. Reported-by: BALATON Zoltan Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bernhard Beschow --- hw/ppc/e50

[PATCH v5 02/14] hw/sd/sdhci: Remove need for SDHCIState::vendor field

All instances of TYPE_IMX_USDHC set vendor=SDHCI_VENDOR_IMX. No need to special-case it. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: BALATON Zoltan Reviewed-by: Bernhard Beschow --- hw/sd/sdhci-internal.h | 1 - include/hw/sd/sdhci.h | 4 hw/arm/fsl-imx25.c | 2 -- hw/arm/f

[PATCH v5 04/14] hw/sd/sdhci: Include 'wp-inverted' property in quirk bitmask

Import Linux's SDHCI_QUIRK_INVERTED_WRITE_PROTECT quirk definition. Replace 'wp_inverted' boolean by a bit in quirk bitmask. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/sd/sdhci.h | 16 ++-- hw/arm/aspeed.c | 2 +- hw/sd/sdhci.c | 6 +++--- 3 files changed,

[PATCH v5 00/14] hw/sd/sdhci: Set reset value of interrupt registers

Since v4: - Convert quirks (Zoltan) - Cache class to avoid invalid cast with PCI - Remove 'endianness' property (Bernhard) Since v3: - Fix "hw/qdev-properties-system.h" (first patch) - Convert to EndianMode (patch #10) Rainy saturday, time for some hobbyist contributions :) In this series we try

[PATCH v5 01/14] hw/qdev-properties-system: Include missing 'qapi/qapi-types-common.h'

DEFINE_PROP_ENDIAN_NODEFAULT() macro uses ENDIAN_MODE_UNSPECIFIED which is defined in "qapi/qapi-types-common.h". Fixes: 4ec96630f93 ("hw/qdev-properties-system: Introduce EndianMode QAPI enum") Signed-off-by: Philippe Mathieu-Daudé --- include/hw/qdev-properties-system.h | 1 + 1 file changed,

[PULL 31/38] target/s390x: Restrict I/O handler installers to system emulation

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20250125170125.32855-19-phi...@linaro.org> --- target/s390x/s390x-internal.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/s390x/s390x-internal.h b/target/s390x/s390x-internal.h index a750e7a343a..6e

Re: [PATCH v3 2/3] bsd-user: Propagate alignment argument to mmap_find_vma()

On Fri, Mar 7, 2025 at 6:10 AM Philippe Mathieu-Daudé wrote: > Propagate the alignment to mmap_find_vma(), effectively > embedding mmap_find_vma_aligned() within mmap_find_vma(). > > Since we ignore the alignment in do_bsd_shmat(), leave a > FIXME comment. > > Signed-off-by: Philippe Mathieu-Daud

[PULL 28/38] target/ppc: Move has_work() from CPUClass to SysemuCPUOps

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20250125170125.32855-16-phi...@linaro.org> --- target/ppc/cpu_init.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index b9772c53ecc..1780cabfc

[PULL 37/38] cpus: Remove CPUClass::has_work() handler

All handlers have been converted to SysemuCPUOps::has_work(). Remove CPUClass::has_work along with cpu_common_has_work() and simplify cpu_has_work(), making SysemuCPUOps::has_work handler mandatory. Note, since cpu-common.c is in meson's common_ss[] source set, we must define cpu_exec_class_post_i

Re: [PATCH v2 45/62] docs/qapidoc: add visit_errors() method

John Snow writes: > Notably, this method does not currently address the formatting issues > present with the "errors" section in QAPIDoc and just vomits the text > verbatim into the rST doc, with somewhat inconsistent results. > > To be addressed in a future revision. > > Signed-off-by: John Snow

Re: [PATCH v4 0/7] hw/hyperv: remove duplication compilation units

Hi Maciej, On 3/7/25 14:31, Maciej S. Szmigiero wrote: Hi Philippe, On 7.03.2025 23:25, Philippe Mathieu-Daudé wrote: Hi Maciej, On 7/3/25 22:56, Pierrick Bouvier wrote: Work towards having a single binary, by removing duplicated object files. Pierrick Bouvier (7):    hw/hyperv/hv-balloo

Re: [PATCH] system: initialize target_page_bits as soon as possible

On 3/9/25 16:12, Richard Henderson wrote: On 3/9/25 12:37, Pierrick Bouvier wrote: Allow device init functions to use it, which can be convenient in some cases (like hw/hyperv/hyperv.c). Signed-off-by: Pierrick Bouvier --- system/physmem.c | 1 - system/vl.c | 3 +++ 2 files change

Re: [PATCH v3 1/3] bsd-user: Always use mmap_find_vma_aligned() in target_mmap()

On Fri, Mar 7, 2025 at 6:09 AM Philippe Mathieu-Daudé wrote: > Massage target_mmap(): calculate alignment once, then > unconditionally call mmap_find_vma_aligned(). > > Signed-off-by: Philippe Mathieu-Daudé > --- > bsd-user/mmap.c | 11 ++- > 1 file changed, 6 insertions(+), 5 deletions

[PATCH v9 02/10] ui/sdl2: Implement dpy dmabuf functions

From: Pierre-Eric Pelloux-Prayer If EGL is used, we can rely on dmabuf to import textures without doing copies. To get this working on X11, we use the existing SDL hint: SDL_HINT_VIDEO_X11_FORCE_EGL (because dmabuf can't be used with GLX). Reviewed-by: Akihiko Odaki Acked-by: Michael S. Tsirki

[PATCH v9 07/10] ui/gtk: Don't disable scanout when display is refreshed

Display refreshment is invoked by a timer and it erroneously disables the active scanout if it happens to be invoked after scanout has been enabled. This offending scanout-disable race condition with a timer can be easily hit when Qemu runs with a disabled vsync by using SDL or GTK displays (with v

Re: [PATCH] system: initialize target_page_bits as soon as possible

On 3/9/25 12:37, Pierrick Bouvier wrote: Allow device init functions to use it, which can be convenient in some cases (like hw/hyperv/hyperv.c). Signed-off-by: Pierrick Bouvier --- system/physmem.c | 1 - system/vl.c | 3 +++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git

[PATCH v9 09/10] docs/system: virtio-gpu: Update Venus link

Change virtio-gpu Venus link, pointing it at the Mesa Venus documentation instead of the protocol. The Mesa doc provides more information and also has a link to the protocol. Suggested-by: Akihiko Odaki Reviewed-by: Akihiko Odaki Signed-off-by: Dmitry Osipenko --- docs/system/devices/virtio-gp

[PATCH v9 05/10] virtio-gpu: Support DRM native context

Add support for DRM native contexts to VirtIO-GPU. DRM context is enabled using a new virtio-gpu-gl device option "drm_native_context=on". Unlike Virgl and Venus contexts that operate on application API level, DRM native contexts work on a kernel UAPI level. This lower level results in a lightweig

[PATCH v9 08/10] docs/system: virtio-gpu: Add link to Mesa VirGL doc

Extend virtio-gpu documentation with a link to the Mesa VirGL documentation. Suggested-by: Akihiko Odaki Reviewed-by: Akihiko Odaki Signed-off-by: Dmitry Osipenko --- docs/system/devices/virtio-gpu.rst | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/docs/system/devices/vi

[PATCH v9 06/10] ui/sdl2: Don't disable scanout when display is refreshed

Display refreshment is invoked by a timer and it erroneously disables the active scanout if it happens to be invoked after scanout has been enabled. This offending scanout-disable race condition with a timer can be easily hit when Qemu runs with a disabled vsync by using SDL or GTK displays (with v

[PATCH v6 22/29] hw/arm/aspeed_ast27x0: Add SoC Support for AST2700 A1

The memory map for AST2700 A1 remains compatible with AST2700 A0. However, the IRQ mapping has been updated for AST2700 A1, with GIC interrupts now ranging from 192 to 201. Add a new IRQ map table for AST2700 A1. Add "aspeed_soc_ast2700a1_class_init" to initialize the AST2700 A1 SoC. Signed-off-by

[PATCH v9 03/10] virtio-gpu: Handle virgl fence creation errors

Print out error messages when virgl fence creation fails to aid debugging of the fence-related bugs. Reviewed-by: Akihiko Odaki Acked-by: Michael S. Tsirkin Tested-by: Alex Bennée Signed-off-by: Dmitry Osipenko --- hw/display/virtio-gpu-virgl.c | 13 - 1 file changed, 12 insertion

[PATCH v9 00/10] Support virtio-gpu DRM native context

This patchset adds DRM native context support to VirtIO-GPU on Qemu. Contarary to Virgl and Venus contexts that mediates high level GFX APIs, DRM native context [1] mediates lower level kernel driver UAPI, which reflects in a less CPU overhead and less/simpler code needed to support it. DRM contex

Re: [PATCH v4 09/14] hw/sd/sdhci: Unify default MemoryRegionOps

On 9/3/25 10:27, Bernhard Beschow wrote: Am 8. März 2025 21:36:35 UTC schrieb "Philippe Mathieu-Daudé" : Note, sdhci_mmio_le_ops[] was missing .impl.access_size = 4. Signed-off-by: Philippe Mathieu-Daudé --- hw/sd/sdhci.c | 46 -- 1 file changed, 2

Re: [PATCH] target/riscv/csr.c: fix OVERFLOW_BEFORE_WIDEN in rmw_sctrdepth()

On Fri, Mar 7, 2025 at 10:47 PM Daniel Henrique Barboza wrote: > > Coverity found the following issue: > > >>> CID 1593156: Integer handling issues (OVERFLOW_BEFORE_WIDEN) > >>> Potentially overflowing expression "0x10 << depth" with type > "int" (32 bits, signed) is evaluated usin

[PULL 01/38] linux-user: Only include 'exec/tb-flush.h' header when necessary

Very few source files require to access "exec/tb-flush.h" declarations, and except a pair, they all include it explicitly. No need to overload the generic "user-internals.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Ilya Leoshkevich Reviewed-by: Pierrick Bouvier Message-Id: <202501021

[PULL 14/38] cpus: Restrict cpu_has_work() to system emulation

This method is not used on user emulation, because there is always work to do there. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20250125170125.32855-2-phi...@linaro.org> --- include/hw/core/cpu.h | 28 ++-- 1 file changed, 14 insert

Re: [PATCH] target/riscv/csr.c: fix OVERFLOW_BEFORE_WIDEN in rmw_sctrdepth()

On Fri, Mar 7, 2025 at 10:47 PM Daniel Henrique Barboza wrote: > > Coverity found the following issue: > > >>> CID 1593156: Integer handling issues (OVERFLOW_BEFORE_WIDEN) > >>> Potentially overflowing expression "0x10 << depth" with type > "int" (32 bits, signed) is evaluated usin

Re: [PATCH v2] hw/riscv/riscv-iommu: Fix process directory table walk

On Sun, Mar 2, 2025 at 3:39 AM Jason Chien wrote: > > The PPN field in a non-leaf PDT entry is positioned differently from that > in a leaf PDT entry. The original implementation incorrectly used the leaf > entry's PPN mask to extract the PPN from a non-leaf entry, leading to an > erroneous page t

Re: [PATCH v3 0/2] Enhanced VSTART and VL checks for vector instructions

On Mon, Jan 6, 2025 at 12:44 PM Chao Liu wrote: > > Hi, all: > > In accordance with the review, i improved the commit message of patch and > added > the reason for the modification. > > There was no change in the patch content. > > PATCH v2 review: > https://lore.kernel.org/qemu-devel/61e8f7d8-60

Re: [PATCH v2 52/62] docs/qapidoc: add visit_sections() method

John Snow writes: > Implement the actual main dispatch method that processes and handles the > list of doc sections for a given QAPI entity. > > Signed-off-by: John Snow > --- > docs/sphinx/qapidoc.py | 25 + > 1 file changed, 25 insertions(+) > > diff --git a/docs/sphin

Re: [PATCH v2 23/62] docs/qapi-domain: add :deprecated: directive option

John Snow writes: > Although "deprecated" is a feature (and *will* appear in the features > list), add a special :deprecated: option to generate an eye-catch that > makes this information very hard to miss. > > (The intent is to modify qapidoc.py to add this option whenever it > detects that the

Re: [PATCH v2 32/62] qapi/parser: adjust info location for doc body section

John Snow writes: > Instead of using the info object for the doc block as a whole (which > always points to the very first line of the block), update the info > pointer for each call to ensure_untagged_section when the existing > section is otherwise empty. This way, Sphinx error information will

[PULL 03/38] bsd-user: Propagate alignment argument to mmap_find_vma()

Propagate the alignment to mmap_find_vma(), effectively embedding mmap_find_vma_aligned() within mmap_find_vma(). Add a comment in do_bsd_shmat() to clarify alignment above page size is not required. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Warner Losh Message-Id: <20250308122842.7637

Re: [PATCH 2/3] hw/net/smc91c111: Sanitize packet length on tx

Hi Peter, On 28/2/25 18:48, Peter Maydell wrote: When the smc91c111 transmits a packet, it must read a control byte which is at the end of the data area and CRC. However, we don't sanitize the length field in the packet buffer, so if the guest sets the length field to something large we will tr

Re: [PATCH v2 56/62] docs/qapidoc: add intermediate output debugger

John Snow writes: > Add debugging output for the qapidoc transmogrifier - setting DEBUG=1 > will produce .ir files (one for each qapidoc directive) that write the > generated rst file to disk to allow for easy debugging and verification > of the generated document. > > Signed-off-by: John Snow

[PULL 16/38] cpus: Introduce SysemuCPUOps::has_work() handler

SysemuCPUOps::has_work() is similar to CPUClass::has_work(), but only exposed on system emulation. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20250125170125.32855-4-phi...@linaro.org> --- include/accel/tcg/cpu-ops.h | 2 +- include/hw/core/sysemu-cpu-

Re: [PATCH v2 33/62] qapi: expand tags to all doc sections

John Snow writes: > This patch adds an explicit section "kind" to all QAPIDoc > sections. Members/Features are now explicitly marked as such, with the > name now being stored in a dedicated "name" field (which qapidoc.py was > not actually using anyway.) > > The qapi-schema tests are updated to a

[PULL 13/38] target/arm: Prefer cached CpuClass over CPU_GET_CLASS() macro

CpuState caches its CPUClass since commit 6fbdff87062 ("cpu: cache CPUClass in CPUState for hot code paths"), use it. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20250122093028.52416-11-phi...@linaro.org> --- target/arm/cpu.c | 3 +-- target/arm/tcg

Re: [PATCH v2 51/62] docs/qapidoc: add visit_member() method

John Snow writes: > This method is used for generating the "members" of a wide variety of > things, including structs, unions, enums, alternates, etc. The field > name it uses to do so is dependent on the type of entity the "member" > belongs to. > > Signed-off-by: John Snow > --- > docs/sphinx

Re: [PATCH v2 00/62] docs: Add new QAPI transmogrifier

Would you be willing to serve as maintainer of (a subset of) docs/sphinx/? If yes, please make it official by patching MAINTAINERS.

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