Re: [PATCH v5 2/2] target/loongarch: check tlb_ps

On 2025/2/28 下午5:06, Song Gao wrote: For LoongArch th min tlb_ps is 12(4KB), for TLB code, the tlb_ps may be 0,this may case UndefinedBehavior Add a check-tlb_ps fuction to check tlb_ps, to make sure the tlb_ps is avalablie. we check tlb_ps when get the tlb_ps from tlb->misc or CSR bits. 1. cp

Re: Some regression due to "ui/gtk: Fix mouse/motion event scaling issue with GTK display backend"

25.02.2025 21:03, Kim, Dongwon wrote: Hi hikalium, This commit actually breaks one of our use cases with Ubuntu host when the display scaling factor is set to 200%. It seems like gtk_widget_get_scale_factor is only way to get that DPI scaling factor and without this, mouse movement on the gues

Re: Some regression due to "ui/gtk: Fix mouse/motion event scaling issue with GTK display backend"

Hi Kim, Thanks for the report! Could you give me detailed steps to reproduce the issue so that we can work on a proper fix? Thank you, -- hikalium 2025年2月26日(水) 3:03 Kim, Dongwon : > Hi hikalium, > > This commit actually breaks one of our use cases with Ubuntu host when the > display scaling f

[PATCH 29/38] target/hexagon: Add locks, id, next_PC to state

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/cpu.h | 37 +++-- target/hexagon/cpu.c | 6 ++ target/hexagon/machine.c | 4 3 files changed, 45 insertions(+), 2 deletions(-) diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu

Kubernetes gitlab-runner jobs cannot be scheduled

Hi, On February 26th GitLab CI started failing many jobs because they could not be scheduled. I've been unable to merge pull requests because the CI is not working. Here is an example failed job: https://gitlab.com/qemu-project/qemu/-/jobs/9281757413 One issue seems to be that the gitlab-cache-pv

Re: [PATCH] util/keyval: fix msan findings

On 2/28/25 22:20, Patrick Venture wrote: From: Peter Foley e.g. qemu: Uninitialized value was created by an allocation of 'key_in_cur.i' in the stack frame qemu: #0 0xc49f489c in keyval_parse_one third_party/qemu/util/keyval.c:190:5 Signed-off-by: Peter Foley Signed-off-by: Patrick Ventu

[PATCH 05/38] target/hexagon: Switch to tag_ignore(), generate via get_{user, sys}_tags()

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/gen_helper_funcs.py | 23 ++- target/hexagon/gen_helper_protos.py | 23 --- target/hexagon/gen_idef_parser_funcs.py | 2 ++ target/hexagon/gen_op_attribs.py| 2 +- target/hex

[PATCH 00/39] hexagon system emu, part 2/3

hexagon architecture system emulation: part 2/3 This series includes the k0 and TLB locking implementation. This was briefly discussed on-list at https://lists.nongnu.org/archive/html/qemu-devel/2024-01/msg04801.html and perhaps we can continue/follow-up discussion on the relevant patch(es) in t

[PATCH 32/38] target/hexagon: Add stubs for modify_ssr/get_exe_mode

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/cpu_helper.h | 2 ++ target/hexagon/cpu_helper.c | 8 2 files changed, 10 insertions(+) diff --git a/target/hexagon/cpu_helper.h b/target/hexagon/cpu_helper.h index 5f5f15149a..e0c0c037a6 100644 --- a/target/hexagon/cpu_hel

[PATCH 29/39] target/hexagon: Add pkt_ends_tb to translation

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/translate.h | 1 + target/hexagon/translate.c | 99 +- 2 files changed, 99 insertions(+), 1 deletion(-) diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h index 9bc4b3ce8b..c953

[PATCH 03/39] target/hexagon: Implement iassign{r,w} helpers

From: Brian Cain iassign{r,w} are the "Interrupt to thread assignment {read,write}" instructions. Signed-off-by: Brian Cain --- target/hexagon/op_helper.c | 48 -- 1 file changed, 46 insertions(+), 2 deletions(-) diff --git a/target/hexagon/op_helper.c b/ta

[PATCH 06/39] target/hexagon: Implement {g,s}etimask helpers

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/op_helper.c | 31 +-- 1 file changed, 29 insertions(+), 2 deletions(-) diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c index 9f79b1a20c..83088cfaa3 100644 --- a/target/hexagon/op_help

[PATCH 20/38] target/hexagon: Implement do_raise_exception()

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/internal.h | 5 + target/hexagon/op_helper.c | 20 2 files changed, 25 insertions(+) diff --git a/target/hexagon/internal.h b/target/hexagon/internal.h index 9658141316..7cf7bcaa6c 100644 --- a/target/hexa

[PATCH 02/39] target/hexagon: Implement {c,}swi helpers

From: Brian Cain {c,}swi are the "software interrupt"/"Cancel pending interrupts" instructions. Signed-off-by: Brian Cain --- target/hexagon/op_helper.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c index b28a1

[PATCH 01/39] target/hexagon: Implement ciad helper

From: Brian Cain ciad is the clear interrupt auto disable instruction. This instruction is defined in the Qualcomm Hexagon V71 Programmer's Reference Manual - https://docs.qualcomm.com/bundle/publicresource/80-N2040-51_REV_AB_Hexagon_V71_ProgrammerS_Reference_Manual.pdf See §11.9.2 SYSTEM MONITO

[PATCH 30/38] target/hexagon: Add a TLB count property

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/cpu.h | 1 + target/hexagon/max.h | 26 ++ target/hexagon/cpu.c | 4 3 files changed, 31 insertions(+) create mode 100644 target/hexagon/max.h diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h

[PATCH 07/38] target/hexagon: Add a placeholder fp exception

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/arch.c | 5 + 1 file changed, 5 insertions(+) diff --git a/target/hexagon/arch.c b/target/hexagon/arch.c index d053d68487..87c2f6a53f 100644 --- a/target/hexagon/arch.c +++ b/target/hexagon/arch.c @@ -208,6 +208,11 @@ void arch_

[PATCH 34/39] target/hexagon: Add TLB, k0 {un,}lock

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/sys_macros.h | 8 +-- target/hexagon/op_helper.c | 104 2 files changed, 108 insertions(+), 4 deletions(-) diff --git a/target/hexagon/sys_macros.h b/target/hexagon/sys_macros.h index 3c4c3c7a

[PATCH 13/39] target/hexagon: Implement modify_syscfg()

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/op_helper.c | 51 +- 1 file changed, 50 insertions(+), 1 deletion(-) diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c index 03bed11f6e..42805d0f1d 100644 --- a/target/hexagon/o

[PATCH 04/38] target/hexagon: Make gen_exception_end_tb non-static

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/translate.h | 2 ++ target/hexagon/translate.c | 9 - 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h index d251e2233f..2bd125297a 100644 --- a/target/hex

[PATCH 25/38] target/hexagon: Add TCG overrides for thread ctl

From: Brian Cain Define TCG overrides for start, stop, wait, resume instructions. Signed-off-by: Brian Cain --- target/hexagon/gen_tcg_sys.h | 18 ++ target/hexagon/helper.h | 4 target/hexagon/op_helper.c | 20 3 files changed, 42 insertions(+

[PATCH 17/38] target/hexagon: Add vmstate representation

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/internal.h | 4 target/hexagon/cpu.c | 3 +++ target/hexagon/machine.c | 25 + 3 files changed, 32 insertions(+) create mode 100644 target/hexagon/machine.c diff --git a/target/hexagon/internal.

[PATCH 37/39] target/hexagon: Add support for loadw_phys

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/hex_common.py | 3 +++ target/hexagon/imported/encode_pp.def | 1 + target/hexagon/imported/ldst.idef | 3 +++ 3 files changed, 7 insertions(+) diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py in

[PATCH 17/39] target/hexagon: Implement software interrupt

From: Brian Cain Co-authored-by: Mike Lambert Signed-off-by: Brian Cain --- target/hexagon/cpu.h | 1 - target/hexagon/hexswi.h| 17 +++ target/hexagon/cpu.c | 2 + target/hexagon/hexswi.c| 258 + target/hexagon/op_helper.c | 1 +

[PATCH 26/38] target/hexagon: Add TCG overrides for rte, nmi

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/gen_tcg_sys.h | 19 +++ target/hexagon/helper.h | 1 + target/hexagon/op_helper.c | 4 3 files changed, 24 insertions(+) diff --git a/target/hexagon/gen_tcg_sys.h b/target/hexagon/gen_tcg_sys.h index 94

[PATCH 36/39] target/hexagon: Add TCG overrides for transfer insts

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/gen_tcg_sys.h | 25 + 1 file changed, 25 insertions(+) diff --git a/target/hexagon/gen_tcg_sys.h b/target/hexagon/gen_tcg_sys.h index 6d73a18db4..e56553462f 100644 --- a/target/hexagon/gen_tcg_sys.h +++ b/tar

[PATCH 30/39] target/hexagon: Add next_PC, {s,g}reg writes

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/cpu.h | 2 +- target/hexagon/translate.h | 2 + target/hexagon/genptr.c| 7 +- target/hexagon/translate.c | 142 - 4 files changed, 132 insertions(+), 21 deletions(-) diff --git a/

[PATCH 14/39] target/hexagon: Add system event, cause codes

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/cpu.h | 10 ++- target/hexagon/cpu_bits.h | 55 --- 2 files changed, 49 insertions(+), 16 deletions(-) diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 7e2ea838c5..dabee310c

[PATCH 26/39] target/hexagon: Decode trap1, rte as COF

From: Brian Cain Also: handle rte instructions at the end of the packet. Signed-off-by: Brian Cain --- target/hexagon/decode.c | 14 ++ 1 file changed, 14 insertions(+) diff --git a/target/hexagon/decode.c b/target/hexagon/decode.c index 23deba2426..5d0beeeaf2 100644 --- a/target/

[PATCH 19/39] target/hexagon: Implement hexagon_tlb_fill()

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/cpu.c | 133 ++- 1 file changed, 132 insertions(+), 1 deletion(-) diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index e9f24581a6..a548d575a7 100644 --- a/target/hexagon/cpu.c +++ b/

[PATCH 07/39] target/hexagon: Implement wait helper

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/cpu_helper.h | 1 + target/hexagon/cpu_helper.c | 40 + target/hexagon/op_helper.c | 6 +- 3 files changed, 46 insertions(+), 1 deletion(-) diff --git a/target/hexagon/cpu_helper.h b/target

[PATCH 27/39] target/hexagon: Implement hexagon_find_last_irq()

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/op_helper.c | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c index d0dc4afac7..f3ffac81b6 100644 --- a/target/hexagon/op_helper.c +++ b/target/hexagon/

[PATCH 13/38] target/hexagon: Define DCache states

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/cpu_bits.h | 7 +++ 1 file changed, 7 insertions(+) diff --git a/target/hexagon/cpu_bits.h b/target/hexagon/cpu_bits.h index 6582bb4f16..5d26815eb9 100644 --- a/target/hexagon/cpu_bits.h +++ b/target/hexagon/cpu_bits.h @@ -41,6

[PATCH 32/39] target/hexagon: Define system, guest reg names

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/internal.h | 2 ++ target/hexagon/cpu.c | 29 + 2 files changed, 31 insertions(+) diff --git a/target/hexagon/internal.h b/target/hexagon/internal.h index 120cfde7b9..fd2397b9ef 100644 --- a/target/

[PATCH 18/39] target/hexagon: Implement exec_interrupt, set_irq

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/cpu.h | 5 +++ target/hexagon/cpu.c | 73 2 files changed, 78 insertions(+) diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 045581d7be..d28c1249f3 100644 --- a/target/hexa

[PATCH 09/39] target/hexagon: Implement arch_get_system_reg()

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/cpu_helper.c | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/target/hexagon/cpu_helper.c b/target/hexagon/cpu_helper.c index e0dd120cd4..0b0802bfb9 100644 --- a/target/hexagon/cpu_helper.c +++ b/target/hex

[PATCH 38/38] target/hexagon: Add hex_interrupts support

From: Brian Cain Co-authored-by: Taylor Simpson Co-authored-by: Sid Manning Co-authored-by: Michael Lambert Signed-off-by: Brian Cain --- target/hexagon/cpu.h| 1 + target/hexagon/hex_interrupts.h | 15 ++ target/hexagon/cpu.c| 2 + target/hexagon/hex_interrupts.

[PATCH 37/38] target/hexagon: Define f{S,G}ET_FIELD macros

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/macros.h | 10 ++ 1 file changed, 10 insertions(+) diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h index b0e9610d98..afbbe8e265 100644 --- a/target/hexagon/macros.h +++ b/target/hexagon/macros.h @@ -649,6 +649

[PATCH 23/39] target/hexagon: Add sysemu_ops, cpu_get_phys_page_debug()

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/cpu.c | 29 + 1 file changed, 29 insertions(+) diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index a548d575a7..9f4cfd03c4 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -489,6

[PATCH 08/39] target/hexagon: Implement get_exe_mode()

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/reg_fields_def.h.inc | 11 +++ target/hexagon/cpu_helper.c | 24 2 files changed, 35 insertions(+) diff --git a/target/hexagon/reg_fields_def.h.inc b/target/hexagon/reg_fields_def.h.inc inde

[PATCH 16/38] target/hexagon: Add placeholder greg/sreg r/w helpers

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/helper.h| 9 + target/hexagon/op_helper.c | 34 ++ 2 files changed, 43 insertions(+) diff --git a/target/hexagon/helper.h b/target/hexagon/helper.h index f8baa599c8..fddbd99a19 100644 ---

[PATCH 28/38] target/hexagon: Initialize htid, modectl regs

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/cpu.c | 8 1 file changed, 8 insertions(+) diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 36a93cc22f..2b6a707fca 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -26,6 +26,7 @@ #include "fpu/

[PATCH 38/39] target/hexagon: Add guest reg reading functionality

From: Matheus Tavares Bernardino Signed-off-by: Matheus Tavares Bernardino --- target/hexagon/cpu.c | 19 ++- target/hexagon/op_helper.c | 19 +-- 2 files changed, 35 insertions(+), 3 deletions(-) diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c in

[PATCH 35/39] target/hexagon: Define gen_precise_exception()

From: Brian Cain Add PC to raise_exception helper Replace the fGEN_TCG_J2_trap0 macro override with the fTRAP()-generated system helper instead. Signed-off-by: Brian Cain --- target/hexagon/gen_tcg.h | 7 --- target/hexagon/helper.h| 2 +- target/hexagon/op_helper.c | 10 -

[PATCH 02/38] docs/system: Add hexagon CPU emulation

From: Brian Cain Signed-off-by: Brian Cain --- docs/system/hexagon/emulation.rst | 16 docs/system/target-hexagon.rst| 1 + 2 files changed, 17 insertions(+) create mode 100644 docs/system/hexagon/emulation.rst diff --git a/docs/system/hexagon/emulation.rst b/docs/syste

[PATCH 04/39] target/hexagon: Implement start/stop helpers

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/cpu.h| 3 ++ target/hexagon/cpu_bits.h | 1 + target/hexagon/cpu_helper.h | 3 ++ target/hexagon/cpu.c| 14 +- target/hexagon/cpu_helper.c | 94 + target/hexagon/op_helper.

[PATCH 34/38] target/hexagon: Add initial MMU model

From: Brian Cain Co-authored-by: Taylor Simpson Co-authored-by: Michael Lambert Co-authored-by: Sid Manning Co-authored-by: Matheus Tavares Bernardino Signed-off-by: Brian Cain --- target/hexagon/cpu-param.h | 4 + target/hexagon/cpu.h | 13 + target/hexagon/hex_mmu.h | 30 +++

[PATCH 15/39] target/hexagon: Implement hex_tlb_entry_get_perm()

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/hex_mmu.c | 54 +++- 1 file changed, 53 insertions(+), 1 deletion(-) diff --git a/target/hexagon/hex_mmu.c b/target/hexagon/hex_mmu.c index 54c4ba2dbf..d2297c036d 100644 --- a/target/hexagon/hex_m

[PATCH 08/38] target/hexagon: Add guest, system reg number defs

From: Brian Cain These registers are defined in the Qualcomm Hexagon V71 Programmer's Reference Manual - https://docs.qualcomm.com/bundle/publicresource/80-N2040-51_REV_AB_Hexagon_V71_ProgrammerS_Reference_Manual.pdf Refer to §11.9.1 SYSTEM GUEST, §11.9.2 SYSTEM MONITOR. Signed-off-by: Brian Cai

[PATCH 25/39] target/hexagon: Add hexagon_cpu_mmu_index()

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/cpu_helper.h | 1 + target/hexagon/cpu.c| 23 + target/hexagon/cpu_helper.c | 41 + 3 files changed, 65 insertions(+) diff --git a/target/hexagon/cpu_helper.h b/target

[PATCH 35/38] target/hexagon: Add IRQ events

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/cpu_bits.h | 34 ++ 1 file changed, 34 insertions(+) diff --git a/target/hexagon/cpu_bits.h b/target/hexagon/cpu_bits.h index 5d26815eb9..b559a7ba88 100644 --- a/target/hexagon/cpu_bits.h +++ b/target

[PATCH 12/39] target/hexagon: Add implementation of cycle counters

From: Brian Cain Co-authored-by: Sid Manning Signed-off-by: Brian Cain --- target/hexagon/cpu.h| 25 ++--- target/hexagon/translate.h | 2 ++ target/hexagon/cpu_helper.c | 12 +--- target/hexagon/translate.c | 27 +++ 4 files chang

[PATCH 05/39] target/hexagon: Implement modify SSR

From: Brian Cain The per-vCPU System Status Register controls many modal behaviors of the system architecture. When the SSR is updated, we trigger the necessary effects for interrupts, privilege/MMU, and HVX context mapping. Signed-off-by: Brian Cain --- target/hexagon/cpu_helper.c | 100

[PATCH 24/38] target/hexagon: Add TCG overrides for int handler insts

From: Brian Cain Define TCG overrides for {c,}swi {c,s}iad, iassign{r,w}, {s,g}etimask instructions. Signed-off-by: Brian Cain --- target/hexagon/gen_tcg_sys.h | 25 ++ target/hexagon/helper.h | 8 target/hexagon/op_helper.c | 40 +++

[PATCH 10/38] target/hexagon: Add TCG values for sreg, greg

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/translate.h | 7 +++ target/hexagon/translate.c | 7 +++ 2 files changed, 14 insertions(+) diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h index 2bd125297a..f611c854dc 100644 --- a/target/hexagon/transla

[PATCH 01/38] docs: Add hexagon sysemu docs

From: Brian Cain Signed-off-by: Brian Cain --- MAINTAINERS| 2 + docs/devel/hexagon-sys.rst | 106 + docs/devel/index-internals.rst | 1 + docs/system/hexagon/cdsp.rst | 10 docs/system/target-hexagon.rst | 100

Re: [PATCH v5 36/36] vfio/migration: Update VFIO migration documentation

On 28.02.2025 11:05, Cédric Le Goater wrote: On 2/27/25 23:01, Maciej S. Szmigiero wrote: On 27.02.2025 07:59, Cédric Le Goater wrote: On 2/19/25 21:34, Maciej S. Szmigiero wrote: From: "Maciej S. Szmigiero" Update the VFIO documentation at docs/devel/migration describing the changes brought

Re: [PATCH 1/1] hw/arm/sbsa-ref: Adding TPM support for ARM SBSA-Ref machine

Hi Graeme, Thank you for your review. Could you please let me know if there is anything else I need to do or wait on before merging the change? Any input is appreciated. Regards, Kun On Thu, Feb 27, 2025 at 7:16 AM Graeme Gregory wrote: > > On 25/02/2025 07:41, Kun Qin wrote: > > From: Kun

Re: [PATCH v5 36/36] vfio/migration: Update VFIO migration documentation

Cédric Le Goater writes: > On 2/27/25 23:01, Maciej S. Szmigiero wrote: >> On 27.02.2025 07:59, Cédric Le Goater wrote: >>> On 2/19/25 21:34, Maciej S. Szmigiero wrote: From: "Maciej S. Szmigiero" Update the VFIO documentation at docs/devel/migration describing the changes br

[PATCH v6 7/8] i386/cpu: Adjust CPUID level for RDT features

Adjust minimum CPUID level if RDT monitoring or allocation features are enabled to ensure that CPUID will return them. Signed-off-by: Hendrik Wuethrich --- target/i386/cpu.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 6262665294..1e

Re: [PATCH] accel/tcg: fix msan findings in translate-all

On Fri, Feb 28, 2025 at 1:38 PM Richard Henderson < richard.hender...@linaro.org> wrote: > On 2/28/25 13:23, Patrick Venture wrote: > > From: Peter Foley > > > > e.g. > >Uninitialized value was created by an allocation of 'host_pc' in the > stack frame > >#0 0xc07df87c in tb_gen_code

Re: [PATCH] accel/tcg: fix msan findings in translate-all

On 2/28/25 13:23, Patrick Venture wrote: From: Peter Foley e.g. Uninitialized value was created by an allocation of 'host_pc' in the stack frame #0 0xc07df87c in tb_gen_code third_party/qemu/accel/tcg/translate-all.c:297:5 Signed-off-by: Peter Foley Signed-off-by: Patrick Venture

[PATCH] util/keyval: fix msan findings

From: Peter Foley e.g. qemu: Uninitialized value was created by an allocation of 'key_in_cur.i' in the stack frame qemu: #0 0xc49f489c in keyval_parse_one third_party/qemu/util/keyval.c:190:5 Signed-off-by: Peter Foley Signed-off-by: Patrick Venture --- util/keyval.c | 2 +- 1 file chang

Re: [PATCH v5 32/36] vfio/migration: Make x-migration-multifd-transfer VFIO property mutable

On 28.02.2025 09:44, Cédric Le Goater wrote: On 2/26/25 22:05, Maciej S. Szmigiero wrote: On 26.02.2025 18:59, Cédric Le Goater wrote: On 2/19/25 21:34, Maciej S. Szmigiero wrote: From: "Maciej S. Szmigiero" DEFINE_PROP_ON_OFF_AUTO() property isn't runtime-mutable so using it would mean that

Re: [PATCH 03/22] target/riscv: introduce RISCVCPUDef

On 2/28/25 02:27, Paolo Bonzini wrote: -.class_data = GUINT_TO_POINTER(misa_mxl_max)\ +.class_data = (void*) &((const RISCVCPUDef) { \ + .misa_mxl_max = (misa_mxl_max_), \ +}), \ Drop

Re: [PATCH v5 30/36] vfio/migration: Multifd device state transfer support - send side

On 28.02.2025 10:13, Cédric Le Goater wrote: On 2/26/25 22:05, Maciej S. Szmigiero wrote: On 26.02.2025 17:43, Cédric Le Goater wrote: On 2/19/25 21:34, Maciej S. Szmigiero wrote: From: "Maciej S. Szmigiero" Implement the multifd device state transfer via additional per-device thread inside

Re: [PATCH v5 34/36] vfio/migration: Max in-flight VFIO device state buffer count limit

On 28.02.2025 09:53, Cédric Le Goater wrote: On 2/27/25 23:01, Maciej S. Szmigiero wrote: On 27.02.2025 07:48, Cédric Le Goater wrote: On 2/19/25 21:34, Maciej S. Szmigiero wrote: From: "Maciej S. Szmigiero" Allow capping the maximum count of in-flight VFIO device state buffers queued at the

Re: [PATCH v5 27/36] vfio/migration: Multifd device state transfer support - load thread

On 28.02.2025 10:11, Cédric Le Goater wrote: On 2/26/25 22:05, Maciej S. Szmigiero wrote: On 26.02.2025 14:49, Cédric Le Goater wrote: On 2/19/25 21:34, Maciej S. Szmigiero wrote: From: "Maciej S. Szmigiero" Since it's important to finish loading device state transferred via the main migrati

Re: [PATCH v5 26/36] vfio/migration: Multifd device state transfer support - received buffers queuing

On 28.02.2025 09:09, Cédric Le Goater wrote: On 2/26/25 22:04, Maciej S. Szmigiero wrote: On 26.02.2025 11:43, Cédric Le Goater wrote: On 2/19/25 21:34, Maciej S. Szmigiero wrote: From: "Maciej S. Szmigiero" The multifd received data needs to be reassembled since device state packets sent vi

Re: [PATCH] scripts: dump stdin on meson-buildoptions error

On Fri, Feb 28, 2025 at 2:26 AM Paolo Bonzini wrote: > > Dump sys.stdin when it errors on meson-buildoptions.py, letting us debug > > the build errors instead of just saying "Couldn't parse" > > Sure, why not. :) Queued the patch, it should go into 10.0. > Thanks! we kept seeing this because we

Re: [PATCH v8 00/28] vfio-user client

I appreciate you posting the patches. I didn't author the patches, actually; John Johnson did it. You could use your name as the author since you should be familiar with it now, and I can review the patches. Please add the following to each patch so it recognizes Oracle's contribution: Co-autho

Re: [PATCH v2] iotest: Unbreak 302 with python 3.13

On Fri, Feb 28, 2025 at 09:57:08PM +0200, Nir Soffer wrote: > This test depends on TarFile.addfile() to add tar member header without > writing the member data, which we write ourself using qemu-nbd. Python > 3.13 changed the function in a backward incompatible way[1] to require a > file object for

[PATCH v2] iotest: Unbreak 302 with python 3.13

This test depends on TarFile.addfile() to add tar member header without writing the member data, which we write ourself using qemu-nbd. Python 3.13 changed the function in a backward incompatible way[1] to require a file object for tarinfo with non-zero size, breaking the test: -[{"name": "vm

[PATCH v6 4/8] i386: Add RDT device interface through MSRs

Implement rdmsr and wrmsr for the following MSRs: * MSR_IA32_PQR_ASSOC * MSR_IA32_QM_EVTSEL * MSR_IA32_QM_CTR * IA32_L3_QOS_Mask_n * IA32_L2_QOS_Mask_n * IA32_L2_QoS_Ext_BW_Thrtl_n This allows for the guest to call RDT-internal functions to associate an RMID with a CLOSID / set an active RMID for

[PATCH v6 5/8] i386: Add CPUID enumeration for RDT

Add CPUID enumeration for intel RDT monitoring and allocation, as well as the flags used in the enumeration code. Signed-off-by: Hendrik Wuethrich --- include/hw/i386/rdt.h | 23 + target/i386/cpu.c | 75 +++ target/i386/cpu.h | 5 +++

[PATCH v6 3/8] i386: Add RDT functionality

Add RDT code to Associate CLOSID with RMID / set RMID for monitoring, write COS, and read monitoring data. This patch does not add code for the guest to interact through these things with MSRs, only the actual ability for the RDT device to do them. Signed-off-by: Hendrik Wuethrich --- hw/i386/rd

[PATCH v6 8/8] i386/cpu: Adjust level for RDT on full_cpuid_auto_level

Make sure that RDT monitoring and allocation features are included in in full_cpuid_auto_level. Signed-off-by: Hendrik Wuethrich --- target/i386/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 1ec3d88a65..55003760a6 100644 --- a/target/i386

[PATCH v6 6/8] i386: Add RDT feature flags.

Add RDT features to feature word / TCG. Signed-off-by: Hendrik Wuethrich --- target/i386/cpu.c | 33 +++-- target/i386/cpu.h | 2 ++ 2 files changed, 33 insertions(+), 2 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index cd06744451..6262665294 100

[PATCH] hw/net/smc91c111: Don't allow data register access to overrun buffer

For accesses to the 91c111 data register, the address within the packet's data frame is determined by a combination of the pointer register and the offset used to access the data register, so that you can access data at effectively wider than byte width. The pointer register's pointer field is 11

Re: [PATCH 0/3] hw/net/smc91c111: Fix potential array overflows

On Fri, 28 Feb 2025 at 17:48, Peter Maydell wrote: > > This patchset fixes some potential array overflows in the > smc91c111 ethernet device model, including the one found in > https://gitlab.com/qemu-project/qemu/-/issues/2742 > > There are two classes of bugs: > * we accept packet numbers from

Re: [PATCH] gitlab: use --refetch in check-patch/check-dco jobs

Daniel P. Berrangé writes: > When gitlab initializes the repo checkout for a CI job, it will have > done a shallow clone with only partial history. Periodically the objects > that are omitted cause trouble with the check-patch/check-dco jobs. This > is exhibited as reporting strange errors being

Re: [BUG, RFC] cpr-transfer: qxl guest driver crashes after migration

On 2/28/25 8:35 PM, Andrey Drobyshev wrote: > On 2/28/25 8:20 PM, Steven Sistare wrote: >> On 2/28/2025 1:13 PM, Steven Sistare wrote: >>> On 2/28/2025 12:39 PM, Andrey Drobyshev wrote: Hi all, We've been experimenting with cpr-transfer migration mode recently and have discovere

Re: [BUG, RFC] cpr-transfer: qxl guest driver crashes after migration

On 2/28/25 8:20 PM, Steven Sistare wrote: > On 2/28/2025 1:13 PM, Steven Sistare wrote: >> On 2/28/2025 12:39 PM, Andrey Drobyshev wrote: >>> Hi all, >>> >>> We've been experimenting with cpr-transfer migration mode recently and >>> have discovered the following issue with the guest QXL driver: >>>

[RFC PATCH] gitlab: add a new build_unit job to track build size

We want to reduce the total number of build units in the system to get on our way to a single binary. It will help to have some numbers so lets add a job to gitlab to track our progress. Signed-off-by: Alex Bennée Cc: Pierrick Bouvier Cc: Philippe Mathieu-Daudé Cc: Richard Henderson --- .gitl

[PATCH v6 5/6] target/i386: Update EPYC-Genoa for Cache property, perfmon-v2, RAS and SVM feature bits

Found that some of the cache properties are not set correctly for EPYC models. l1d_cache.no_invd_sharing should not be true. l1i_cache.no_invd_sharing should not be true. L2.self_init should be true. L2.inclusive should be true. L3.inclusive should not be true. L3.no_invd_sharing should be true.

Re: [BUG, RFC] cpr-transfer: qxl guest driver crashes after migration

On 2/28/2025 1:13 PM, Steven Sistare wrote: On 2/28/2025 12:39 PM, Andrey Drobyshev wrote: Hi all, We've been experimenting with cpr-transfer migration mode recently and have discovered the following issue with the guest QXL driver: Run migration source: EMULATOR=/path/to/emulator ROOTFS=/pat

Re: [PATCH] hw/net: ftgmac100: copy eth_hdr for alignment

On Thu, Feb 27, 2025 at 9:54 PM Andrew Jeffery wrote: > Hi Patrick, > > On Thu, 2025-02-27 at 15:42 +, Patrick Venture wrote: > > eth_hdr requires 2 byte alignment > > > > Signed-off-by: Patrick Venture > > --- > > hw/net/ftgmac100.c | 15 --- > > 1 file changed, 12 insertions(+

Re: [PATCH] hw/i386/ovmf: check if ovmf is supported before calling ovmf parsing code

On Fri, Feb 28, 2025 at 10:34 PM Ani Sinha wrote: > > Currently call to x86_firmware_configure() -> pc_system_parse_ovmf_flash() > happens only when SEV is enabled. Fortunately, X86_FW_OVMF is turned on > automatically when SEV is enabled and therefore, we never end up calling > pc_system_parse_o

Re: [BUG, RFC] cpr-transfer: qxl guest driver crashes after migration

On 2/28/2025 12:39 PM, Andrey Drobyshev wrote: Hi all, We've been experimenting with cpr-transfer migration mode recently and have discovered the following issue with the guest QXL driver: Run migration source: EMULATOR=/path/to/emulator ROOTFS=/path/to/image QMPSOCK=/var/run/alma8qmp-src.sock

[PATCH v6 2/6] target/i386: Update EPYC-Rome CPU model for Cache property, RAS, SVM feature bits

Found that some of the cache properties are not set correctly for EPYC models. l1d_cache.no_invd_sharing should not be true. l1i_cache.no_invd_sharing should not be true. L2.self_init should be true. L2.inclusive should be true. L3.inclusive should not be true. L3.no_invd_sharing should be true.

[PATCH v6 1/6] target/i386: Update EPYC CPU model for Cache property, RAS, SVM feature bits

Found that some of the cache properties are not set correctly for EPYC models. l1d_cache.no_invd_sharing should not be true. l1i_cache.no_invd_sharing should not be true. L2.self_init should be true. L2.inclusive should be true. L3.inclusive should not be true. L3.no_invd_sharing should be true.

[PATCH v6 4/6] target/i386: Add feature that indicates WRMSR to BASE reg is non-serializing

Add the CPUID bit indicates that a WRMSR to MSR_FS_BASE, MSR_GS_BASE, or MSR_KERNEL_GS_BASE is non-serializing. CPUID_Fn8021_EAX BitFeature description 1 FsGsKernelGsBaseNonSerializing. WRMSR to FS_BASE, GS_BASE and KernelGSbase are non-serializing. Link: https://www.amd.com/

[PATCH v6 3/6] target/i386: Update EPYC-Milan CPU model for Cache property, RAS, SVM feature bits

Found that some of the cache properties are not set correctly for EPYC models. l1d_cache.no_invd_sharing should not be true. l1i_cache.no_invd_sharing should not be true. L2.self_init should be true. L2.inclusive should be true. L3.inclusive should not be true. L3.no_invd_sharing should be true.

[PATCH 2/3] hw/net/smc91c111: Sanitize packet length on tx

When the smc91c111 transmits a packet, it must read a control byte which is at the end of the data area and CRC. However, we don't sanitize the length field in the packet buffer, so if the guest sets the length field to something large we will try to read past the end of the packet data buffer whe

[PATCH 1/3] hw/net/smc91c111: Sanitize packet numbers

The smc91c111 uses packet numbers as an index into its internal s->data[][] array. Valid packet numbers are between 0 and 3, but the code does not generally check this, and there are various places where the guest can hand us an arbitrary packet number and cause an out-of-bounds access to the data

[PATCH 3/3] hw/net/smc91c111: Use MAX_PACKET_SIZE instead of magic numbers

Now we have a constant for the maximum packet size, we can use it to replace various hardcoded 2048 values. Signed-off-by: Peter Maydell --- hw/net/smc91c111.c | 8 +--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/hw/net/smc91c111.c b/hw/net/smc91c111.c index 23ca99f926a..4

[PATCH 0/3] hw/net/smc91c111: Fix potential array overflows

This patchset fixes some potential array overflows in the smc91c111 ethernet device model, including the one found in https://gitlab.com/qemu-project/qemu/-/issues/2742 There are two classes of bugs: * we accept packet numbers from the guest, but we were not validating that they were in range

[BUG, RFC] cpr-transfer: qxl guest driver crashes after migration

Hi all, We've been experimenting with cpr-transfer migration mode recently and have discovered the following issue with the guest QXL driver: Run migration source: > EMULATOR=/path/to/emulator > ROOTFS=/path/to/image > QMPSOCK=/var/run/alma8qmp-src.sock > > $EMULATOR -enable-kvm \ > -machine

Re: [PATCH 13/25] tests/tcg: fix constraints in test-i386-adcox

On 2/28/25 03:35, Alex Bennée wrote: Richard Henderson writes: On 2/26/25 06:03, Alex Bennée wrote: Clang complains: clang -O2 -m64 -mcx16 /home/alex/lsrc/qemu.git/tests/tcg/i386/test-i386-adcox.c -o test-i386-adcox -static /home/alex/lsrc/qemu.git/tests/tcg/i386/test-i386-adcox.c:32:

Re: [PATCH] include/exec/memop.h: Expand comment for MO_ATOM_SUBALIGN

On 2/28/25 02:32, Peter Maydell wrote: Expand the example in the comment documenting MO_ATOM_SUBALIGN, to be clearer about the atomicity guarantees it represents. Signed-off-by: Peter Maydell --- include/exec/memop.h | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) Reviewed-by:

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