On Mon, Feb 10, 2025 at 5:25 PM Sahil Siddiq wrote:
>
> Hi,
>
> On 2/10/25 7:53 PM, Eugenio Perez Martin wrote:
> > On Mon, Feb 10, 2025 at 11:58 AM Sahil Siddiq wrote:
> >> On 2/6/25 8:47 PM, Sahil Siddiq wrote:
> >>> On 2/6/25 12:42 PM, Eugenio Perez Martin wrote:
> On Thu, Feb 6, 2025 at
On virt machine, enable CPU hotplug feature has_hotpluggable_cpus. For
hot-added CPUs, there is socket-id/core-id/thread-id property set,
arch_id can be caculated from these properties. So that cpu slot can be
searched from its arch_id.
Co-developed-by: Xianglai Li
Signed-off-by: Bibo Mao
---
h
Cédric Le Goater writes:
> On 2/6/25 14:14, Cédric Le Goater wrote:
>> Depending on the configuration of the host and VM, a passthrough
>> device may generate recurring DMA mapping errors at runtime. In such
>> cases, reporting the issue once is sufficient.
>>
>> We have already the warn/error_re
Markus Armbruster writes:
> Daniel P. Berrangé writes:
>
>> Hi Markus,
>>
>> These patches seem to have got lost/delayed along the way. Are
>> you able to send a pull for them soon ?
>
> My bad! Will send them out a.s.a.p. Thanks for the reminder!
It's in master now.
Paolo Bonzini writes:
> On 2/10/25 10:59, Zhao Liu wrote:
>> On Thu, Feb 06, 2025 at 12:15:14PM +0100, Paolo Bonzini wrote:
>>> Not a major change but, as a small but significant step in creating
>>> qdev bindings, show how pl011_create can be written without "unsafe"
>>> calls (apart from conv
On 24/01/25 02:56PM, Jonathan Cameron wrote:
On Thu, 23 Jan 2025 10:39:02 +0530
Vinayak Holikatti wrote:
Hi Vinayak,
Thanks for your patch! Good to add support for this.
Various comments inline, but all fairly minor things.
thanks,
Jonathan
CXL spec 3.1 section 8.2.9.9.5.3 describes
Add some properties such as socket_id, core_id, thread_id and node_id
on LoongArch CPU object.
Co-developed-by: Xianglai Li
Signed-off-by: Bibo Mao
---
target/loongarch/cpu.c | 9 +
target/loongarch/cpu.h | 4
2 files changed, 13 insertions(+)
diff --git a/target/loongarch/cpu.c b
On Fri, Feb 07, 2025 at 11:16:23AM +0100, Paolo Bonzini wrote:
> Date: Fri, 7 Feb 2025 11:16:23 +0100
> From: Paolo Bonzini
> Subject: [PATCH 12/12] rust: pl011: convert pl011_create to safe Rust
> X-Mailer: git-send-email 2.48.1
>
> Not a major change but, as a small but significant step in cre
Implement cpu plug interface, and cold-plug cpu uses plug interface
when cpu object is created.
Co-developed-by: Xianglai Li
Signed-off-by: Bibo Mao
---
hw/loongarch/virt.c| 88 --
target/loongarch/cpu.c | 1 +
2 files changed, 78 insertions(+), 11 d
On Fri, Feb 07, 2025 at 11:16:22AM +0100, Paolo Bonzini wrote:
> Date: Fri, 7 Feb 2025 11:16:22 +0100
> From: Paolo Bonzini
> Subject: [PATCH 11/12] rust: chardev, qdev: add bindings to
> qdev_prop_set_chr
> X-Mailer: git-send-email 2.48.1
>
> Because the argument to the function is an Owned, t
> +unsafe impl ObjectType for IRQState {
> +type Class = ObjectClass;
> +const TYPE_NAME: &'static CStr =
> +unsafe { CStr::from_bytes_with_nul_unchecked(bindings::TYPE_IRQ) };
> +}
> +qom_isa!(IRQState: Object);
This is necessary for Owned<>, though IRQState has been defined in C.
Implement cpu unplug interfaces including virt_cpu_unplug_request()
and virt_cpu_unplug().
Co-developed-by: Xianglai Li
Signed-off-by: Bibo Mao
---
hw/loongarch/virt.c | 58 +
1 file changed, 58 insertions(+)
diff --git a/hw/loongarch/virt.c b/hw/loo
Add topological relationships for Loongarch VCPU and initialize
topology member variables.
On LoongArch system there is socket/core/thread topo information,
physical CPU id is calculated from CPU topo, every topo sub-field is
aligned by power of 2. So it is different from logical cpu index.
Co-de
On LoongArch virt machine, ACPI GED hardware is used for CPU hotplug
handler, here CPU hotplug support feature is added based on GED handler,
also CPU scan and reject method is added about CPU device in DSDT table.
Co-developed-by: Xianglai Li
Signed-off-by: Bibo Mao
---
hw/loongarch/Kconfig
LoongArch cpu hotplug is based on ACPI GED device, it depends on
patchset where TYPE_HOTPLUG_HANDLER interface is added in ipi and extioi
interrupt controller class for cpu hotplug event notification.
https://lore.kernel.org/qemu-devel/0d920309-c7ba-48d8-b46d-04ac1e38e...@linaro.org/T/#t
It can
Add basic cpu hotplug interface framework, cpu hotplug interface is
stub function and only framework is added here.
Co-developed-by: Xianglai Li
Signed-off-by: Bibo Mao
---
hw/loongarch/virt.c| 29 +
target/loongarch/cpu.c | 13 +
target/loongarch/cpu
On Fri, Feb 07, 2025 at 11:16:20AM +0100, Paolo Bonzini wrote:
> Date: Fri, 7 Feb 2025 11:16:20 +0100
> From: Paolo Bonzini
> Subject: [PATCH 09/12] rust: bindings for MemoryRegionOps
> X-Mailer: git-send-email 2.48.1
>
> Signed-off-by: Paolo Bonzini
> ---
> rust/hw/char/pl011/src/device.rs
On Fri, Feb 07, 2025 at 11:16:18AM +0100, Paolo Bonzini wrote:
> Date: Fri, 7 Feb 2025 11:16:18 +0100
> From: Paolo Bonzini
> Subject: [PATCH 07/12] rust: qdev: switch from legacy reset to Resettable
> X-Mailer: git-send-email 2.48.1
>
> Signed-off-by: Paolo Bonzini
> ---
> meson.build
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/10.0 for any
user-visible changes.
signature.asc
Description: PGP signature
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/10.0 for any
user-visible changes.
signature.asc
Description: PGP signature
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/10.0 for any
user-visible changes.
signature.asc
Description: PGP signature
The previous default value of sn is UI64_NULL which would cause the
cookie of nd_interleave_set be '0' and the "invalid interleave-set
-cookie" failure in label validation.
As many users maybe not know how to set a unique sn for cxl-type3
device and perhaps be confuesd by the failure of label vali
The previous default value of sn is UI64_NULL which would cause the
cookie of nd_interleave_set be '0' and the "invalid interleave-set
-cookie" failure in label validation.
As many users maybe not know how to set a unique sn for cxl-type3
device and perhaps be confuesd by the failure of label vali
On 2/10/25 14:59, Philippe Mathieu-Daudé wrote:
On 10/2/25 23:10, Richard Henderson wrote:
On 2/10/25 13:29, Philippe Mathieu-Daudé wrote:
Have the CPUClass::disas_set_info() callback set the
disassemble_info::endian field.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/cpu.c | 10 +++
On 2/10/25 12:53, Tom Lendacky wrote:
> On 2/7/25 17:33, Kim Phillips wrote:
>> The Allowed SEV Features feature allows the host kernel to control
>> which SEV features it does not want the guest to enable [1].
>>
>> This has to be explicitly opted-in by the user because it has the
>> ability to br
On 10/2/25 23:10, Richard Henderson wrote:
On 2/10/25 13:29, Philippe Mathieu-Daudé wrote:
Have the CPUClass::disas_set_info() callback set the
disassemble_info::endian field.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/cpu.c | 10 +++---
1 file changed, 3 insertions(+), 7 dele
Am 10. Februar 2025 14:26:00 UTC schrieb "Philippe Mathieu-Daudé"
:
>On 6/2/25 22:58, Bernhard Beschow wrote:
>>
>>
>> Am 6. Februar 2025 17:32:31 UTC schrieb Peter Maydell
>> :
>>> On Tue, 4 Feb 2025 at 09:21, Bernhard Beschow wrote:
The implementation just allows Linux to deter
Am 10. Februar 2025 17:30:01 UTC schrieb Peter Maydell
:
>On Tue, 4 Feb 2025 at 09:21, Bernhard Beschow wrote:
>>
>> As a first step, implement the bare minimum: CPUs, RAM, interrupt controller,
>> serial. All other devices of the A53 memory map are represented as
>> TYPE_UNIMPLEMENTED_DEVICE,
All CPUClass implementating disas_set_info() must set the
disassemble_info::endian value.
Ensure that by setting %endian to BFD_ENDIAN_UNKNOWN before
calling the CPUClass::disas_set_info() handler, then asserting
%endian is not BFD_ENDIAN_UNKNOWN after the call.
This allows removing the target_wo
Have the CPUClass::disas_set_info() callback always set\
the disassemble_info::endian field.
Reviewed-by: Thomas Huth
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
target/ppc/cpu_init.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/ppc/cpu_init.c b/tar
Have the CPUClass::disas_set_info() callback set the
disassemble_info::endian field.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
Reviewed-by: Richard Henderson
---
target/xtensa/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/xtensa/cpu.c b/target/xtensa/c
Have the CPUClass::disas_set_info() callback set the
disassemble_info::endian field.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
Reviewed-by: Richard Henderson
---
target/mips/cpu.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/mips/cp
Have the CPUClass::disas_set_info() callback set the
disassemble_info::endian field.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
Reviewed-by: Richard Henderson
---
target/riscv/cpu.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/target/riscv/cpu.c b/target/ris
Have the CPUClass::disas_set_info() callback set the
disassemble_info::endian field for big-endian targets.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
Reviewed-by: Richard Henderson
---
target/hppa/cpu.c | 1 +
target/m68k/cpu.c | 1 +
target/openrisc/cpu.c | 1 +
t
Have the CPUClass::disas_set_info() callback set the
disassemble_info::endian field.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
Reviewed-by: Richard Henderson
---
target/sh4/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
inde
Have the CPUClass::disas_set_info() callback set the
disassemble_info::endian field for little-endian targets.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
Reviewed-by: Richard Henderson
---
target/alpha/cpu.c | 1 +
target/avr/cpu.c | 1 +
target/hexagon/cpu.c |
Since v2:
- Addressed Richard comments, tricore not disingenuously modified.
Since v1:
- Addressed Thomas & Richard comments
Targets are aware of their endianness. No need for a global
target_words_bigendian() call in disas/ where we call the
CPUClass::disas_set_info() handler which already updat
Have the CPUClass::disas_set_info() callback set the
disassemble_info::endian field.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
target/arm/cpu.c | 10 +++---
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index
Have the CPUClass::disas_set_info() callback set the
disassemble_info::endian field.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
Reviewed-by: Richard Henderson
---
target/microblaze/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/microblaze/cpu.c b/target/
On 2/10/25 13:29, Philippe Mathieu-Daudé wrote:
All CPUClass implementations must implement disas_set_info()
which sets the disassemble_info::endian value.
Ensure that by:
1/ assert disas_set_info() handler is not NULL
Can we do that earlier than here?
@@ -61,15 +60,11 @@ void disas_initial
On 2/10/25 13:29, Philippe Mathieu-Daudé wrote:
Have the CPUClass::disas_set_info() callback set the
disassemble_info::endian field.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
---
target/riscv/cpu.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/target/risc
On 2/10/25 13:29, Philippe Mathieu-Daudé wrote:
Have the CPUClass::disas_set_info() callback set the
disassemble_info::endian field.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
---
target/xtensa/cpu.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/xtensa/
On 2/10/25 13:29, Philippe Mathieu-Daudé wrote:
Have the CPUClass::disas_set_info() callback always set\
the disassemble_info::endian field.
Reviewed-by: Thomas Huth
Signed-off-by: Philippe Mathieu-Daudé
---
target/ppc/cpu_init.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/
On 2/10/25 13:29, Philippe Mathieu-Daudé wrote:
Have the CPUClass::disas_set_info() callback set the
disassemble_info::endian field.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
---
target/sh4/cpu.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/sh4/cpu.c
On 2/10/25 13:29, Philippe Mathieu-Daudé wrote:
Have theCPUClass::disas_set_info() callback set the
disassemble_info::endian field.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
---
target/mips/cpu.c | 3 +++
1 file changed, 3 insertions(+)
Reviewed-by: Richard Henderson
On 2/10/25 13:29, Philippe Mathieu-Daudé wrote:
Have the CPUClass::disas_set_info() callback set the
disassemble_info::endian field.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
---
target/microblaze/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/microbla
On 2/10/25 13:29, Philippe Mathieu-Daudé wrote:
Have the CPUClass::disas_set_info() callback set the
disassemble_info::endian field.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/cpu.c | 10 +++---
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git a/target/arm/cpu.c b/ta
On 10/2/25 22:54, Richard Henderson wrote:
On 2/10/25 13:29, Philippe Mathieu-Daudé wrote:
@@ -35,6 +35,11 @@ static const gchar *tricore_gdb_arch_name(CPUState
*cs)
return "tricore";
}
+static void tricore_cpu_disas_set_info(CPUState *cpu,
disassemble_info *info)
+{
+ info->endian
On 25/1/25 18:01, Philippe Mathieu-Daudé wrote:
Philippe Mathieu-Daudé (24):
cpus: Restrict cpu_has_work() to system emulation
cpus: Un-inline cpu_has_work()
cpus: Introduce SysemuCPUOps::has_work() handler
target/alpha: Move has_work() from CPUClass to SysemuCPUOps
target/arm: Mo
On 22/1/25 10:30, Philippe Mathieu-Daudé wrote:
Philippe Mathieu-Daudé (10):
hw/core/generic-loader: Do not open-code cpu_set_pc()
gdbstub: Clarify no more than @gdb_num_core_regs can be accessed
cpus: Cache CPUClass early in instance_init() handler
cpus: Prefer cached CpuClass over
On 2/10/25 13:29, Philippe Mathieu-Daudé wrote:
Have theCPUClass::disas_set_info() callback set the
disassemble_info::endian field for big-endian targets.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
---
target/hppa/cpu.c | 1 +
target/m68k/cpu.c | 1 +
target/openr
On 2/10/25 13:29, Philippe Mathieu-Daudé wrote:
@@ -35,6 +35,11 @@ static const gchar *tricore_gdb_arch_name(CPUState *cs)
return "tricore";
}
+static void tricore_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
+{
+info->endian = BFD_ENDIAN_LITTLE;
+}
While this is no
On Thu, Feb 06, 2025 at 10:20:09AM +0300, Vladimir Sementsov-Ogievskiy wrote:
> > ---
> > qapi/block-export.json | 10 ++
> > include/block/nbd.h| 6 +++---
>
> [..]
>
> > @@ -52,6 +57,10 @@
> > #
> > # @addr: Address on which to listen.
> > #
> > +# @handshak
On 2/10/25 13:36, Philippe Mathieu-Daudé wrote:
I'll amend to the description:
---
Note, since cpu-common.c is in meson's common_ss[] source set, we
must define cpu_exec_class_post_init() in cpu-target.c (which is
in the specific_ss[] source set) to have CONFIG_USER_ONLY defined.
---
Excellent
On 27/1/25 08:50, Philippe Mathieu-Daudé wrote:
On 26/1/25 13:31, Richard Henderson wrote:
On 1/25/25 09:01, Philippe Mathieu-Daudé wrote:
diff --git a/cpu-target.c b/cpu-target.c
index 98e9e7cc4a1..778f622b07a 100644
--- a/cpu-target.c
+++ b/cpu-target.c
@@ -230,6 +230,14 @@ void cpu_class_ini
Have the CPUClass::disas_set_info() callback set the
disassemble_info::endian field.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
---
target/sh4/cpu.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index e3c2aea1a64..9d3e6cb2fd7 10
Have the CPUClass::disas_set_info() callback set the
disassemble_info::endian field.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
---
target/xtensa/cpu.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index efbfe73fcfb..bc170
Have the CPUClass::disas_set_info() callback set the
disassemble_info::endian field.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
---
target/microblaze/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 13d194cef88
Have the CPUClass::disas_set_info() callback set the
disassemble_info::endian field for little-endian targets.
Note, there was no disas_set_info() handler registered
for the TriCore target, so we implement one.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
---
target/alpha/cpu
All CPUClass implementations must implement disas_set_info()
which sets the disassemble_info::endian value.
Ensure that by:
1/ assert disas_set_info() handler is not NULL
2/ set %endian to BFD_ENDIAN_UNKNOWN before calling the
CPUClass::disas_set_info() handler, then assert %endian
is not B
Have the CPUClass::disas_set_info() callback always set\
the disassemble_info::endian field.
Reviewed-by: Thomas Huth
Signed-off-by: Philippe Mathieu-Daudé
---
target/ppc/cpu_init.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 25e835d
Have the CPUClass::disas_set_info() callback set the
disassemble_info::endian field.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
---
target/mips/cpu.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 0b267d2e507..f6d247b530f 1
Have the CPUClass::disas_set_info() callback set the
disassemble_info::endian field for big-endian targets.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
---
target/hppa/cpu.c | 1 +
target/m68k/cpu.c | 1 +
target/openrisc/cpu.c | 1 +
target/s390x/cpu.c| 1 +
targ
Have the CPUClass::disas_set_info() callback set the
disassemble_info::endian field.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/cpu.c | 10 +++---
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 94f1c55622b..68b3a9d3ab0 100644
Have the CPUClass::disas_set_info() callback set the
disassemble_info::endian field.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
---
target/riscv/cpu.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 3d4bd157d2c..b39a
Missing review: patch #3
Since v1:
- Addressed Thomas & Richard comments
Targets are aware of their endianness. No need for a global
target_words_bigendian() call in disas/ where we call the
CPUClass::disas_set_info() handler which already update
disassemble_info fields. Specify the target endian
On 27/1/25 14:57, Thomas Huth wrote:
On 27/01/2025 12.54, Philippe Mathieu-Daudé wrote:
Have the CPUClass::disas_set_info() callback set the
disassemble_info::endian field.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/targe
Do not explain why VFIO_PLATFORM devices are user_creatable,
have them inherit TYPE_DYNAMIC_SYS_BUS_DEVICE, to make explicit
that they can optionally be plugged on TYPE_PLATFORM_BUS_DEVICE.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Alexander Graf
Message-
From: Peter Maydell
The SMC91C111 includes an MMU Command register which permits
the guest to remove entries from the RX FIFO. The datasheet
does not specify what happens if the guest tries to do this
when the FIFO is already empty; there are no status registers
containing error bits which might
The archive used in test_microblaze_s3adsp1800.py (testing a
big-endian target) contains a big-endian kernel. Rename using
the _BE suffix.
Similarly, the archive in test_microblazeel_s3adsp1800 (testing
a little-endian target) contains a little-endian kernel. Rename
using _LE suffix.
These change
Using the auto_create_sdcard feature without SD Bus is irrelevant.
Reviewed-by: Thomas Huth
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20250204200934.65279-8-phi...@linaro.org>
---
system/vl.c | 16
1 file changed, 16 insertions(+)
diff --git a/system/vl.c b/system/vl.
Commit f0ec14c78c4 ("tests/avocado: Fix console data loss") fixed
QEMUMachine's problem with console, we don't need to use the sleep()
kludges.
Suggested-by: Thomas Huth
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
Reviewed-by: Richard Henderson
Message-Id: <20250206131052.30
Invert the 'no_sdcard' logic, renaming it as the more explicit
"auto_create_sdcard". Machines are supposed to create a SD Card
drive when this flag is set. In many cases it doesn't make much
sense (as boards don't expose SD Card host controller), but this
is patch only aims to expose that nonsense;
opentitan_machine_init() calls get_system_memory(),
which is declared in "exec/address-spaces.h". Include
it in order to avoid when refactoring unrelated headers:
hw/riscv/opentitan.c:83:29: error: call to undeclared function
'get_system_memory'
83 | MemoryRegion *sys_mem = get_system_
From: Bernhard Beschow
Makes the code less sensitive regarding changes in the class hierarchy which
will be performed in the next patch.
Signed-off-by: Bernhard Beschow
Reviewed-by: Philippe Mathieu-Daudé
Message-ID: <20250127094129.15941-1-shen...@gmail.com>
Signed-off-by: Philippe Mathieu-Da
Make microblaze tests a bit more generic.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
Message-Id: <20250206131052.30207-14-phi...@linaro.org>
---
tests/functional/test_microblaze_s3adsp1800.py | 7 +--
tests/functional/test_microblazeel_s3adsp1800.py | 7 +--
2 file
When multiple QOM types are registered in the same file,
it is simpler to use the the DEFINE_TYPES() macro. In
particular because type array declared with such macro
are easier to review.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Alexander Graf
Reviewed-b
On 25/1/25 19:13, Philippe Mathieu-Daudé wrote:
Philippe Mathieu-Daudé (9):
hw/sysbus: Use sizeof(BusState) in main_system_bus_create()
hw/sysbus: Declare QOM types using DEFINE_TYPES() macro
hw/sysbus: Introduce TYPE_DYNAMIC_SYS_BUS_DEVICE
hw/vfio: Have VFIO_PLATFORM devices inherit
A number of machines create an if=sd drive by default even though
they lack an SD bus, and therefore cannot use the drive.
This drive is created when the machine sets flag
@auto_create_sdcard.
See for example running HMP "info block" on the HPPA C3700 machine:
$ qemu-system-hppa -M C3700 -moni
MachineClass::auto_create_sdcard is only useful to automatically
create a SD card, attach a IF_SD block drive to it and plug the
card onto a SD bus. None of the RISCV machines modified by this
commit try to use the IF_SD interface.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
M
Because the legacy Xen backend devices can optionally be plugged on the
TYPE_PLATFORM_BUS_DEVICE, have it inherit TYPE_DYNAMIC_SYS_BUS_DEVICE.
Remove the implicit TYPE_XENSYSDEV instance_size.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alexander Graf
Tested-by: Bernhard Beschow
Reviewed
MachineClass::auto_create_sdcard is only useful to automatically
create a SD card, attach a IF_SD block drive to it and plug the
card onto a SD bus. None of the ARM machines modified by this
commit try to use the IF_SD interface.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
Mes
Replace the DEVICE_NATIVE_ENDIAN MemoryRegionOps by a pair
of DEVICE_LITTLE_ENDIAN / DEVICE_BIG_ENDIAN.
Add the "little-endian" property to select the device
endianness, defaulting to little endian.
Set the proper endianness on the single machine using the
device.
Signed-off-by: Philippe Mathieu-D
Have the MicroblazeMachine class being common to both
MicroblazeBigEndianMachine and MicroblazeLittleEndianMachine
classes. Move the xmaton and ballerina tests to the parent class.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
Message-Id: <20250206131052.30207-16-phi...@linaro.o
MachineClass::no_sdcard is initialized as false by default.
To catch all uses, convert it to a tri-state, having the
current default (false) becoming AUTO.
No logical change intended.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
Message-Id: <20250204200934.65279-2-phi...@linar
Because the TPM TIS sysbus device can be optionally plugged on the
TYPE_PLATFORM_BUS_DEVICE, have it inherit TYPE_DYNAMIC_SYS_BUS_DEVICE.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Alexander Graf
Reviewed-by: Clément Mathieu--Drif
Reviewed-by: Stefan Berg
Replace the DEVICE_NATIVE_ENDIAN MemoryRegionOps by a pair
of DEVICE_LITTLE_ENDIAN / DEVICE_BIG_ENDIAN.
Add the "little-endian" property to select the device
endianness, defaulting to little endian.
Set the proper endianness for each machine using the device.
Reviewed-by: Richard Henderson
Signed
Because the RAM FB device can be optionally plugged on the
TYPE_PLATFORM_BUS_DEVICE, have it inherit TYPE_DYNAMIC_SYS_BUS_DEVICE.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Alexander Graf
Reviewed-by: Clément Mathieu--Drif
Message-Id: <20250125181343.5915
Update MachineClass::no_sdcard default implicit AUTO
initialization to explicit OFF. This flag is consumed
in system/vl.c::qemu_disable_default_devices(). Use
this place to assert we don't have anymore AUTO state.
In hw/ppc/e500.c we add the ppce500_machine_class_init()
method to initialize once a
From: Zhao Liu
Currently, neither i386 nor ARM have real hardware support for per-
thread cache, and there is no clear demand for this specific cache
topology.
Additionally, since ARM even can't support this special cache topology
in device tree, it is unnecessary to support it at this moment, e
When a property value is static (not provided by QMP or CLI),
error shouldn't happen, otherwise it is a programming error.
Therefore simplify and use &error_abort as this can't fail.
Reported-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Anton Johansson
Message-Id: <2
Because the network eTSEC device can be optionally plugged on the
TYPE_PLATFORM_BUS_DEVICE, have it inherit TYPE_DYNAMIC_SYS_BUS_DEVICE.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Alexander Graf
Reviewed-by: Clément Mathieu--Drif
Tested-by: Bernhard Besch
Rather than using the obscure system_bus_info.instance_size,
directly use sizeof(BusState).
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Alexander Graf
Reviewed-by: Clément Mathieu--Drif
Message-Id: <20250125181343.59151-2-phi...@linaro.org>
---
hw/core/sys
Do not explain why _X86_IOMMU devices are user_creatable,
have them inherit TYPE_DYNAMIC_SYS_BUS_DEVICE, to explicit
they can optionally be plugged on TYPE_PLATFORM_BUS_DEVICE.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Alexander Graf
Reviewed-by: Clément
Replace the DEVICE_NATIVE_ENDIAN MemoryRegionOps by a pair
of DEVICE_LITTLE_ENDIAN / DEVICE_BIG_ENDIAN.
Add the "little-endian" property to select the device
endianness, defaulting to little endian.
Set the proper endianness on the single machine using the
device.
Reviewed-by: Richard Henderson
S
Some TYPE_SYS_BUS_DEVICEs can be optionally dynamically
plugged on the TYPE_PLATFORM_BUS_DEVICE.
Rather than sometimes noting that with comment around
the 'user_creatable = true' line in each DeviceRealize
handler, introduce an abstract TYPE_DYNAMIC_SYS_BUS_DEVICE
class.
Signed-off-by: Philippe Ma
The following changes since commit 54e91d1523b412b4cff7cb36c898fa9dc133e886:
Merge tag 'pull-qapi-2025-02-10-v2' of https://repo.or.cz/qemu/armbru into
staging (2025-02-10 10:47:31 -0500)
are available in the Git repository at:
https://github.com/philmd/qemu.git tags/hw-misc-202
From: Phil Dennis-Jordan
This changes replaces the use of an explicit literal constant for
the APIC base address mask with the existing symbolic constant
intended for this purpose.
Additionally, we remove the comment about not being able to
re-enable the APIC after disabling it. This is no longe
sprintf() is deprecated on Darwin since macOS 13.0 / XCode 14.1.
Using qemu_hexdump_line() both fixes the deprecation warning and
simplifies the code base.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Stefan Berger
[rth: Keep the linebreaks every 16 bytes]
Signed-off-by: Richard Henderson
Replace the DEVICE_NATIVE_ENDIAN MemoryRegionOps by a pair
of DEVICE_LITTLE_ENDIAN / DEVICE_BIG_ENDIAN.
Add the "little-endian" property to select the device
endianness, defaulting to little endian.
Set the proper endianness for each machine using the device.
Reviewed-by: Richard Henderson
Signed
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