Re: [PATCH 5/5] tests/functional: Introduce a bletchley machine test

2025-01-29 Thread Thomas Huth
On 29/01/2025 08.18, Cédric Le Goater wrote: Use do_test_arm_aspeed_openbmc() to run the latest OpenBMC firmware build of the bletchley BMC. Signed-off-by: Cédric Le Goater --- tests/functional/meson.build | 2 ++ tests/functional/test_arm_aspeed_bletchley.py | 24 +

Re: [PATCH 0/5] tests/functional: Update Aspeed OpenBMC images

2025-01-29 Thread Cédric Le Goater
On 1/30/25 04:03, Andrew Jeffery wrote: On Wed, 2025-01-29 at 08:19 +0100, Cédric Le Goater wrote: On 1/29/25 00:29, Andrew Jeffery wrote: Hi Cédric, On Tue, 2025-01-28 at 22:41 +0100, Cédric Le Goater wrote: Hello, This series updates the OpenBMC firmware images to the latest version for ex

Re: [PATCH] hw/i386/pc: Fix crash that occurs when introspecting TYPE_PC_MACHINE machines

2025-01-29 Thread Thomas Huth
On 29/01/2025 08.11, Philippe Mathieu-Daudé wrote: Hi Thomas, On 17/1/25 20:21, Thomas Huth wrote: QEMU currently crashes when you try to inspect the machines based on TYPE_PC_MACHINE for their properties:   $ echo '{ "execute": "qmp_capabilities" }   { "execute": "qom-list-properties"

Re: [PATCH 1/5] tests/functional: Introduce a new test routine for OpenBMC images

2025-01-29 Thread Thomas Huth
On 29/01/2025 17.28, Cédric Le Goater wrote: On 1/29/25 08:58, Thomas Huth wrote: On 29/01/2025 08.18, Cédric Le Goater wrote: The OpenBMC images currently used by QEMU to test the Aspeed machines are rather old. To prepare an update to the latest builds, we need to adjust the console patterns.

Re: [PATCH v2 3/4] target/riscv: add RVA23U64 profile

2025-01-29 Thread Daniel Henrique Barboza
On 1/28/25 10:22 PM, Alistair Francis wrote: On Wed, Jan 15, 2025 at 5:02 AM Daniel Henrique Barboza wrote: Add RVA23U64 as described in [1]. Add it as a child of RVA22U64 since all RVA22U64 mandatory extensions are also present in RVA23U64. What's left then is to list the mandatory extensi

Re: [PATCH v1 17/18] hw/arm/aspeed_ast27x0: Add HACE support for AST2700

2025-01-29 Thread Andrew Jeffery
On Tue, 2025-01-21 at 15:04 +0800, Jamin Lin wrote: > The HACE controller between AST2600 and AST2700 are almost identical. > The HACE controller registers base address starts at 0x1207_ and > its alarm interrupt is connected to GICINT4. > > Signed-off-by: Jamin Lin Reviewed-by: Andrew Jeffe

Re: [PATCH v1 16/18] hw/misc/aspeed_hace: Add AST2700 support

2025-01-29 Thread Andrew Jeffery
On Tue, 2025-01-21 at 15:04 +0800, Jamin Lin wrote: > Introduce a new ast2700 class to support AST2700. > > Signed-off-by: Jamin Lin Reviewed-by: Andrew Jeffery

Re: [PATCH v1 14/18] hw/arm/aspeed: Add SoC and Machine Support for AST2700 A1

2025-01-29 Thread Andrew Jeffery
On Tue, 2025-01-21 at 15:04 +0800, Jamin Lin wrote: > The memory map for AST2700 A1 remains compatible with AST2700 A0. > However, the IRQ mapping has been updated for AST2700 A1, with GIC > interrupts > now ranging from 192 to 201. Add a new IRQ map table for AST2700 A1. > > Introduce "aspeed_mac

Re: [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two levels of INTC controllers for AST2700 A1

2025-01-29 Thread Andrew Jeffery
On Tue, 2025-01-21 at 15:04 +0800, Jamin Lin wrote: > The design of INTC controllers has significantly changed in AST2700 A1. > > There are a total of 480 interrupt sources in AST2700 A1. For interrupt > numbers > from 0 to 127, they can route directly to PSP, SSP, and TSP. Due to the > limitatio

Re: [PATCH v1 11/18] hw/misc/aspeed_scu: Add Support for AST2700/AST2750 A1 Silicon Revisions

2025-01-29 Thread Andrew Jeffery
On Tue, 2025-01-21 at 15:04 +0800, Jamin Lin wrote: > Added new definitions for AST2700_A1_SILICON_REV and > AST2750_A1_SILICON_REV to > identify the A1 silicon revisions. > > Update "aspeed_ast2700_scu_reset" to set the silicon_rev field in the > SCU > registers. > > Signed-off-by: Jamin Lin >

Re: [PATCH v1 06/18] hw/intc/aspeed: Introduce AspeedINTCIRQ structure to save the irq index and register address

2025-01-29 Thread Andrew Jeffery
On Tue, 2025-01-21 at 15:04 +0800, Jamin Lin wrote: > The INTC0 controller supports GICINT128 to GICINT136, mapping 1:1 to > input and > output IRQs 0 to 8. Previously, the formula "address & 0x0f00" was > used to > derive the IRQ index numbers. > > However, the INTC0 controller also supports GICI

Re: [PATCH v1 02/18] hw/intc/aspeed: Support different memory region ops

2025-01-29 Thread Andrew Jeffery
On Tue, 2025-01-21 at 15:04 +0800, Jamin Lin wrote: > The previous implementation set the "aspeed_intc_ops" struct, > containing read > and write callbacks, to be used when I/O is performed on the INTC > region. > Both "aspeed_intc_read" and "aspeed_intc_write" callback functions > were used > for

Re: [PATCH v1 01/18] hw/intc/aspeed: Rename INTC to INTC0

2025-01-29 Thread Andrew Jeffery
On Tue, 2025-01-21 at 15:04 +0800, Jamin Lin wrote: > The design of the INTC has significant changes in the AST2700 A1. In > the > AST2700 A0, there was one INTC controller, whereas in the AST2700 A1, > there were two INTC controllers: INTC0 (CPU DIE) and INTC1 (I/O DIE). > > The previous INTC mod

Re: [PATCH v1 01/18] hw/intc/aspeed: Rename INTC to INTC0

2025-01-29 Thread Andrew Jeffery
On Wed, 2025-01-29 at 18:03 +0100, Cédric Le Goater wrote: > On 1/21/25 08:04, Jamin Lin wrote: > > The design of the INTC has significant changes in the AST2700 A1. > > In the > > AST2700 A0, there was one INTC controller, whereas in the AST2700 > > A1, > > there were two INTC controllers: INTC0 (

Re: [PATCH 0/5] tests/functional: Update Aspeed OpenBMC images

2025-01-29 Thread Andrew Jeffery
On Wed, 2025-01-29 at 08:19 +0100, Cédric Le Goater wrote: > On 1/29/25 00:29, Andrew Jeffery wrote: > > Hi Cédric, > > > > On Tue, 2025-01-28 at 22:41 +0100, Cédric Le Goater wrote: > > > Hello, > > > > > > This series updates the OpenBMC firmware images to the latest > > > version > > > for exi

Re: [PATCH] net/slirp: introduce slirp_os_socket to stay compatible with libslirp past 4.8.0

2025-01-29 Thread Samuel Thibault
Hello, Samuel Thibault, le jeu. 10 oct. 2024 01:06:47 +0200, a ecrit: > Michael Tokarev, le sam. 05 oct. 2024 10:07:53 +0300, a ecrit: > > libslirp introduced new typedef after 4.8.0, slirp_os_socket, which > > is defined to SOCKET on windows, which, in turn, is a 64bit number. > > qemu uses int,

Re: [PATCH v3] tcg/optimize: optimize TSTNE using smask and zmask

2025-01-29 Thread Richard Henderson
On 1/29/25 05:11, Paolo Bonzini wrote: Generalize the existing optimization of "TSTNE x,sign" and "TSTNE x,-1". This can be useful for example in the i386 frontend, which will generate tests of zero-extended registers against 0x. Ironically, on x86 hosts this is a very slight pessimizati

Re: [PATCH 20/21] hw/i2c: Import TCA6416 emulation from Xilinx

2025-01-29 Thread Corey Minyard
I'm not sure about ownership here, but from an I2C point of view this all looks ok. Reviewed-by: Corey Minyard On Mon, Jan 20, 2025 at 12:43 PM Bernhard Beschow wrote: > > Xilinx QEMU implements a TCA6416 device model which may be useful for the > broader QEMU community, so upstream it. In the

Re: [PATCH 4/4] target/hppa: Implement space register hashing for 64-bit HP-UX

2025-01-29 Thread Richard Henderson
On 1/29/25 07:30, Helge Deller wrote: Subject: [PATCH] target/hppa: Implement space register hashing for 64-bit HP-UX The Linux kernel turns space-register hashing off unconditionally at bootup. That code was provided by HP at the beginning of the PA-RISC Linux porting effort, and I don't know

Re: CXL emulation on aarch64

2025-01-29 Thread Itaru Kitayama
> On Jan 30, 2025, at 2:16, Jonathan Cameron > wrote: > > On Wed, 29 Jan 2025 10:14:34 +0900 > Itaru Kitayama wrote: > >>> On Jan 22, 2025, at 23:07, Jonathan Cameron >>> wrote: >>> >>> On Fri, 17 Jan 2025 09:43:11 + >>> Jonathan Cameron via wrote: >>> On Fri, 17 Jan 2025 10:1

Re: [RFC PATCH QEMU 0/3] cxl/plugins: Hotness Monitoring Unit with 'real' data.

2025-01-29 Thread Pierrick Bouvier
Hi Jonathan, On 1/29/25 02:29, Jonathan Cameron wrote: On Tue, 28 Jan 2025 12:04:19 -0800 Pierrick Bouvier wrote: On 1/27/25 02:20, Jonathan Cameron wrote: On Fri, 24 Jan 2025 12:55:52 -0800 Pierrick Bouvier wrote: Hi Jonathan, thanks for posting this. It's a creative usage of plugins

Re: [PULL 00/36] target-arm queue

2025-01-29 Thread Stefan Hajnoczi
Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/10.0 for any user-visible changes. signature.asc Description: PGP signature

Re: [PULL v3 00/49] i386, Rust changes for 2025-01-24

2025-01-29 Thread Stefan Hajnoczi
Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/10.0 for any user-visible changes. signature.asc Description: PGP signature

Re: [PATCH] hw/i386/pc: Fix crash that occurs when introspecting TYPE_PC_MACHINE machines

2025-01-29 Thread Michael S. Tsirkin
On Wed, Jan 29, 2025 at 08:00:40AM +0100, Thomas Huth wrote: > On 17/01/2025 20.21, Thomas Huth wrote: > > QEMU currently crashes when you try to inspect the machines based on > > TYPE_PC_MACHINE for their properties: > > > > $ echo '{ "execute": "qmp_capabilities" } > > { "execute": "

Re: [PATCH v3 0/8] qapi-go: add generator for Golang interfaces

2025-01-29 Thread Victor Toso
Hi, On Thu, Jan 16, 2025 at 09:59:52PM +, Daniel P. Berrangé wrote: > On Fri, Jan 10, 2025 at 11:49:38AM +0100, Victor Toso wrote: > > I've pushed this series in my gitlab fork: > > https://gitlab.com/victortoso/qapi-go/ > > > > The fork contains some tests, including tests that were generate

Re: [PATCH 5/6] Revert "tcg/cputlb: remove other-cpu capability from TLB flushing"

2025-01-29 Thread BALATON Zoltan
On Wed, 29 Jan 2025, Igor Mammedov wrote: 1) This reverts commit 30933c4fb4f3df95ae44c4c3c86a5df049852c01. ("tcg/cputlb: remove other-cpu capability from TLB flushing") The commit caused a regression which went unnoticed due to affected being disabled by default (DEBUG_TLB_GATE 0) Previous patc

Re: [PATCH 0/4] intel_iommu: Reset vIOMMU after all the rest of devices

2025-01-29 Thread Eric Auger
Hi Peter, On 1/23/25 6:57 PM, Peter Xu wrote: > On Thu, Jan 23, 2025 at 10:16:23AM +0100, Eric Auger wrote: >> I haven't seen any follow-up on this series. Is anyone still looking at >> this issue? Peter gave some guidance about the way to rework the reset >> chain. Is it still up to date? > I d

Re: [PATCH] migration: ram block cpr blockers

2025-01-29 Thread Steven Sistare
On 1/17/2025 6:57 PM, Peter Xu wrote: On Fri, Jan 17, 2025 at 02:10:14PM -0500, Steven Sistare wrote: On 1/17/2025 1:16 PM, Peter Xu wrote: On Fri, Jan 17, 2025 at 09:46:11AM -0800, Steve Sistare wrote: +/* + * Return true if ram contents would be lost during CPR. + * Return false for ram_devi

Re: [PATCH 09/21] hw/arm/fsl-imx8mp: Add PCIe support

2025-01-29 Thread BALATON Zoltan
On Tue, 28 Jan 2025, Bernhard Beschow wrote: Am 28. Januar 2025 14:33:14 UTC schrieb Peter Maydell : On Mon, 20 Jan 2025 at 20:38, Bernhard Beschow wrote: Linux checks for the PLLs in the PHY to be locked, so implement a model emulating that. Signed-off-by: Bernhard Beschow diff --git a

Re: [PATCH v2] tests/functional: Extend PPC 40p test with Linux boot

2025-01-29 Thread Philippe Mathieu-Daudé
On 29/1/25 18:34, BALATON Zoltan wrote: On Wed, 29 Jan 2025, Cédric Le Goater wrote: Fetch the cdrom image for the IBM 6015 PReP PowerPC machine hosted on the Juneau Linux Users Group site, boot and check Linux version. Not related to this patch just by the way, I've noticed that the rom imag

Re: Call for GSoC internship project ideas

2025-01-29 Thread Stefano Garzarella
+Cc rust-vmm ML, since in past years we have used QEMU as an umbrella project for rust-vmm ideas for GSoC. Thanks, Stefano On Tue, 28 Jan 2025 at 17:17, Stefan Hajnoczi wrote: > > Dear QEMU and KVM communities, > QEMU will apply for the Google Summer of Code internship > program again this year.

Re: [PATCH v2 05/34] target/arm: Rename FPST_FPCR_AH* to FPST_AH*

2025-01-29 Thread Philippe Mathieu-Daudé
On 29/1/25 02:38, Richard Henderson wrote: Signed-off-by: Richard Henderson --- target/arm/tcg/translate.h | 14 +++--- target/arm/tcg/translate-a64.c | 8 target/arm/tcg/translate-sve.c | 8 3 files changed, 15 insertions(+), 15 deletions(-) Reviewed-by: P

Re: [PATCH v2 04/34] target/arm: Rename FPST_FPCR_F16_A64 to FPST_A64_F16

2025-01-29 Thread Philippe Mathieu-Daudé
On 29/1/25 02:38, Richard Henderson wrote: Signed-off-by: Richard Henderson --- target/arm/tcg/translate.h | 8 ++--- target/arm/tcg/translate-a64.c | 44 +++ target/arm/tcg/translate-sve.c | 66 +- 3 files changed, 59 insertions(+),

Re: [PATCH v2 03/34] target/arm: Rename FPST_FPCR_F16_A32 to FPST_A32_F16

2025-01-29 Thread Philippe Mathieu-Daudé
On 29/1/25 02:38, Richard Henderson wrote: Signed-off-by: Richard Henderson --- target/arm/tcg/translate.h | 6 +++--- target/arm/tcg/translate-vfp.c | 24 2 files changed, 15 insertions(+), 15 deletions(-) Reviewed-by: Philippe Mathieu-Daudé

Re: [PATCH v2 02/34] target/arm: Rename FPST_FPCR_A64 to FPST_A64

2025-01-29 Thread Philippe Mathieu-Daudé
On 29/1/25 02:38, Richard Henderson wrote: Signed-off-by: Richard Henderson --- target/arm/tcg/translate.h | 8 +-- target/arm/tcg/translate-a64.c | 78 +-- target/arm/tcg/translate-sme.c | 4 +- target/arm/tcg/translate-sve.c | 98 +

Re: [PATCH v2 01/34] target/arm: Rename FPST_FPCR_A32 to FPST_A32

2025-01-29 Thread Philippe Mathieu-Daudé
On 29/1/25 02:38, Richard Henderson wrote: Signed-off-by: Richard Henderson --- target/arm/tcg/translate.h | 6 ++-- target/arm/tcg/translate-vfp.c | 54 +- 2 files changed, 30 insertions(+), 30 deletions(-) Reviewed-by: Philippe Mathieu-Daudé

Re: [PATCH v2 16/34] target/arm: Simplify DO_VFP_cmp in vfp_helper.c

2025-01-29 Thread Philippe Mathieu-Daudé
On 29/1/25 02:38, Richard Henderson wrote: Pass ARMFPStatusFlavour index instead of fp_status[FOO]. Signed-off-by: Richard Henderson --- target/arm/vfp_helper.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) Reviewed-by: Philippe Mathieu-Daudé

Re: [PATCH v2 15/34] target/arm: Simplify fp_status indexing in mve_helper.c

2025-01-29 Thread Philippe Mathieu-Daudé
On 29/1/25 02:38, Richard Henderson wrote: Select on index instead of pointer. No functional change. Signed-off-by: Richard Henderson --- target/arm/tcg/mve_helper.c | 40 + 1 file changed, 14 insertions(+), 26 deletions(-) Reviewed-by: Philippe Mathieu-

Re: [PATCH v2 14/34] target/arm: Remove fp_status_a32

2025-01-29 Thread Philippe Mathieu-Daudé
On 29/1/25 02:38, Richard Henderson wrote: Replace with fp_status[FPST_A32]. As this was the last of the old structures, we can remove the anonymous union and struct. Signed-off-by: Richard Henderson --- target/arm/cpu.h| 7 +-- target/arm/cpu.c| 2 +- target/arm/vfp_

Re: [PATCH v2 10/34] target/arm: Remove ah_fp_status

2025-01-29 Thread Philippe Mathieu-Daudé
On 29/1/25 02:38, Richard Henderson wrote: Replace with fp_status[FPST_AH]. Signed-off-by: Richard Henderson --- target/arm/cpu.h| 3 +-- target/arm/cpu.c| 6 +++--- target/arm/vfp_helper.c | 6 +++--- 3 files changed, 7 insertions(+), 8 deletions(-) Reviewed-by: Philippe

Re: [PATCH v2 13/34] target/arm: Remove fp_status_a64

2025-01-29 Thread Philippe Mathieu-Daudé
On 29/1/25 02:38, Richard Henderson wrote: Replace with fp_status[FPST_A64]. Signed-off-by: Richard Henderson --- target/arm/cpu.h| 1 - target/arm/cpu.c| 2 +- target/arm/tcg/sme_helper.c | 2 +- target/arm/tcg/vec_helper.c | 10 +- target/arm/vfp_helpe

Re: [PATCH v2 12/34] target/arm: Remove fp_status_f16_a32

2025-01-29 Thread Philippe Mathieu-Daudé
On 29/1/25 02:38, Richard Henderson wrote: Replace with fp_status[FPST_A32_F16]. Signed-off-by: Richard Henderson --- target/arm/cpu.h| 1 - target/arm/cpu.c| 2 +- target/arm/tcg/vec_helper.c | 4 ++-- target/arm/vfp_helper.c | 14 +++--- 4 files ch

Re: [PATCH v2 11/34] target/arm: Remove fp_status_f16_a64

2025-01-29 Thread Philippe Mathieu-Daudé
On 29/1/25 02:38, Richard Henderson wrote: Replace with fp_status[FPST_A64_F16]. Signed-off-by: Richard Henderson --- target/arm/cpu.h| 1 - target/arm/cpu.c| 2 +- target/arm/tcg/sme_helper.c | 2 +- target/arm/tcg/vec_helper.c | 8 target/arm/vfp_hel

Re: [PATCH v2 09/34] target/arm: Remove ah_fp_status_f16

2025-01-29 Thread Philippe Mathieu-Daudé
On 29/1/25 02:38, Richard Henderson wrote: Replace with fp_status[FPST_AH_F16]. Signed-off-by: Richard Henderson --- target/arm/cpu.h| 3 +-- target/arm/cpu.c| 2 +- target/arm/vfp_helper.c | 10 +- 3 files changed, 7 insertions(+), 8 deletions(-) Reviewed-by: P

Re: [PATCH v2 08/34] target/arm: Remove standard_fp_status

2025-01-29 Thread Philippe Mathieu-Daudé
On 29/1/25 02:38, Richard Henderson wrote: Replace with fp_status[FPST_STD]. Signed-off-by: Richard Henderson --- target/arm/cpu.h| 1 - target/arm/cpu.c| 8 target/arm/tcg/mve_helper.c | 28 ++-- target/arm/tcg/vec_helper.c | 4 +

Re: [PATCH v2 07/34] target/arm: Remove standard_fp_status_f16

2025-01-29 Thread Philippe Mathieu-Daudé
On 29/1/25 02:38, Richard Henderson wrote: Replace with fp_status[FPST_STD_F16]. Signed-off-by: Richard Henderson --- target/arm/cpu.h| 1 - target/arm/cpu.c| 4 ++-- target/arm/tcg/mve_helper.c | 24 target/arm/vfp_helper.c | 8 -

Re: [PATCH v2] tests/functional: Extend PPC 40p test with Linux boot

2025-01-29 Thread BALATON Zoltan
On Wed, 29 Jan 2025, Cédric Le Goater wrote: Fetch the cdrom image for the IBM 6015 PReP PowerPC machine hosted on the Juneau Linux Users Group site, boot and check Linux version. Not related to this patch just by the way, I've noticed that the rom image is loaded from within hw/pci-host/raven

Re: [PATCH v2 06/34] target/arm: Introduce CPUARMState.vfp.fp_status[]

2025-01-29 Thread Philippe Mathieu-Daudé
On 29/1/25 02:38, Richard Henderson wrote: Move ARMFPStatusFlavour to cpu.h with which to index this array. For now, place the array in an anonymous union with the existing structures. Adjust the order of the existing structures to match the enum. Simplify fpstatus_ptr() using the new array.

Re: CXL emulation on aarch64

2025-01-29 Thread Jonathan Cameron via
On Wed, 29 Jan 2025 10:14:34 +0900 Itaru Kitayama wrote: > > On Jan 22, 2025, at 23:07, Jonathan Cameron > > wrote: > > > > On Fri, 17 Jan 2025 09:43:11 + > > Jonathan Cameron via wrote: > > > >> On Fri, 17 Jan 2025 10:13:41 +0900 > >> Itaru Kitayama wrote: > >> > On Jan 16, 2

Re: [PATCH v1 01/18] hw/intc/aspeed: Rename INTC to INTC0

2025-01-29 Thread Cédric Le Goater
On 1/21/25 08:04, Jamin Lin wrote: The design of the INTC has significant changes in the AST2700 A1. In the AST2700 A0, there was one INTC controller, whereas in the AST2700 A1, there were two INTC controllers: INTC0 (CPU DIE) and INTC1 (I/O DIE). The previous INTC model only supported the AST27

Re: [PATCH] hw/arm/virt: Support larger highmem MMIO regions

2025-01-29 Thread Matt Ochs
On Jan 29, 2025, at 2:25 AM, Philippe Mathieu-Daudé wrote: Hi Matthew, On 28/1/25 17:02, Matthew R. Ochs wrote: The MMIO region size required to support virtualized environments with large PCI BAR regions can exceed the hardcoded limit configured in QEMU. For example, a VM with multiple NVIDIA

Re: [PATCH v2] tests/functional: Add a ppc64 mac99 test

2025-01-29 Thread BALATON Zoltan
On Tue, 28 Jan 2025, Cédric Le Goater wrote: The test sequence boots from disk a mac99 machine in 64-bit mode, in which case the CPU is a PPC 970. The buildroot rootfs is built with config : BR2_powerpc64=y BR2_powerpc_970=y and the kernel with the g5 deconfig. Reviewed-by: Thomas Huth Signe

Re: [PATCH] tests/functional: Add a ppc64 mac99 test

2025-01-29 Thread BALATON Zoltan
On Tue, 28 Jan 2025, Cédric Le Goater wrote: +    self.vm.set_console() + +    self.vm.add_args('-kernel', linux_path, + '-append', 'root=/dev/sda', + '-drive', f'file={rootfs_path},format=raw', + '-net', 'nic,model=s

Re: [PATCH 1/5] tests/functional: Introduce a new test routine for OpenBMC images

2025-01-29 Thread Cédric Le Goater
On 1/29/25 08:58, Thomas Huth wrote: On 29/01/2025 08.18, Cédric Le Goater wrote: The OpenBMC images currently used by QEMU to test the Aspeed machines are rather old. To prepare an update to the latest builds, we need to adjust the console patterns. Introduce a new routine to preserve the curre

[PULL 25/42] migration: cpr-transfer documentation

2025-01-29 Thread Fabiano Rosas
From: Steve Sistare Add documentation for the cpr-transfer migration mode. Signed-off-by: Steve Sistare Reviewed-by: Peter Xu Link: https://lore.kernel.org/r/1736967650-129648-25-git-send-email-steven.sist...@oracle.com [add -machine memory-backend=ram0] Signed-off-by: Fabiano Rosas --- doc

[PULL 29/42] migration: Avoid two src-downtime-end tracepoints for postcopy

2025-01-29 Thread Fabiano Rosas
From: Peter Xu Postcopy can trigger this tracepoint twice, while only the 1st one is valid. Avoid triggering the 2nd tracepoint just like what we do with recording the total downtime. Signed-off-by: Peter Xu Tested-by: Jiri Denemark Reviewed-by: Juraj Marcin Link: https://lore.kernel.org/r/2

[PULL 36/42] migration: Notify COMPLETE once for postcopy

2025-01-29 Thread Fabiano Rosas
From: Peter Xu Postcopy invokes qemu_savevm_state_complete_precopy() twice, that means it'll invoke COMPLETE notify twice.. also twice the tracepoints that marking precopy complete. Move that notification (along with the tracepoint) out to the caller, so that postcopy will only notify once right

[PULL 30/42] migration: Drop inactivate_disk param in qemu_savevm_state_complete*

2025-01-29 Thread Fabiano Rosas
From: Peter Xu This parameter is only used by one caller, which is the genuine precopy complete path (migration_completion_precopy). The parameter was introduced in a1fbe750fd ("migration: Fix race of image locking between src and dst") to make sure the inactivate will happen before EOF to make

[PULL 13/42] migration: incoming channel

2025-01-29 Thread Fabiano Rosas
From: Steve Sistare Extend the -incoming option to allow an @MigrationChannel to be specified. This allows channels other than 'main' to be described on the command line, which will be needed for CPR. Signed-off-by: Steve Sistare Acked-by: Peter Xu Link: https://lore.kernel.org/r/1736967650-1

[PULL 11/42] hostmem-shm: preserve for cpr

2025-01-29 Thread Fabiano Rosas
From: Steve Sistare Preserve memory-backend-shm memory objects during cpr-transfer. Signed-off-by: Steve Sistare Reviewed-by: Peter Xu Link: https://lore.kernel.org/r/1736967650-129648-11-git-send-email-steven.sist...@oracle.com Signed-off-by: Fabiano Rosas --- backends/hostmem-shm.c | 12 +

[PULL 27/42] migration: Do not construct JSON description if suppressed

2025-01-29 Thread Fabiano Rosas
From: Peter Xu QEMU machine has a property "suppress-vmdesc". When it is enabled, QEMU will stop attaching JSON VM description at the end of the precopy migration stream (postcopy is never affected because postcopy never attach that). However even if it's suppressed by the user, the source QEMU

[PULL 09/42] physmem: preserve ram blocks for cpr

2025-01-29 Thread Fabiano Rosas
From: Steve Sistare Save the memfd for ramblocks in CPR state, along with a name that uniquely identifies it. The block's idstr is not yet set, so it cannot be used for this purpose. Find the saved memfd in new QEMU when creating a block. If size of a resizable block is larger in new QEMU, ext

[PULL 16/42] migration: cpr-transfer save and load

2025-01-29 Thread Fabiano Rosas
From: Steve Sistare Add functions to create a QEMUFile based on a unix URI, for saving or loading, for use by cpr-transfer mode to preserve CPR state. Signed-off-by: Steve Sistare Reviewed-by: Peter Xu Link: https://lore.kernel.org/r/1736967650-129648-16-git-send-email-steven.sist...@oracle.c

[PULL 12/42] migration: enhance migrate_uri_parse

2025-01-29 Thread Fabiano Rosas
From: Steve Sistare Export migrate_uri_parse for use outside migration internals, and define a method migrate_is_uri that indicates when migrate_uri_parse should be used. Signed-off-by: Steve Sistare Reviewed-by: Peter Xu Link: https://lore.kernel.org/r/1736967650-129648-12-git-send-email-ste

[PULL 39/42] migration: Always set DEVICE state

2025-01-29 Thread Fabiano Rosas
From: Peter Xu DEVICE state was introduced back in 2017: https://lore.kernel.org/qemu-devel/20171020090556.18631-1-dgilb...@redhat.com/ Quote from Dave's cover letter, when the pre-switchover phase was enabled, the state transition looks like this: The precopy flow is: active->pre-switchov

[PULL 03/42] physmem: fix qemu_ram_alloc_from_fd size calculation

2025-01-29 Thread Fabiano Rosas
From: Steve Sistare qemu_ram_alloc_from_fd allocates space if file_size == 0. If non-zero, it uses the existing space and verifies it is large enough, but the verification was broken when the offset parameter was introduced. As a result, a file smaller than offset passes the verification and ca

[PULL 14/42] migration: SCM_RIGHTS for QEMUFile

2025-01-29 Thread Fabiano Rosas
From: Steve Sistare Define functions to put/get file descriptors to/from a QEMUFile, for qio channels that support SCM_RIGHTS. Maintain ordering such that put(A), put(fd), put(B) followed by get(A), get(fd), get(B) always succeeds. Other get orderings may succeed but are not guaranteed. Si

[PULL 15/42] migration: VMSTATE_FD

2025-01-29 Thread Fabiano Rosas
From: Steve Sistare Define VMSTATE_FD for declaring a file descriptor field in a VMStateDescription. Signed-off-by: Steve Sistare Reviewed-by: Peter Xu Link: https://lore.kernel.org/r/1736967650-129648-15-git-send-email-steven.sist...@oracle.com Signed-off-by: Fabiano Rosas --- include/migr

[PULL 22/42] tests/qtest: enhance migration channels

2025-01-29 Thread Fabiano Rosas
From: Steve Sistare Change the migrate_qmp and migrate_qmp_fail channels argument to a QObject type so the caller can manipulate the object before passing it to the helper. Define migrate_str_to_channel to aid such manipulation. Add a channels argument to migrate_incoming_qmp. Signed-off-by: St

[PULL 10/42] hostmem-memfd: preserve for cpr

2025-01-29 Thread Fabiano Rosas
From: Steve Sistare Preserve memory-backend-memfd memory objects during cpr-transfer. Signed-off-by: Steve Sistare Reviewed-by: Peter Xu Link: https://lore.kernel.org/r/1736967650-129648-10-git-send-email-steven.sist...@oracle.com Signed-off-by: Fabiano Rosas --- backends/hostmem-memfd.c |

[PULL 21/42] migration-test: defer connection

2025-01-29 Thread Fabiano Rosas
From: Steve Sistare Add an option to defer connection to the target monitor, needed by the cpr-transfer test. Signed-off-by: Steve Sistare Reviewed-by: Fabiano Rosas Link: https://lore.kernel.org/r/1736967650-129648-21-git-send-email-steven.sist...@oracle.com Signed-off-by: Fabiano Rosas ---

[PULL 02/42] backends/hostmem-shm: factor out allocation of "anonymous shared memory with an fd"

2025-01-29 Thread Fabiano Rosas
From: Steve Sistare Let's factor it out so we can reuse it. Signed-off-by: David Hildenbrand Signed-off-by: Steve Sistare Reviewed-by: Peter Xu Link: https://lore.kernel.org/r/1736967650-129648-2-git-send-email-steven.sist...@oracle.com Signed-off-by: Fabiano Rosas --- backends/hostmem-shm

[PULL 42/42] migration: refactor ram_save_target_page functions

2025-01-29 Thread Fabiano Rosas
From: Prasad Pandit Refactor ram_save_target_page legacy and multifd functions into one. Other than simplifying it, it frees 'migration_ops' object from usage, so it is expunged. Signed-off-by: Prasad Pandit Reviewed-by: Fabiano Rosas Message-ID: <20250127120823.144949-3-ppan...@redhat.com> Si

[PULL 28/42] migration: Optimize postcopy on downtime by avoiding JSON writer

2025-01-29 Thread Fabiano Rosas
From: Peter Xu postcopy_start() is the entry function that postcopy is destined to start. It also means QEMU source will not dump VM description, aka, the JSON writer is garbage now. We can leave that to be cleaned up when migration completes, however when with the JSON writer object being prese

[PULL 17/42] migration: cpr-transfer mode

2025-01-29 Thread Fabiano Rosas
From: Steve Sistare Add the cpr-transfer migration mode, which allows the user to transfer a guest to a new QEMU instance on the same host with minimal guest pause time, by preserving guest RAM in place, albeit with new virtual addresses in new QEMU, and by preserving device file descriptors. Pa

[PULL 31/42] migration: Synchronize all CPU states only for non-iterable dump

2025-01-29 Thread Fabiano Rosas
From: Peter Xu Do one shot cpu sync at qemu_savevm_state_complete_precopy_non_iterable(), instead of coding it separately in two places. Note that in the context of qemu_savevm_state_complete_precopy(), this patch is also an optimization for postcopy path, in that we can avoid sync cpu twice dur

[PULL 23/42] tests/qtest: assert qmp connected

2025-01-29 Thread Fabiano Rosas
From: Steve Sistare Assert that qmp_fd is valid when we communicate with the monitor. Suggested-by: Peter Xu Signed-off-by: Steve Sistare Link: https://lore.kernel.org/r/1736967650-129648-23-git-send-email-steven.sist...@oracle.com Signed-off-by: Fabiano Rosas --- tests/qtest/libqtest.c | 4

[PULL 38/42] migration: Cleanup qemu_savevm_state_complete_precopy()

2025-01-29 Thread Fabiano Rosas
From: Peter Xu Now qemu_savevm_state_complete_precopy() is never used in postcopy, clean it up as in_postcopy==false now unconditionally. Signed-off-by: Peter Xu Tested-by: Jiri Denemark Reviewed-by: Juraj Marcin Link: https://lore.kernel.org/r/20250114230746.3268797-14-pet...@redhat.com Sign

[PULL 37/42] migration: Unwrap qemu_savevm_state_complete_precopy() in postcopy

2025-01-29 Thread Fabiano Rosas
From: Peter Xu Postcopy invokes qemu_savevm_state_complete_precopy() twice for a long time, and that caused way too much confusions. Let's clean this up and make postcopy easier to read. It's actually fairly straightforward: postcopy starts with saving non-postcopiable iterables, then later it

[PULL 40/42] migration: Merge precopy/postcopy on switchover start

2025-01-29 Thread Fabiano Rosas
From: Peter Xu Now after all the cleanups, finally we can merge the switchover startup phase into one single function for precopy/postcopy. Signed-off-by: Peter Xu Tested-by: Jiri Denemark Reviewed-by: Juraj Marcin Link: https://lore.kernel.org/r/20250114230746.3268797-16-pet...@redhat.com Si

[PULL 35/42] migration: Take BQL slightly longer in postcopy_start()

2025-01-29 Thread Fabiano Rosas
From: Peter Xu This paves way for some follow up patch to modify migration states at the end of postcopy_start(), which should better be with the BQL so that there's no way of concurrent cancellation. So we'll do something slightly more with BQL but they're really trivial, hopefully nothing will

[PULL 19/42] tests/qtest: optimize migrate_set_ports

2025-01-29 Thread Fabiano Rosas
From: Steve Sistare Do not query connection parameters if all port numbers are known. This is more efficient, and also solves a problem for the cpr-transfer test. At the point where cpr-transfer calls migrate_qmp and migrate_set_ports, the monitor is not connected and queries are not allowed. P

[PULL 32/42] migration: Adjust postcopy bandwidth during switchover

2025-01-29 Thread Fabiano Rosas
From: Peter Xu Precopy uses unlimited bandwidth always during switchover, it makes sense because this is so critical and no one would like to throttle bandwidth during the VM blackout. OTOH, postcopy surprisingly didn't do that. There's one line that in the middle of the postcopy switchover it

[PULL 26/42] migration: Remove postcopy implications in should_send_vmdesc()

2025-01-29 Thread Fabiano Rosas
From: Peter Xu should_send_vmdesc() has a hack inside (which was not reflected in the function name) in that it tries to detect global postcopy state and that will affect the value to be returned. It's easier to keep the helper simple by only check the suppress-vmdesc property. Then: - On th

[PULL 41/42] migration: Trivial cleanup on JSON writer of vmstate_save()

2025-01-29 Thread Fabiano Rosas
From: Peter Xu Two small cleanups in the same section of vmstate_save(): - Check vmdesc before the "mixed null/non-null data in array" logic, to be crystal clear that it's only about the JSON writer, not the vmstate on its own in the migration stream. - Since we have is_null variable no

[PULL 08/42] migration: cpr-state

2025-01-29 Thread Fabiano Rosas
From: Steve Sistare CPR must save state that is needed after QEMU is restarted, when devices are realized. Thus the extra state cannot be saved in the migration channel, as objects must already exist before that channel can be loaded. Instead, define auxilliary state structures and vmstate descr

[PULL 33/42] migration: Adjust locking in migration_maybe_pause()

2025-01-29 Thread Fabiano Rosas
From: Peter Xu In migration_maybe_pause() QEMU may yield BQL before waiting for a semaphore. However it yields the BQL too early, which logically gives it chance for the main thread to quickly take the BQL and modify the state to CANCELLING. To avoid such race condition from happening at all, a

[PULL 20/42] tests/qtest: defer connection

2025-01-29 Thread Fabiano Rosas
From: Steve Sistare Add an option to defer making the connecting to the monitor and qtest sockets when calling qtest_init_with_env. The client makes the connection later by calling qtest_connect and qtest_qmp_handshake. Signed-off-by: Steve Sistare Reviewed-by: Peter Xu Link: https://lore.ke

[PULL 34/42] migration: Drop cached migration state in migration_maybe_pause()

2025-01-29 Thread Fabiano Rosas
From: Peter Xu I can't see why we must cache the state now after we avoided possible CANCEL race: that's the only thing I can think of that can modify the migration state concurrently with the migration thread itself. Make all the state updates to happen always, then we don't need to cache the s

[PULL 18/42] migration-test: memory_backend

2025-01-29 Thread Fabiano Rosas
From: Steve Sistare Allow each migration test to define its own memory backend, replacing the standard "-m " specification. Signed-off-by: Steve Sistare Reviewed-by: Fabiano Rosas Link: https://lore.kernel.org/r/1736967650-129648-18-git-send-email-steven.sist...@oracle.com Signed-off-by: Fabi

[PULL 01/42] migration: fix -Werror=maybe-uninitialized

2025-01-29 Thread Fabiano Rosas
From: Marc-André Lureau ../migration/savevm.c: In function ‘qemu_savevm_state_complete_precopy_non_iterable’: ../migration/savevm.c:1560:20: error: ‘ret’ may be used uninitialized [-Werror=maybe-uninitialized] 1560 | return ret; |^~~ Cc: Peter Xu Signed-

[PULL 06/42] memory: add RAM_PRIVATE

2025-01-29 Thread Fabiano Rosas
From: Steve Sistare Define the RAM_PRIVATE flag. In RAMBlock creation functions, if MAP_SHARED is 0 in the flags parameter, in a subsequent patch the implementation may still create a shared mapping if other conditions require it. Callers who specifically want a private mapping, eg for objects

[PULL 04/42] physmem: qemu_ram_alloc_from_fd extensions

2025-01-29 Thread Fabiano Rosas
From: Steve Sistare Extend qemu_ram_alloc_from_fd to support resizable ram, and define qemu_ram_resize_cb to clean up the API. Add a grow parameter to extend the file if necessary. However, if grow is false, a zero-sized file is always extended. Signed-off-by: Steve Sistare Link: https://lor

[PULL 24/42] migration-test: cpr-transfer

2025-01-29 Thread Fabiano Rosas
From: Steve Sistare Add a migration test for cpr-transfer mode. Defer the connection to the target monitor, else the test hangs because in cpr-transfer mode QEMU does not listen for monitor connections until we send the migrate command to source QEMU. To test -incoming defer, send a migrate inc

[PULL 07/42] machine: aux-ram-share option

2025-01-29 Thread Fabiano Rosas
From: Steve Sistare Allocate auxilliary guest RAM as an anonymous file that is shareable with an external process. This option applies to memory allocated as a side effect of creating various devices. It does not apply to memory-backend-objects, whether explicitly specified on the command line,

[PULL 05/42] physmem: fd-based shared memory

2025-01-29 Thread Fabiano Rosas
From: Steve Sistare Create MAP_SHARED RAMBlocks by mmap'ing a file descriptor rather than using MAP_ANON, so the memory can be accessed in another process by passing and mmap'ing the fd. This will allow CPR to support memory-backend-ram and memory-backend-shm objects, provided the user creates t

[PULL 00/42] Migration patches for 2025-01-29

2025-01-29 Thread Fabiano Rosas
The following changes since commit 7faf9d2f12ace4c1d04cf1a2b39334eef9a45f22: Merge tag 'pull-aspeed-20250127' of https://github.com/legoater/qemu into staging (2025-01-27 11:20:35 -0500) are available in the Git repository at: https://gitlab.com/farosas/qemu.git tags/migratio

Re: [PATCH 4/4] target/hppa: Implement space register hashing for 64-bit HP-UX

2025-01-29 Thread Helge Deller
Richard, thanks for your feedback! Can you please review the updated patch below which includes your suggestions. Additionally I've successfully tested it. Thanks in advance, Helge - Subject: [PATCH] target/hppa: Implement space register hashing for 64-bit HP-UX The Linux kernel t

Re: [PATCH v2 12/13] tests/acpi: virt: add a HEST table to aarch64 virt and update DSDT

2025-01-29 Thread Igor Mammedov
On Wed, 29 Jan 2025 09:04:18 +0100 Mauro Carvalho Chehab wrote: > DSDT has gained a GED device to notify errors: > > --- a/DSDT.dsl2025-01-28 09:38:15.155347858 +0100 > +++ b/DSDT.dsl2025-01-28 09:39:01.684836954 +0100 > @@ -9,9 +9,9 @@ > * > * Original Table Header: > *

Re: [PATCH v2 03/13] acpi/ghes: add a firmware file with HEST address

2025-01-29 Thread Igor Mammedov
On Wed, 29 Jan 2025 09:04:09 +0100 Mauro Carvalho Chehab wrote: > Store HEST table address at GPA, placing its content at > hest_addr_le variable. > > Signed-off-by: Mauro Carvalho Chehab > Reviewed-by: Jonathan Cameron > > While here, capitalize first letter on a comment about hardware_error

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