On 1/25/25 05:13, Alex Williamson wrote:
> On Sat, 25 Jan 2025 03:12:45 +0800
> Tomita Moeko wrote:
>
>> Both enable opregion option (x-igd-opregion) and legacy mode require
>> setting up OpRegion copy for IGD devices. Move x-igd-opregion handler
>> in vfio_realize() to vfio_probe_igd_config_quir
On 2025/01/24 19:01, Christian Schoenebeck wrote:
On Friday, January 24, 2025 6:12:06 AM CET Akihiko Odaki wrote:
coreaudio had names that are not conforming to QEMU codding style.
coreaudioVoiceOut also had some members that are prefixed with redundant
words like "output" or "audio".
Global nam
On 2025/01/24 18:39, Christian Schoenebeck wrote:
On Friday, January 24, 2025 6:12:04 AM CET Akihiko Odaki wrote:
coreaudio had unnecessary explicit casts and they had extra whitespaces
around them so remove them.
Signed-off-by: Akihiko Odaki
---
audio/coreaudio.m | 6 +++---
1 file changed
On Thu, Jan 23, 2025 at 7:52 PM Igor Mammedov wrote:
>
> On Thu, 23 Jan 2025 17:26:12 +0530
> Ani Sinha wrote:
>
> > commit 0788a56bd1ae3 ("i386: Make unversioned CPU models be aliases")
> > introduced 'default_cpu_version' for PCMachineClass. This created three
> > categories of CPU models:
> >
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/10.0 for any
user-visible changes.
signature.asc
Description: PGP signature
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/10.0 for any
user-visible changes.
signature.asc
Description: PGP signature
>with an error message indicating DMA mapping failed for the
passthrough >devices.
A correction - the message indicates UEFI failed to find a mapping for
the boot partition ("map: no mapping found"), not that DMA mapping
failed. But earlier EDK debug logs still show PCI host bridge resource
conf
Hi All,
This is an RFC mainly to seek feedback on the approach used, particularly
the aspect of how to get data from a TCG plugin into a device model.
Two options that we have tried
1. Socket over which the plugin sends data to an external server
(as seen here)
2. Register and manage a plugin f
Hi Jonathan,
thanks for posting this. It's a creative usage of plugins.
I think that your current approach, decoupling plugins, CHMU and device
model is a good thing.
I'm not familiar with CXL, but one question that comes to my mind is:
Is that mandatory to do this analysis during execution (
On Sat, 25 Jan 2025 03:12:45 +0800
Tomita Moeko wrote:
> Both enable opregion option (x-igd-opregion) and legacy mode require
> setting up OpRegion copy for IGD devices. Move x-igd-opregion handler
> in vfio_realize() to vfio_probe_igd_config_quirk() to elimate duplicate
> code. Finally we moved
On 1/24/25 13:10, Michael Clark wrote:
this metadata is based on x86-csv with numerous inaccuracies
fixed plus conversion of legacy instructions to a new LEX format.
this metadata has been fuzz-tested against the LLVM disassembler
for x86-64 with 64-bit ISA coverage in the order of ~99.9%.
addi
When receiving a guest mpcifc(4) or mpcifc(6) instruction without the T
bit set, treat this as a request to perform direct mapping instead of
address translation. In order to facilitate this, pin the entirety of
guest memory into the host iommu.
Pinning for the direct mapping case is handled via
Il ven 24 gen 2025, 20:05 Stefan Hajnoczi ha scritto:
> Hi Paolo,
> Please take a look at this failure and send a v2 pull request, if
> necessary:
>
> thread '' panicked at 'already borrowed',
> rust/qemu-api/libqemu_api.rlib.p/structured/cell.rs:450:5
> note: run with `RUST_BACKTRACE=1` environm
Specifying this bit in the guest CLP response indicates that the guest
can optionally choose to skip translation and instead use
identity-mapped operations.
Signed-off-by: Matthew Rosato
---
hw/s390x/s390-pci-vfio.c| 5 -
include/hw/s390x/s390-pci-clp.h | 1 +
2 files changed, 5 inse
This series introduces the concept of the relaxed translation requirement
for s390x guests in order to allow bypass of the guest IOMMU for more
efficient PCI passthrough.
With this series, QEMU can indicate to the guest that an IOMMU is not
strictly required for a zPCI device. This would subseque
On 1/21/25 06:23, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
target/s390x/s390x-internal.h | 2 ++
1 file changed, 2 insertions(+)
Reviewed-by: Richard Henderson
r~
From: Helge Deller
The following changes since commit 32a97c5d05c5deb54a42315d48cecf86cbeadaf4:
Merge tag 'pull-tcg-20250117' of https://gitlab.com/rth7680/qemu into staging
(2025-01-21 08:28:33 -0500)
are available in the Git repository at:
https://github.com/hdeller/qemu-hppa.git tags/h
From: Helge Deller
Commit 20f7b890173b ("hw/hppa: Reset vCPUs calling resettable_reset()")
broke booting the Linux kernel with initrd which may have been provided
on the command line. The problem is, that the mentioned commit zeroes
out initial registers which were preset with addresses for the L
From: Helge Deller
Allow up to 256 GB RAM, which is the maximum a rp8440 machine (the very
last 64-bit PA-RISC machine) physically supports.
Signed-off-by: Helge Deller
Reviewed-by: Richard Henderson
---
hw/hppa/hppa_hardware.h | 2 ++
hw/hppa/machine.c | 26 +++---
The negation step in the SVE FTMAD insn mustn't negate a NaN when
FPCR.AH is set. Pass FPCR.AH to the helper via the SIMD data field
and use that to determine whether to do the negation.
Signed-off-by: Peter Maydell
---
target/arm/tcg/sve_helper.c| 21 +++--
target/arm/tcg/t
On 1/22/25 01:30, Philippe Mathieu-Daudé wrote:
Directly call cpu_set_pc() instead of open-coding it.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/core/generic-loader.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/hw/core/generic-loader.c b/hw/core/generic-loader.c
Both enable opregion option (x-igd-opregion) and legacy mode require
setting up OpRegion copy for IGD devices. Move x-igd-opregion handler
in vfio_realize() to vfio_probe_igd_config_quirk() to elimate duplicate
code. Finally we moved all the IGD-related code into igd.c.
Signed-off-by: Tomita Moeko
Some devices, such as IGD, require device-specific quirks to be applied
to their pci config spaces. Currently, these quirks are either part of
BAR quirk, or being a part of vfio_realize(). Add a placeholder for pci
config quirks for moving the quirks to one place later.
Signed-off-by: Tomita Moeko
Based on experiments and reverse engineering about the mysterious IO
BAR4, it appears that the current quirk implementation is incorrect.
As discussed in a previous mail thread [1], current implementation
believes VBIOS is writing HPA of Data Stolen Memory (DSM) in GTT
entries, so it intercepts and
Though GTT Stolen Memory (GSM) is right below Data Stolen Memory (DSM)
in host address space, direct access to GSM is prohibited, and it is
not mapped to guest address space. Both host and guest accesses GSM
indirectly through the second half of MMIO BAR0 (GTTMMADR).
Guest firmware only need to re
The actual IO BAR4 write quirk in vfio_probe_igd_bar4_quirk() was
removed in previous change, leaving the function not matching its name,
so move it into the newly introduced vfio_config_quirk_setup(). There
is no functional change in this commit. If any failure occurs, the
function simply returns
The IO BAR4 of IGD devices contains a pair of 32-bit address/data
registers, MMIO_Index (0x0) and MMIO_Data (0x4), which provide access
to the MMIO BAR0 (GTTMMADR) from IO space. These registers are probably
only used by the VBIOS, and are not documented by intel. The observed
layout of MMIO_Index
On Fri, 24 Jan 2025 at 04:52, Paolo Bonzini wrote:
>
> The following changes since commit d6430c17d7113d3c38480dc34e59d00b0504e2f7:
>
> Merge tag 'pull-riscv-to-apply-20250119-1' of
> https://github.com/alistair23/qemu into staging (2025-01-19 08:55:46 -0500)
>
> are available in the Git reposi
Intended to support enabling in kernel. For now this is dumb and the data
made up. That will change in the near future.
Instantiates 3 instances within one CHMU with separate
interrupts.
Signed-off-by: Jonathan Cameron
---
include/hw/cxl/cxl.h| 1 +
include/hw/cxl/cxl_chmu.h | 154
On 1/21/25 06:23, Philippe Mathieu-Daudé wrote:
SysemuCPUOps::has_work() is similar to CPUClass::has_work(),
but only exposed on system emulation.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/core/sysemu-cpu-ops.h | 4
hw/core/cpu-system.c | 4
2 files changed,
On 1/21/25 06:23, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
Reviewed-by: Richard Henderson
r~
On 1/24/25 18:52, Philippe Mathieu-Daudé wrote:
On 22/1/25 19:09, del...@kernel.org wrote:
From: Helge Deller
Allow up to 256 GB RAM, which is the maximum a rp8440 machine (the very
last 64-bit PA-RISC machine) physically supports.
Signed-off-by: Helge Deller
---
hw/hppa/hppa_hardware.h |
Definitely not suggesting to install an invalid pointer anywhere. The
mapped pointer will still be valid for gmem for example, but the fault
isn't. We need to differenciate two things (1) virtual address mapping,
then (2) permission and accesses on the folios / pages of the mapping.
Here I think
On Wed, 2025-01-15 at 14:31 +0100, Shalini Chellathurai Saroja wrote:
> This commit adds the firmware control-program
> identifiers received from a KVM guest via the
> SCLP event type Control-Program Identification to QOM.
> A timestamp in which the data is received is also
> added to QOM.
>
> Exa
On Wed, 2025-01-15 at 14:31 +0100, Shalini Chellathurai Saroja wrote:
> This commit saves the state of CPI values in the guest and
> transfers this state during live migration of the guest.
IMO, using active voice and directly stating what is done is preferable.
Something like:
Register Control-P
On 24/1/25 18:50, Philippe Mathieu-Daudé wrote:
QOM types are now registered using as TypeInfo via DEFINE_TYPES()
or type_init(). Update TYPE_SH_SERIAL, removing the empty QOM
instance_init/finalize handlers.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/char/sh_serial.c | 23 +++--
On 1/24/25 18:45, Thomas Huth wrote:
The tacoma-bmc machine has recently been removed, so let's remove
it from the documentation now, too.
Fixes: 2b1b66e01f ("arm: Remove tacoma-bmc machine")
Signed-off-by: Thomas Huth
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
docs/system/arm/aspe
- Parity in realize / unrealize
- Define TypeInfo structure
Philippe Mathieu-Daudé (2):
hw/char/sh_serial: Delete fifo_timeout_timer in DeviceUnrealize
hw/char/sh_serial: Convert to TypeInfo
hw/char/sh_serial.c | 24 ++--
1 file changed, 14 insertions(+), 10 deletions(-)
Hi,
On 1/24/25 4:41 AM, Jason Wang wrote:
> On Fri, Jan 24, 2025 at 11:30 AM Jason Wang wrote:
>> On Fri, Jan 24, 2025 at 10:44 AM Duan, Zhenzhong
>> wrote:
>>>
>>>
-Original Message-
From: Eric Auger
Subject: Re: [PATCH] hw/virtio/vhost: Disable IOTLB callbacks when IOM
On 1/21/25 06:23, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
target/tricore/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Richard Henderson
r~
On 22/1/25 19:09, del...@kernel.org wrote:
From: Helge Deller
Allow up to 256 GB RAM, which is the maximum a rp8440 machine (the very
last 64-bit PA-RISC machine) physically supports.
Signed-off-by: Helge Deller
---
hw/hppa/hppa_hardware.h | 2 ++
hw/hppa/machine.c | 26
fifo_timeout_timer is created in the DeviceRealize handler,
not in the instance_init one. For parity, delete it in
DeviceUnrealize, rather than instance_finalize.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/char/sh_serial.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --
QOM types are now registered using as TypeInfo via DEFINE_TYPES()
or type_init(). Update TYPE_SH_SERIAL, removing the empty QOM
instance_init/finalize handlers.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/char/sh_serial.c | 23 +++
1 file changed, 11 insertions(+), 12 deleti
On 1/22/25 10:09, del...@kernel.org wrote:
From: Helge Deller
Allow up to 256 GB RAM, which is the maximum a rp8440 machine (the very
last 64-bit PA-RISC machine) physically supports.
Signed-off-by: Helge Deller
---
hw/hppa/hppa_hardware.h | 2 ++
hw/hppa/machine.c | 26
On 1/21/25 06:23, Philippe Mathieu-Daudé wrote:
diff --git a/hw/core/cpu-system.c b/hw/core/cpu-system.c
index 7b16bda2250..7f287984aa6 100644
--- a/hw/core/cpu-system.c
+++ b/hw/core/cpu-system.c
@@ -25,12 +25,8 @@
bool cpu_has_work(CPUState *cpu)
{
-if (cpu->cc->sysemu_ops->has_work
On 1/22/25 10:09, del...@kernel.org wrote:
From: Helge Deller
Commit 20f7b890173b ("hw/hppa: Reset vCPUs calling resettable_reset()")
broke booting the Linux kernel with initrd which may have been provided
on the command line. The problem is, that the mentioned commit zeroes
out initial register
Hi Zhenzhong,
On 1/24/25 3:44 AM, Duan, Zhenzhong wrote:
>
>> -Original Message-
>> From: Eric Auger
>> Subject: Re: [PATCH] hw/virtio/vhost: Disable IOTLB callbacks when IOMMU gets
>> disabled
>>
>> Hi Jason,
>>
>>
>> On 1/23/25 2:34 AM, Jason Wang wrote:
>>> On Wed, Jan 22, 2025 at 3:5
The tacoma-bmc machine has recently been removed, so let's remove
it from the documentation now, too.
Fixes: 2b1b66e01f ("arm: Remove tacoma-bmc machine")
Signed-off-by: Thomas Huth
---
docs/system/arm/aspeed.rst | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/docs/system
This is used inconjuction with the cache plugin (with port
parameter supplied) and the CXL Type 3 device with a hotness
monitoring unit (chmu-port parameter supplied).
It implements a very basic oracle with a counter per 4KiB page
and simple loop to find large counts. The hotlist length is
contro
We want to pass another flag that will be stored in MemTxAttrs. So pass
MemTxAttrs directly.
Signed-off-by: David Hildenbrand
---
hw/core/loader.c | 2 +-
hw/remote/vfio-user-obj.c | 2 +-
include/exec/memory.h | 5 +++--
system/memory_ldst.c.inc | 18 +-
system/
On 24/1/25 18:17, Richard Henderson wrote:
On 1/21/25 06:23, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
target/riscv/cpu.h | 9 +
target/riscv/internals.h | 3 ---
target/riscv/cpu.c | 8 +++-
3 files changed, 8 insertions(+), 12 deletio
We directly use fp_status_f16 in a handful of helpers that
are AArch32-specific; switch to fp_status_f16_a32 for these.
Signed-off-by: Peter Maydell
---
target/arm/tcg/vec_helper.c | 4 ++--
target/arm/vfp_helper.c | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/target
Please swap patch 1 and 2 and incorporate the changes of write_event_data
into this patch.
Reviewed-by: Nina Schoetterl-Glausch
See some minor nits below.
On Wed, 2025-01-15 at 14:31 +0100, Shalini Chellathurai Saroja wrote:
> This commit implements the SCLP event type Control-Program
> Identif
On 1/21/25 06:23, Philippe Mathieu-Daudé wrote:
Move has_work() from CPUClass to SysemuCPUOps, simplifying
xtensa_cpu_has_work() by directly using CPU env.
Signed-off-by: Philippe Mathieu-Daudé
---
target/xtensa/cpu.c | 12 +---
1 file changed, 5 insertions(+), 7 deletions(-)
Review
On 1/21/25 06:23, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
target/sparc/cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
Reviewed-by: Richard Henderson
r~
On 1/21/25 06:23, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
target/sh4/cpu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Richard Henderson
r~
Queued, thanks.
Paolo
This allows an external program to act as a hotness tracker.
Signed-off-by: Jonathan Cameron
---
contrib/plugins/cache.c | 75 +
1 file changed, 68 insertions(+), 7 deletions(-)
diff --git a/contrib/plugins/cache.c b/contrib/plugins/cache.c
index 7baff868
On 1/21/2025 8:23 AM, Philippe Mathieu-Daudé wrote:
Remove as unreachable code.
Signed-off-by: Philippe Mathieu-Daudé
---
Reviewed-by: Brian Cain
target/hexagon/cpu.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index 0b7fc98f6c
On 1/21/25 06:23, Philippe Mathieu-Daudé wrote:
Move has_work() from CPUClass to SysemuCPUOps, move
s390_cpu_has_work() to cpu-system.c so it is only build
for system emulation binaries, restrict functions not
used anymore on user emulation in interrupt.c.
Signed-off-by: Philippe Mathieu-Daudé
-
On 1/21/25 06:23, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
target/riscv/cpu.h | 9 +
target/riscv/internals.h | 3 ---
target/riscv/cpu.c | 8 +++-
3 files changed, 8 insertions(+), 12 deletions(-)
diff --git a/target/riscv/cpu.h b/tar
On 1/21/25 06:23, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
target/rx/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Richard Henderson
r~
On 1/21/25 06:23, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
target/hppa/cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
Reviewed-by: Richard Henderson
r~
The negation steps in FCADD must honour FPCR.AH's "don't change the
sign of a NaN" semantics. Implement this in the same way we did for
the base ASIMD FCADD, by encoding FPCR.AH into the SIMD data field
passed to the helper and using that to decide whether to negate the
values.
Signed-off-by: Pet
On Fri, Jan 24, 2025 at 05:47:45PM +0800, Xu Yilun wrote:
> On Thu, Jan 23, 2025 at 11:47:17AM -0500, Peter Xu wrote:
> > On Thu, Jan 23, 2025 at 05:33:53PM +0800, Xu Yilun wrote:
> > > On Wed, Jan 22, 2025 at 11:43:01AM -0500, Peter Xu wrote:
> > > > On Wed, Jan 22, 2025 at 05:41:31PM +0800, Xu Yi
On 1/21/25 06:23, Philippe Mathieu-Daudé wrote:
Currently only system emulation is supported.
Assert no target code is built for user emulation.
Remove #ifdef'ry since more work is required before
being able to emulate a user process.
Signed-off-by: Philippe Mathieu-Daudé
---
target/rx/cpu.h
Peter Maydell writes:
> Add a test case which tests some corner case behaviour of
> fused-multiply-add on x86:
> * 0 * Inf + SNaN should raise Invalid
> * 0 * Inf + QNaN shouldh not raise Invalid
> * tininess should be detected after rounding
>
> There is also one currently-disabled test case:
On 24/1/25 13:47, BALATON Zoltan wrote:
The variable is uint64_t so needs %PRIu64 instead of %d.
Fixes: 3ae7eb88c47 ("ehci: fix overflow in frame timer code")
Signed-off-by: BALATON Zoltan
Reviewed-by: Peter Maydell
---
v3: Fixed commit message to match what the patch actually does
hw/usb/h
On 1/21/25 06:23, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
target/ppc/cpu_init.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
Reviewed-by: Richard Henderson
r~
On 1/21/25 06:23, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
target/openrisc/cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
Reviewed-by: Richard Henderson
r~
On 1/21/25 06:23, Philippe Mathieu-Daudé wrote:
Move has_work() from CPUClass to SysemuCPUOps and
cpu_mips_hw_interrupts_enabled() to system.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/internal.h | 4 ++--
target/mips/cpu.c | 4 +++-
2 files changed, 5 insertions(+), 3 delet
On 1/21/25 06:23, Philippe Mathieu-Daudé wrote:
This method is not used on user emulation, because there
is always work to do there.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/core/cpu.h | 28 ++--
1 file changed, 14 insertions(+), 14 deletions(-)
Reviewed
On 1/21/25 06:23, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
target/microblaze/cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
Reviewed-by: Richard Henderson
r~
On 1/21/25 06:23, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
target/m68k/cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
Reviewed-by: Richard Henderson
r~
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index 41dfdf58045..eb7fb4f7e4c 100644
On Fri, Jan 24, 2025 at 03:15:27PM +0100, Thomas Huth wrote:
> Move the mipsel replay tests from tests/avocado/replay_kernel.py to
> the functional framework. Since the functional tests should be run per
> target, we cannot stick all replay tests in one file. Thus let's add
> these tests to the fil
On 1/21/25 06:23, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
target/loongarch/cpu.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
Reviewed-by: Richard Henderson
r~
On Thu, 23 Jan 2025 09:51:51 +
Jonathan Cameron via wrote:
> On Wed, 22 Jan 2025 07:56:24 +0100
> Philippe Mathieu-Daudé wrote:
>
> > Map the component I/O region as UnimplementedDevice
> > to be able to trace guest I/O accesses with '-d unimp'.
> >
> > Signed-off-by: Philippe Mathieu-Daud
On 1/21/25 06:23, Philippe Mathieu-Daudé wrote:
Move has_work() from CPUClass to SysemuCPUOps,
restrict x86_cpu_pending_interrupt() to system.
Signed-off-by: Philippe Mathieu-Daudé
---
target/i386/cpu.h | 4 ++--
target/i386/cpu.c | 8 +++-
2 files changed, 5 insertions(+), 7 deletions(-
Implement the FPCR.AH semantics for FMAXV and FMINV. These are the
"recursively reduce all lanes of a vector to a scalar result" insns;
we just need to use the _ah_ helper for the reduction step when
FPCR.AH == 1.
Signed-off-by: Peter Maydell
---
target/arm/tcg/translate-a64.c | 28
On 1/21/25 06:23, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
target/avr/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Richard Henderson
r~
On 1/21/25 06:23, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
target/alpha/cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
Reviewed-by: Richard Henderson
r~
On 1/21/25 06:23, Philippe Mathieu-Daudé wrote:
Remove as unreachable code.
Signed-off-by: Philippe Mathieu-Daudé
---
target/hexagon/cpu.c | 6 --
1 file changed, 6 deletions(-)
Reviewed-by: Richard Henderson
r~
On 1/21/25 06:23, Philippe Mathieu-Daudé wrote:
In order to expand cpu_has_work(), un-inline it.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/core/cpu.h | 6 +-
hw/core/cpu-system.c | 6 ++
2 files changed, 7 insertions(+), 5 deletions(-)
Reviewed-by: Richard Henderson
r
On 1/21/25 06:23, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/core/cpu.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index b7367f6d808..2402706c7d9 100644
--- a/include/hw/core/cpu
When FPCR.AH is 1, use FPST_FPCR_AH for:
* AdvSIMD BFMLALB, BFMLALT
* SVE BFMLALB, BFMLALT, BFMLSLB, BFMLSLT
so that they get the required behaviour changes.
We do this by making gen_gvec_op4_fpst() take an ARMFPStatusFlavour
rather than a bool is_fp16; existing callsites now select
FPST_FPCR_F
Handle the FPCR.AH "don't negate the sign of a NaN" semantics
in FMLS (vector), by implementing a new set of helpers for
the AH=1 case.
Signed-off-by: Peter Maydell
---
target/arm/helper.h| 4
target/arm/tcg/translate-a64.c | 7 ++-
target/arm/tcg/vec_helper.c| 25
Let's factor more of the generic "is this directly accessible" check,
independent of the "write" condition out.
Note that the "!mr->rom_device" check in the write case essentially
disallows the memory_region_is_romd() condition again. Further note that
RAM DEVICE regions are also RAM regions, so w
On 1/21/25 06:23, Philippe Mathieu-Daudé wrote:
Currently only system emulation is supported.
Assert no target code is built for user emulation.
Signed-off-by: Philippe Mathieu-Daudé
---
target/tricore/cpu.h | 4
1 file changed, 4 insertions(+)
diff --git a/target/tricore/cpu.h b/targe
On Fri, Jan 24, 2025 at 03:15:25PM +0100, Thomas Huth wrote:
> Some tests have a very long runtime and might run into timeout
> issues e.g. when QEMU has been compiled with --enable-debug.
> Add a decorator for marking them more easily and document the
> corresponding environment variable that is u
On 23/1/25 02:22, Gustavo Romero wrote:
Add me as the maintainer for the ivshmem-pci.c device, the ivshmem
server, and the ivshmem client tool. Also, adjust remaining parts left
behind after ivshmem PCI device was renamed from ivshmem.c to
ivshmem-pci.c, like header files, Kconfig, docs, and buil
For the instructions FRECPE, FRECPS, FRECPX, FRSQRTE, FRSQRTS, use
FPST_FPCR_AH or FPST_FPCR_AH_F16 when FPCR.AH is 1, so that they get
the required behaviour changes.
Signed-off-by: Peter Maydell
---
select_fpst() is another function I'm not super happy wit hthe
naming of, because again it shoul
The negation steps in FCADD must honour FPCR.AH's "don't change the
sign of a NaN" semantics. Implement this by encoding FPCR.AH into
the SIMD data field passed to the helper and using that to decide
whether to negate the values.
Signed-off-by: Peter Maydell
---
target/arm/tcg/translate-a64.c |
Now the emulation is complete, we can enable FEAT_RPRES for the 'max'
CPU type.
Signed-off-by: Peter Maydell
---
docs/system/arm/emulation.rst | 1 +
target/arm/tcg/cpu64.c| 1 +
2 files changed, 2 insertions(+)
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
Part of FEAT_AFP is the new control bit FPCR.FIZ. This bit affects
flushing of single and double precision denormal inputs to zero for
AArch64 floating point instructions. (For half-precision, the
existing FPCR.FZ16 control remains the only one.)
FPCR.FIZ differs from FPCR.FZ in that if we flush
Implement the FPCR.AH semantics for the pairwise floating
point minimum/maximum insns FMINP and FMAXP.
Signed-off-by: Peter Maydell
---
target/arm/tcg/helper-sve.h| 14 ++
target/arm/tcg/translate-a64.c | 25 +
target/arm/tcg/vec_helper.c| 10 +
For FEAT_AFP's FPCR.NEP bit, we need to programmatically change the
behaviour of the writeback of the result for most SIMD scalar
operations, so that instead of zeroing the upper part of the result
register it merges the upper elements from one of the input
registers.
Provide new functions write_f
FEAT_RPRES implements an "increased precision" variant of the single
precision FRECPE and FRSQRTE instructions from an 8 bit to a 12
bit mantissa. This applies only when FPCR.AH == 1. Note that the
halfprec and double versions of these insns retain the 8 bit
precision regardless.
In this commit we
Handle the FPCR.AH semantics that we do not change the sign of an
input NaN in the FRECPS and FRSQRTS scalar insns, by providing
new helper functions that do the CHS part of the operation
differently.
Since the extra helper functions would be very repetitive if written
out longhand, we condense th
The x86 DE bit in the FPU and MXCSR status is supposed to be set
when an input denormal is consumed. We didn't previously report
this from softfloat, so the x86 code either simply didn't set
the DE bit or else incorrectly wired it up to denormal_flushed,
depending on which register you looked at.
Implement the FPCR.AH semantics for the SVE FMAX and FMIN operations
that take an immediate as the second operand.
Signed-off-by: Peter Maydell
---
target/arm/tcg/helper-sve.h| 14 ++
target/arm/tcg/sve_helper.c| 8
target/arm/tcg/translate-sve.c | 25 ++
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