Hi,
On Tue, 21 Jan 2025 at 21:17, Peter Xu wrote:
> https://lore.kernel.org/qemu-devel/ZykJBq7ME5jgSzCA@x1n/
> Would you please add all the tests mentioned there?
/x86_64/migration/multifd/file/mapped-ram/
/x86_64/migration/multifd/tcp/uri/plain/none
/x86_64/migration/multifd/tcp/plai
With CSR register, dynamic function access is used for CSR register
access in TCG mode, so that csr info can be used by other modules.
Signed-off-by: Bibo Mao
---
.../tcg/insn_trans/trans_privileged.c.inc | 37 +--
target/loongarch/tcg/tcg_loongarch.h | 12 ++
ta
CSR registers is import system control registers, it had better
dump all CSR registers when VM is running in system mode.
Here is dump output example of CSR registers:
CSR000: CRMD b4 PRMD 4EUEN 0
MISC 0
CSR004: ECFG 71c1cESTAT
Parameter type TCGv and TCGv_ptr for function GenCSRRead and GenCSRWrite
is not used in non-TCG mode. Generic csr function type is added here
with parameter void type, so that it passes to compile with non-TCG mode.
Signed-off-by: Bibo Mao
---
.../tcg/insn_trans/trans_privileged.c.inc | 27 +
On LA464, some CSR registers are not used such as CSR_SAVE8 -
CSR_SAVE15, also CSR registers relative with MCE is not used now.
Flag CSRFL_UNUSED is added for these registers, so that it will
not dumped. In order to keep compatiblity, these CSR registers are
not removed since it is used in vmstate
CSR registers is import system control registers, it had better to dump
all CSR registers when VM is running in system mode, rather than dump
part of those, since guest OS uses these CSR registers. And it is very
useful to debug guest OS.
---
v2 .. v3:
1. Split patch into smaller in order to
Since CSR function setting is done dynamically in TCG mode, remove
static CSR function setting here.
Signed-off-by: Bibo Mao
---
.../tcg/insn_trans/trans_privileged.c.inc| 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/loongarch/tcg/insn_trans/t
Common header file csr.h is added here, it can be used by both
TCG mode and kvm mode.
Signed-off-by: Bibo Mao
---
target/loongarch/csr.h| 25 +++
.../tcg/insn_trans/trans_privileged.c.inc | 16 +---
2 files changed, 26 insertions(+), 15 deletio
Common source file csr.c is added here, it can be used by both
TCG mode and kvm mode. The common code is removed from file
tcg/insn_trans/trans_privileged.c.inc to csrc.c
It is simply code movement, no function change.
Signed-off-by: Bibo Mao
---
target/loongarch/csr.c|
Hi Cedric,
> -Original Message-
> From: Cédric Le Goater
> Sent: Wednesday, January 22, 2025 3:23 PM
> To: Jamin Lin ; qemu-...@nongnu.org;
> qemu-devel@nongnu.org
> Cc: Joel Stanley ; Andrew Jeffery
> ; Troy Lee ;
> Steven Lee
> Subject: Re: [PATCH 0/9] aspeed: pre-PR for QEMU 10.0
>
> -Original Message-
> From: Cédric Le Goater
> Sent: Wednesday, January 22, 2025 3:09 PM
> To: qemu-...@nongnu.org; qemu-devel@nongnu.org
> Cc: Joel Stanley ; Andrew Jeffery
> ; Troy Lee ;
> Jamin Lin ; Steven Lee
> ; Cédric Le Goater
> Subject: [PATCH 9/9] aspeed: Create sd devices only
On 1/22/25 08:28, Jamin Lin wrote:
Hi Cedric,
From: Cédric Le Goater
Sent: Wednesday, January 22, 2025 3:09 PM
To: qemu-...@nongnu.org; qemu-devel@nongnu.org
Cc: Joel Stanley ; Andrew Jeffery
; Troy Lee ;
Jamin Lin ; Steven Lee
; Cédric Le Goater
Subject: [PATCH 7/9] test/functional: Update t
> From: Cédric Le Goater
> Sent: Wednesday, January 22, 2025 3:09 PM
> To: qemu-...@nongnu.org; qemu-devel@nongnu.org
> Cc: Joel Stanley ; Andrew Jeffery
> ; Troy Lee ;
> Jamin Lin ; Steven Lee
> ; Cédric Le Goater
> Subject: [PATCH 8/9] test/functional: Update buildroot images to 2024.11
>
> Th
Hi Cedric,
> From: Cédric Le Goater
> Sent: Wednesday, January 22, 2025 3:09 PM
> To: qemu-...@nongnu.org; qemu-devel@nongnu.org
> Cc: Joel Stanley ; Andrew Jeffery
> ; Troy Lee ;
> Jamin Lin ; Steven Lee
> ; Cédric Le Goater
> Subject: [PATCH 7/9] test/functional: Update the Aspeed aarch64 test
On 12/11/24 17:41, Aleksandar Rakic wrote:
Add emulation of MIPS' CRC32 (Cyclic Redundancy Check) instructions.
Reuse zlib crc32() and Linux crc32c().
Cherry-picked 4cc974938aee1588f852590509004e340c072940
from https://github.com/MIPS/gnutools-qemu
Signed-off-by: Yongbok Kim
Signed-off-by: Ale
Hi
On Tue, Jan 21, 2025 at 10:47 PM Roman Penyaev wrote:
>
> Mux is a character backend (host side) device, which multiplexes
> multiple frontends with one backend device. The following is a
> few lines from the QEMU manpage [1]:
>
> A multiplexer is a "1:N" device, and here the "1" end is your
On 1/22/25 08:08, Cédric Le Goater wrote:
On 1/22/25 04:35, Jamin Lin wrote:
Hi Cedric,
-Original Message-
From: Cédric Le Goater
Sent: Monday, January 20, 2025 5:58 PM
To: qemu-...@nongnu.org; qemu-devel@nongnu.org
Cc: Joel Stanley ; Andrew Jeffery
; Troy Lee ;
Jamin Lin ; Steven Lee
On 12/11/24 17:41, Aleksandar Rakic wrote:
Add emulation of MIPS' CRC32 (Cyclic Redundancy Check) instructions.
Reuse zlib crc32() and Linux crc32c().
Cherry-picked 4cc974938aee1588f852590509004e340c072940
from https://github.com/MIPS/gnutools-qemu
Signed-off-by: Yongbok Kim
Signed-off-by: Ale
From: Jamin Lin
The register set have a significant change in AST2700. The TMC00-TMC3C
are used for TIMER0 and TMC40-TMC7C are used for TIMER1. In additional,
TMC20-TMC3C and TMC60-TMC7C are reserved registers for TIMER0 and TIMER1,
respectively.
Besides, each TIMER has their own control and int
On Wed, Jan 22, 2025 at 12:25 AM Eric Auger wrote:
>
>
> Hi Jason,
>
> On 1/21/25 4:27 AM, Jason Wang wrote:
> > On Tue, Jan 21, 2025 at 1:33 AM Eric Auger wrote:
> >> When a guest exposed with a vhost device and protected by an
> >> intel IOMMU gets rebooted, we sometimes observe a spurious warn
Hello,
Here are the changes I plan to send as a PR for QEMU 10.0, this week
or the next. The last 3 patches still need a review. An Ack would be
appreciated.
Thanks,
C.
Cédric Le Goater (3):
test/functional: Update the Aspeed aarch64 test
test/functional: Update buildroot images to 2024.11
Bumped SDK version to v09.03. v09.04 is available but not yet
supported in QEMU.
Signed-off-by: Cédric Le Goater
---
tests/functional/test_aarch64_aspeed.py | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/tests/functional/test_aarch64_aspeed.py
b/tests/functional/tes
From: Jamin Lin
Add Timer model for AST2700 Timer support. The Timer controller include 8 sets
of 32-bit decrement counters.
The base address of TIMER0 to TIMER7 as following.
Base Address of Timer 0 = 0x12C1_
Base Address of Timer 1 = 0x12C1_0040
Base Address of Timer 2 = 0x12C1_0080
Base A
From: Kenneth Jia
In the loop, we need ignore the index increase when uart == uart_chosen
We should increase the index only after we allocate a serial.
Signed-off-by: Kenneth Jia
Fixes: d2b3eaefb4d7 ("aspeed: Refactor UART init for multi-SoC machines")
Reviewed-by: Cédric Le Goater
Link: https
The main changes compared to upstream 2024.11 buildroot are
- bumped Linux to version 6.11.11 with a custom config
- changed U-Boot to OpenBMC branch for more support
- included extra target packages
See branch [1] for more details.
There is a slight output change when powering off the machine,
When the -nodefaults option is set, sd devices should not be
automatically created by the machine. Instead they should be defined
on the command line.
Note that it is not currently possible to define which bus an
"sd-card" device is attached to:
-blockdev node-name=drive0,driver=file,filename=/
From: Jamin Lin
The Write Protect pin of SDHCI model is default active low to match the SDHCI
spec. So, write enable the bit 19 should be 1 and write protected the bit 19
should be 0 at the Present State Register (0x24).
According to the design of AST2600 EVB, the Write Protected pin is active
h
From: Jamin Lin
The Write Protect pin of SDHCI model is default active low to match the SDHCI
spec. So, write enable the bit 19 should be 1 and write protected the bit 19
should be 0 at the Present State Register (0x24). However, some boards are
design Write Protected pin active high. In other wo
From: Jamin Lin
The timer controller include 8 sets of 32-bit decrement counters, based on
either PCLK or 1MHZ clock and the design of timer controller between AST2600
and AST2700 are almost the same.
TIMER0 – TIMER7 has their own individual control and interrupt status register.
In other words,
On 1/22/25 04:35, Jamin Lin wrote:
Hi Cedric,
-Original Message-
From: Cédric Le Goater
Sent: Monday, January 20, 2025 5:58 PM
To: qemu-...@nongnu.org; qemu-devel@nongnu.org
Cc: Joel Stanley ; Andrew Jeffery
; Troy Lee ;
Jamin Lin ; Steven Lee
; Cédric Le Goater
Subject: [PATCH 0/9] a
On 17/1/25 13:42, Daniel Henrique Barboza wrote:
On 1/16/25 8:04 PM, Philippe Mathieu-Daudé wrote:
When methods don't modify the CPUARMState* argument,
we can mark it const. This allow enforcing places where
the CPU env shouldn't be modified at all,
Signed-off-by: Philippe Mathieu-Daudé
---
On 17/1/25 18:28, Nicholas Piggin wrote:
Of the MSI-X PBA pending bits, the PCI Local Bus Specification says:
Software should never write, and should only read
Pending Bits. If software writes to Pending Bits, the
result is undefined.
Log a GUEST_ERROR message if the PBA is written to
On 21/1/25 16:55, Philippe Mathieu-Daudé wrote:
Split IPACK Kconfig key as {IPACK, TPCI200, IP_OCTAL_232}
- IPack is a bus
- TPCI200 is a PCI device providing an IPack bus
- IP-Octal232 is an IPack device plugged on an IPack bus
Signed-off-by: Philippe Mathieu-Daudé
---
hw/char/Kcon
On 21/1/25 11:59, Titus Rwantare wrote:
This has been useful when debugging and unsure if the guest is
generating i2c traffic.
Signed-off-by: Titus Rwantare
---
hw/misc/i2c-echo.c | 8
hw/misc/trace-events | 5 +
2 files changed, 13 insertions(+)
Reviewed-by: Philippe Mathi
Add me as the maintainer for the ivshmem-pci device.
Signed-off-by: Gustavo Romero
---
MAINTAINERS | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 846b81e3ec..c3e69ef3e4 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2789,11 +2789,14 @@ F:
Map the component I/O region as UnimplementedDevice
to be able to trace guest I/O accesses with '-d unimp'.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/cxl/cxl_component.h | 3 ++-
hw/cxl/cxl-component-utils.c | 14 +++---
hw/cxl/Kconfig | 1 +
3 files change
Avoid wasting 4K for each component, remove unused io_registers[].
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/cxl/cxl_component.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/include/hw/cxl/cxl_component.h b/include/hw/cxl/cxl_component.h
index 945ee6ffd04..ac61c3f33a5 100644
---
Allow tracing component I/O accesses,
remove unused io_registers[] array.
Philippe Mathieu-Daudé (2):
hw/cxl: Remove unused component_registers::io_registers[] array
hw/cxl: Allow tracing component I/O accesses
include/hw/cxl/cxl_component.h | 4 ++--
hw/cxl/cxl-component-utils.c | 14 +++
On Tue, Jan 21, 2025 at 6:20 PM Alex Bennée wrote:
> Hao Wu writes:
>
> > Have you tried that the test can pass with this? If I remember
> correctly, interrupt won't trigger properly if not advancing the
> > timer
>
> Yes but the IRQ has yet to be enabled at this point.
>
I believe that's the ca
On 1/21/2025 6:26 PM, David Hildenbrand wrote:
> On 21.01.25 11:16, Chenyi Qiang wrote:
>>
>>
>> On 1/21/2025 5:26 PM, David Hildenbrand wrote:
>>> On 21.01.25 10:00, Chenyi Qiang wrote:
Thanks Peter for your review!
On 1/21/2025 2:09 AM, Peter Xu wrote:
> Two trivial comments
On Tue, Jan 21, 2025 at 7:00 PM Titus Rwantare wrote:
> This has been useful when debugging and unsure if the guest is
> generating i2c traffic.
>
> Signed-off-by: Titus Rwantare
>
Reviewed-by: Hao Wu
> ---
> hw/misc/i2c-echo.c | 8
> hw/misc/trace-events | 5 +
> 2 files chang
On 22/01/2025 01.27, Stefan Hajnoczi wrote:
Hi Thomas,
Please take a look at these CI failures:
https://gitlab.com/qemu-project/qemu/-/jobs/8913471007
https://gitlab.com/qemu-project/qemu/-/jobs/8913471508
https://gitlab.com/qemu-project/qemu/-/jobs/8913472011
Ah, thanks, nice catch, unlike the
On 1/21/25 19:47, Michael Tokarev wrote:
22.01.2025 02:14, Pierrick Bouvier wrote:
..
I agree the existing code (and this patch) is pretty cryptic for anyone not
familiar with FAT format.
However, I think it could be a good thing to first merge this one (which is
correct, and works), and refac
On 1/22/2025 11:28 AM, Chenyi Qiang wrote:
On 1/22/2025 12:35 AM, Peter Xu wrote:
On Tue, Jan 21, 2025 at 09:35:26AM +0800, Chenyi Qiang wrote:
On 1/21/2025 2:33 AM, Peter Xu wrote:
On Mon, Jan 20, 2025 at 06:54:14PM +0100, David Hildenbrand wrote:
On 20.01.25 18:21, Peter Xu wrote:
On M
On 22/1/25 02:18, Peter Xu wrote:
On Tue, Jun 25, 2024 at 12:31:13AM +0800, Xu Yilun wrote:
On Mon, Jan 20, 2025 at 03:46:15PM -0500, Peter Xu wrote:
On Mon, Jan 20, 2025 at 09:22:50PM +1100, Alexey Kardashevskiy wrote:
It is still uncertain how to implement the private MMIO. Our assumption
On Wed, Jan 22, 2025 at 09:16:37AM +0800, Tao Su wrote:
> On Tue, Jan 21, 2025 at 09:34:58AM -0800, Pawan Gupta wrote:
> > On Tue, Jan 21, 2025 at 10:06:47AM +0800, Tao Su wrote:
> > > Update SierraForest CPU model to add LAM, 4 bits indicating certain bits
> > > of IA32_SPEC_CTR are supported(inte
22.01.2025 02:14, Pierrick Bouvier wrote:
..
I agree the existing code (and this patch) is pretty cryptic for anyone not
familiar with FAT format.
However, I think it could be a good thing to first merge this one (which is correct, and works), and refactor this in a second time, so the current
Hi Cedric,
> -Original Message-
> From: Cédric Le Goater
> Sent: Monday, January 20, 2025 5:30 PM
> To: Jamin Lin ; Peter Maydell
> ; Steven Lee ; Troy
> Lee ; Andrew Jeffery ;
> Joel Stanley ; open list:ASPEED BMCs
> ; open list:All patches CC here
>
> Cc: Troy Lee ; Yunlin Tang
>
> S
Hi Cedric,
> -Original Message-
> From: Cédric Le Goater
> Sent: Monday, January 20, 2025 5:58 PM
> To: qemu-...@nongnu.org; qemu-devel@nongnu.org
> Cc: Joel Stanley ; Andrew Jeffery
> ; Troy Lee ;
> Jamin Lin ; Steven Lee
> ; Cédric Le Goater
> Subject: [PATCH 0/9] aspeed: pre-PR for QE
On 1/22/2025 12:35 AM, Peter Xu wrote:
> On Tue, Jan 21, 2025 at 09:35:26AM +0800, Chenyi Qiang wrote:
>>
>>
>> On 1/21/2025 2:33 AM, Peter Xu wrote:
>>> On Mon, Jan 20, 2025 at 06:54:14PM +0100, David Hildenbrand wrote:
On 20.01.25 18:21, Peter Xu wrote:
> On Mon, Jan 20, 2025 at 11:48
On Tue, Jan 21, 2025 at 05:15:46PM +0100, Paolo Bonzini wrote:
> Date: Tue, 21 Jan 2025 17:15:46 +0100
> From: Paolo Bonzini
> Subject: [PATCH] rust: pl011: fix repr(C) for PL011Class
> X-Mailer: git-send-email 2.47.1
>
> Signed-off-by: Paolo Bonzini
> ---
> rust/hw/char/pl011/src/device.rs | 1
On Tue, Jan 21, 2025 at 04:58:21PM +0100, Paolo Bonzini wrote:
> Date: Tue, 21 Jan 2025 16:58:21 +0100
> From: Paolo Bonzini
> Subject: Re: [PATCH RESEND 0/2] rust/pl011: miscellaneous cleanups
>
> On 1/21/25 15:04, Zhao Liu wrote:
> > (Resend the series since it was missed on
> > https://lore.k
Hi Cedric,
> From: Cédric Le Goater
> Sent: Tuesday, January 21, 2025 6:39 PM
> To: Jamin Lin ; Peter Maydell
> ; Steven Lee ; Troy
> Lee ; Andrew Jeffery ;
> Joel Stanley ; Philippe Mathieu-Daudé ;
> Bin Meng ; open list:ASPEED BMCs
> ; open list:All patches CC here
> ; open list:SD (Secure Car
On 1/21/2025 10:06 AM, Tao Su wrote:
Update SierraForest CPU model to add LAM, 4 bits indicating certain bits
of IA32_SPEC_CTR are supported(intel-psfd, ipred-ctrl, rrsba-ctrl,
bhi-ctrl) and the missing features(ss, tsc-adjust, cldemote, movdiri,
movdir64b)
Also add GDS-NO and RFDS-NO to indicat
On 1/21/2025 10:06 AM, Tao Su wrote:
Branch History Injection (BHI) is a CPU side-channel vulnerability, where
an attacker may manipulate branch history before transitioning from user
to supervisor mode or from VMX non-root/guest to root mode. CPUs that set
BHI_NO bit in MSR IA32_ARCH_CAPABILITIE
On 1/21/2025 10:06 AM, Tao Su wrote:
According to table 1-2 in Intel Architecture Instruction Set Extensions
and Future Features (rev 056) [1], ClearwaterForest has the following new
features which have already been virtualized:
- AVX-VNNI-INT16 CPUID.(EAX=7,ECX=1):EDX[bit 10]
- SHA512
On Tue, Jan 21, 2025 at 02:38:44PM +0100, Paolo Bonzini wrote:
> Queued with the tweaks suggested by Zoltan and Zhao; thanks!
Thank you Paolo :-)
On Tue, Jan 21, 2025 at 09:31:25PM +0800, Zhao Liu wrote:
> On Tue, Jan 21, 2025 at 10:06:50AM +0800, Tao Su wrote:
> > Date: Tue, 21 Jan 2025 10:06:50 +0800
> > From: Tao Su
> > Subject: [PATCH 4/4] docs: Add GNR, SRF and CWF CPU models
> > X-Mailer: git-send-email 2.34.1
> >
> > Update GraniteR
On Tue, Jan 21, 2025 at 09:34:58AM -0800, Pawan Gupta wrote:
> On Tue, Jan 21, 2025 at 10:06:47AM +0800, Tao Su wrote:
> > Update SierraForest CPU model to add LAM, 4 bits indicating certain bits
> > of IA32_SPEC_CTR are supported(intel-psfd, ipred-ctrl, rrsba-ctrl,
> > bhi-ctrl) and the missing fe
On 21/01/2025 23:19, Jonathan Cameron wrote:
>>> -msix_uninit_exclusive_bar(pci_dev);
>>> g_free(regs->special_ops);
>>> -err_address_space_free:
>>> +err_msix_uninit:
>>> +msix_uninit_exclusive_bar(pci_dev);
>> This reorder doesn't look correct.
>>
>> Should end up I think as
>> er
On 1/2/25 10:25, Philippe Mathieu-Daudé wrote:
Commit bb6cf6f0168 ("accel/tcg: Factor tcg_cpu_reset_hold()
out") wanted to restrict tlb_flush() to system emulation,
but inadvertently also restricted tcg_flush_jmp_cache(),
which was before called on user emulation via:
Realize -> Reset -> cpu_
On 1/2/25 10:25, Philippe Mathieu-Daudé wrote:
Since tcg_cpu_reset_hold() is a system emulation specific
helper, factor tcg_exec_reset() out so we can use it from
user emulation, similarly to the [un]realize() handlers.
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/internal-common.h | 1
On 1/2/25 10:25, Philippe Mathieu-Daudé wrote:
Very few source files require to access "exec/tb-flush.h"
declarations, and except a pair, they all include it
explicitly. No need to overload the generic "user-internals.h".
Signed-off-by: Philippe Mathieu-Daudé
---
linux-user/user-internals.h |
Hi Thomas,
Please take a look at these CI failures:
https://gitlab.com/qemu-project/qemu/-/jobs/8913471007
https://gitlab.com/qemu-project/qemu/-/jobs/8913471508
https://gitlab.com/qemu-project/qemu/-/jobs/8913472011
Thanks,
Stefan
On 1/21/25 11:03, Philippe Mathieu-Daudé wrote:
Returning target segment low boundary address multiple
shouldn't need to modify the CPU env. Make it const.
Signed-off-by: Philippe Mathieu-Daudé
---
linux-user/arm/target_syscall.h| 2 +-
linux-user/mips/target_syscall.h | 2 +-
linux-us
On 1/21/25 10:28, Philippe Mathieu-Daudé wrote:
There are a fixed number of PCI IRQs, known beforehand.
Allocate them within PCIMultiSerialState, and initialize
using qemu_init_irq(), allowing to remove the legacy
qemu_allocate_irqs() and qemu_free_irqs() calls.
Signed-off-by: Philippe Mathieu-D
On 1/18/25 09:10, Michael Tokarev wrote:
05.01.2025 16:59, Volker Rümelin wrote:
In function create_long_filname(), the array name[8 + 3] in
struct direntry_t is used as if it were defined as name[32].
This is intentional and works. It's nevertheless an out of
bounds array access. To avoid this
On 1/21/25 10:24, Philippe Mathieu-Daudé wrote:
The FPGA exposes a fixed set of IRQs. Hold them in the FPGA
state and initialize them in place calling qemu_init_irqs().
Move r2d_fpga_irq enums earlier so we can use NR_IRQS within
the r2d_fpga_t structure. r2d_fpga_init() returns r2d_fpga_t,
and
On 1/21/25 09:06, Daniel Henrique Barboza wrote:
In the RISC-V privileged ISA section 3.1.15 table 15, it is determined
that a debug exception that is triggered from a load/store has a higher
priority than a possible fault that this access might trigger.
This is not the case ATM as shown in [1].
On 1/21/25 08:18, Philippe Mathieu-Daudé wrote:
There are always 8 IRQs created with a MIPS CPU.
Allocate their state once in CPUMIPSState, initialize
them in place in cpu_mips_irq_init_cpu(). Update hw/ uses.
Move cpu_mips_irq_init_cpu() declaration from "cpu.h"
to "internal.h", as it shouldn't
On 1/21/25 08:18, Philippe Mathieu-Daudé wrote:
MIPS CPU timer is tied to the CPU, no point of modelling it as
a general timer device. Move mips_int.c to target/mips/system/.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/mips_int.c => target/mips/system/interrupts.c | 0
hw/mips/meson.bu
On 1/21/25 08:18, Philippe Mathieu-Daudé wrote:
The MIPS timer and IRQs are tied to the CPU. Creating them outside
in board code isn't correct. Do it once in the DeviceRealize() handler.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/cps.c| 4
hw/mips/fuloong2e.c | 4
On 1/21/25 07:55, Philippe Mathieu-Daudé wrote:
No need to dynamically allocate IRQ when we know before hands
how many we'll use. Declare the 2 of them in IPackDevice state
and initialize them in the DeviceRealize handler.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/ipack/ipack.h | 7
On 1/21/25 07:55, Philippe Mathieu-Daudé wrote:
While qemu_init_irq() initialize a single IRQ,
qemu_init_irqs() initialize an array of them.
Suggested-by: Bernhard Beschow
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/irq.h | 11 +++
hw/core/irq.c| 8
2 files c
From: William Roche
Punching a hole in a file with fallocate needs to take into account the
fd_offset value for a correct file location.
But guest_memfd internal use doesn't currently consider fd_offset.
Fixes: 4b870dc4d0c0 ("hostmem-file: add offset option")
Signed-off-by: William Roche
---
From: William Roche
Working on the poisoned memory recovery mechanisms with David
Hildenbrand, it appeared that the file hole punching done with
the memory discard functions are missing the file offset value
fd_offset to correctly modify the right file location.
Note that guest_memfd would not c
Am 21. Januar 2025 03:00:17 UTC schrieb BALATON Zoltan :
>On Mon, 20 Jan 2025, Bernhard Beschow wrote:
>> On a real device, the boot ROM contains the very first instructions the CPU
>> executes. Also, U-Boot calls into the ROM to determine the boot device. While
>> we're not actually implementin
On 21.01.25 21:59, Peter Xu wrote:
On Tue, Jan 21, 2025 at 09:41:55PM +0100, David Hildenbrand wrote:
So far my understanding is that Google that does shared+private guest_memfd
kernel part won't be working on QEMU patches. I raised that to our
management recently, that this would be a good proj
On Tue, Jan 21, 2025 at 09:41:55PM +0100, David Hildenbrand wrote:
> So far my understanding is that Google that does shared+private guest_memfd
> kernel part won't be working on QEMU patches. I raised that to our
> management recently, that this would be a good project for RH to focus on.
>
> I a
This "anon" memory cannot be "shared" with other processes, but
virtio-kernel etc. can just use it.
To "share" the memory with other processes, we'd need memfd/file.
Ah OK, thanks David. Is this the planned long term solution for
vhost-kernel?
I think the basic idea was that the memory backe
On Tue, Jan 21, 2025 at 07:24:29PM +0100, David Hildenbrand wrote:
> On 21.01.25 18:39, Peter Xu wrote:
> > On Wed, Mar 20, 2024 at 03:39:03AM -0500, Michael Roth wrote:
> > > From: Xiaoyao Li
> > >
> > > Add a new member "guest_memfd" to memory backends. When it's set
> > > to true, it enables R
On 21/1/25 19:47, Daniel Henrique Barboza wrote:
On 1/21/25 2:40 PM, Philippe Mathieu-Daudé wrote:
On 20/1/25 21:49, Daniel Henrique Barboza wrote:
The mcontrol select bit (19) is always zero, meaning our triggers will
always match virtual addresses. In this condition, if the user does not
sp
Returning target segment low boundary address multiple
shouldn't need to modify the CPU env. Make it const.
Signed-off-by: Philippe Mathieu-Daudé
---
linux-user/arm/target_syscall.h| 2 +-
linux-user/mips/target_syscall.h | 2 +-
linux-user/mips64/target_syscall.h | 2 +-
linux-user/sh4/ta
On 21/1/25 12:40, Philippe Mathieu-Daudé wrote:
CpuState caches its CPUClass since commit 6fbdff87062
("cpu: cache CPUClass in CPUState for hot code paths"),
use it.
Signed-off-by: Philippe Mathieu-Daudé
---
target/microblaze/gdbstub.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
On 21/1/25 12:40, Philippe Mathieu-Daudé wrote:
CpuState caches its CPUClass since commit 6fbdff87062
("cpu: cache CPUClass in CPUState for hot code paths"),
use it.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/core/generic-loader.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
Coverity reported a BAD_SHIFT issue in the following code:
> 2097
CID 1590355: Integer handling issues (BAD_SHIFT)
In expression "hdeleg >> cause", right shifting by more than 63
bits has undefined behavior. The shift amount, "cause", is at least 64.
> 2098
Mux is a character backend (host side) device, which multiplexes
multiple frontends with one backend device. The following is a
few lines from the QEMU manpage [1]:
A multiplexer is a "1:N" device, and here the "1" end is your
specified chardev backend, and the "N" end is the various parts
o
Coverity found a second DEADCODE issue in rmw_xireg() claiming that we can't
reach 'RISCV_EXCP_NONE' at the 'done' label:
> 2706 done:
> 2707 if (ret) {
> 2708 return (env->virt_enabled && virt) ?
> 2709RISCV_EXCP_VIRT_INSTRUCTION_FAULT :
> RISCV_E
Coverity found a DEADCODE issue in rmw_xiregi() claiming that we can't
reach 'RISCV_EXCP_VIRT_INSTRUCTION_FAULT' at the 'done' label:
> 2652 done:
CID 1590357: Control flow issues (DEADCODE)
Execution cannot reach the expression
"RISCV_EXCP_VIRT_INSTRUCTION_FAUL
This commit introduces a new test function `char_hub_test` to validate
the functionality and constraints of the "hub" chardev backend in QEMU.
The test includes multiple scenarios:
1. Invalid hub creation:
- Creating a hub without defining `chardevs.N` (expects an error).
- Creating a hub wi
This patch implements a new chardev backend `hub` device, which
aggregates input from multiple backend devices and forwards it to a
single frontend device. Additionally, `hub` device takes the output
from the frontend device and sends it back to all the connected
backend devices. This allows for se
Coverity reported a DEADCODE ticket in this function, as follows:
CID 1590358: Control flow issues (DEADCODE)
Execution cannot reach this statement: "return ret;".
> 380 return ret;
> 381 }
The cause is that the 'if (ret != RISCV_EXCP_NONE)' condition
Hi,
This series contains Coverity fixes for issues found in the latest
RISC-V pull made yesterday.
Coverity CIDs being resolved: 1590355, 1590356, 1590357, 1590358 and
1590359.
Patches based on master.
Daniel Henrique Barboza (5):
target/riscv/csr.c: fix deadcode in rmw_xireg()
target/ri
Coverity found a DEADCODE issue in rmw_xireg() claiming that we can't
reach 'RISCV_EXCP_VIRT_INSTRUCTION_FAULT' at the 'done' label:
done:
if (ret) {
return (env->virt_enabled && virt) ?
RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
}
return RISCV_
Change makes code symmetric to the code, which handles
the "connected" state, i.e. send CHR_EVENT_CLOSED when
state changes from "connected" to "disconnected".
This behavior is similar to char-socket, for example.
Signed-off-by: Roman Penyaev
Reviewed-by: "Alex Bennée"
Cc: "Marc-André Lureau"
This adds a few lines describing `hub` aggregator configuration
for aggregation of several backend devices with a single frontend
device.
Signed-off-by: Roman Penyaev
Cc: "Marc-André Lureau"
Cc: qemu-devel@nongnu.org
---
qemu-options.hx | 49 +
1
On 1/21/25 2:40 PM, Philippe Mathieu-Daudé wrote:
On 20/1/25 21:49, Daniel Henrique Barboza wrote:
The mcontrol select bit (19) is always zero, meaning our triggers will
always match virtual addresses. In this condition, if the user does not
specify a size for the trigger, the access size def
On 21.01.25 19:38, William Roche wrote:
Thank you Peter and David for your feedback.
On 1/21/25 19:25, David Hildenbrand wrote:
On 21.01.25 19:17, Peter Xu wrote:
On Tue, Jan 21, 2025 at 05:59:56PM +, “William Roche wrote:
From: William Roche
Punching a hole in a file with fallocate ne
Thank you Peter and David for your feedback.
On 1/21/25 19:25, David Hildenbrand wrote:
On 21.01.25 19:17, Peter Xu wrote:
On Tue, Jan 21, 2025 at 05:59:56PM +, “William Roche wrote:
From: William Roche
Punching a hole in a file with fallocate needs to take into account the
fd_offset va
There are a fixed number of PCI IRQs, known beforehand.
Allocate them within PCIMultiSerialState, and initialize
using qemu_init_irq(), allowing to remove the legacy
qemu_allocate_irqs() and qemu_free_irqs() calls.
Signed-off-by: Philippe Mathieu-Daudé
---
Based-on: <20250121155526.29982-2-phi...
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