On 1/22/25 04:35, Jamin Lin wrote:
Hi Cedric,
-----Original Message-----
From: Cédric Le Goater <c...@redhat.com>
Sent: Monday, January 20, 2025 5:58 PM
To: qemu-...@nongnu.org; qemu-devel@nongnu.org
Cc: Joel Stanley <j...@jms.id.au>; Andrew Jeffery
<and...@codeconstruct.com.au>; Troy Lee <troy_...@aspeedtech.com>;
Jamin Lin <jamin_...@aspeedtech.com>; Steven Lee
<steven_...@aspeedtech.com>; Cédric Le Goater <c...@redhat.com>
Subject: [PATCH 0/9] aspeed: pre-PR for QEMU 10.0
Sorry, I do not see this patch series in the following links.
I guess the mailing list had issues when I sent it. Will resend.
Thanks,
C.
Do I lost anything?
https://patchwork.kernel.org/project/qemu-devel/list/
https://patchew.org/QEMU/
https://www.mail-archive.com/qemu-devel@nongnu.org/mail5.html
Thanks-Jamin
Hello,
Here are the changes I plan to send as a PR for QEMU 10.0, this week or the
next. The last 3 patches still need a review. An Ack would be appreciated.
Thanks,
C.
Cédric Le Goater (3):
test/functional: Update the Aspeed aarch64 test
test/functional: Update buildroot images to 2024.11
aspeed: Create sd devices only when defaults are enabled
Jamin Lin (5):
hw/sd/sdhci: Introduce a new Write Protected pin inverted property
hw/arm/aspeed: Invert sdhci write protected pin for AST2600 EVB
hw/timer/aspeed: Refactor Timer Callbacks for SoC-Specific
Implementations
hw/timer/aspeed: Add AST2700 Support
aspeed/soc: Support Timer for AST2700
Kenneth Jia (1):
hw/arm/aspeed: fix connect_serial_hds_to_uarts
include/hw/arm/aspeed.h | 1 +
include/hw/sd/sdhci.h | 5 +
include/hw/timer/aspeed_timer.h | 1 +
hw/arm/aspeed.c | 15 +-
hw/arm/aspeed_ast27x0.c | 17 ++
hw/sd/sdhci.c | 6 +
hw/timer/aspeed_timer.c | 263
++++++++++++++++++--
hw/timer/trace-events | 2 +-
tests/functional/aspeed.py | 2 +-
tests/functional/test_aarch64_aspeed.py | 8 +-
tests/functional/test_arm_aspeed_ast2500.py | 8 +-
tests/functional/test_arm_aspeed_ast2600.py | 8 +-
12 files changed, 303 insertions(+), 33 deletions(-)
--
2.48.1
