Re: [RFC v4 0/5] Add packed virtqueue to shadow virtqueue

Hi, On 1/7/25 1:35 PM, Eugenio Perez Martin wrote: On Fri, Jan 3, 2025 at 2:06 PM Sahil Siddiq wrote: Hi, On 12/20/24 12:28 PM, Eugenio Perez Martin wrote: On Thu, Dec 19, 2024 at 8:37 PM Sahil Siddiq wrote: Hi, On 12/17/24 1:20 PM, Eugenio Perez Martin wrote: On Tue, Dec 17, 2024 at 6

[PATCH v3 3/6] linux-user: netlink: Add IP_PKTINFO cmsg parsing

From: Helge Deller Fixes those warnings: Unsupported host ancillary data: 0/8 Signed-off-by: Helge Deller v2: (based on feedback by Laurent Vivier) - add target_in_pktinfo struct and fix copying target_in_addr fields --- linux-user/syscall.c | 10 ++ linux-user/syscall_defs.h |

[PATCH v3 0/6] linux-user: Add support for various missing netlink sockopt entries

From: Helge Deller This patchset adds various missing sockopt calls, so that qemu linux-user is able to successfully build the debian gupnp package in a chroot. Tested with a 32-bit big-endian hppa linux-user chroot running on a phyiscal x86-64 little-endian host. This fixes debian's bug report

[PATCH v3 6/6] linux-user: netlink: Add missing QEMU_IFLA entries

From: Helge Deller This fixes the following qemu warnings when building debian gupnp package: Unknown host QEMU_IFLA type: 61 Unknown host QEMU_IFLA type: 58 Unknown host QEMU_IFLA type: 59 Unknown host QEMU_IFLA type: 60 Unknown host QEMU_IFLA type: 32820 QEMU_IFLA type 32820 is actually N

[PATCH v3 1/6] linux-user: netlink: Add missing IFA_PROTO to host_to_target_data_addr_rtattr()

From: Helge Deller Fixes this warning: Unknown host IFA type: 11 Signed-off-by: Helge Deller Reviewed-by: Laurent Vivier --- linux-user/fd-trans.c | 1 + 1 file changed, 1 insertion(+) diff --git a/linux-user/fd-trans.c b/linux-user/fd-trans.c index c04a97c73a..a86ed2f4b4 100644 --- a/linux

[PATCH v3 4/6] linux-user: netlink: Add emulation of IP_MULTICAST_IF

From: Helge Deller Add IP_MULTICAST_IF and share the code with IP_ADD_MEMBERSHIP / IP_DROP_MEMBERSHIP. Sharing the code makes sense, because the manpage of ip(7) says: IP_MULTICAST_IF (since Linux 1.2) Set the local device for a multicast socket. The argument for setsockopt(2) is

[PATCH v3 5/6] linux-user: netlink: add netlink neighbour emulation

From: Helge Deller Fixes various warnings in the testsuite while building gupnp: gssdp-net-DEBUG: Failed to send netlink message: Operation not supported gupnp-context-DEBUG: Mismatch between host header and host IP (example.com, expected: 127.0.0.1) gupnp-context-DEBUG: Mismatch between host

[PATCH v3 2/6] linux-user: Use unique error messages for cmsg parsing

From: Helge Deller Avoid using the same error message for two different code paths as it complicates determining the one which actually triggered. Signed-off-by: Helge Deller Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Laurent Vivier --- linux-user/syscall.c | 4 ++-- 1 file changed, 2

[PULL v2 36/50] target/riscv: Invoke pmu init after feature enable

From: Atish Patra The dependant ISA features are enabled at the end of cpu_realize in finalize_features. Thus, PMU init should be invoked after that only. Move the init invocation to riscv_tcg_cpu_finalize_features. Reviewed-by: Alistair Francis Signed-off-by: Atish Patra Message-ID: <20250110

[PULL v2 37/50] target/riscv: Add implied rule for counter delegation extensions

From: Atish Patra The counter delegation/configuration extensions depend on the following extensions. 1. Smcdeleg - To enable counter delegation from M to S 2. S[m|s]csrind - To enable indirect access CSRs Add an implied rule so that these extensions are enabled by default if the sscfg extensio

[PULL v2 02/50] target/riscv: rvv: speed up small unit-stride loads and stores

From: Craig Blackmore Calling `vext_continuous_ldst_tlb` for load/stores up to 6 bytes significantly improves performance. Co-authored-by: Helene CHELIN Co-authored-by: Paolo Savini Co-authored-by: Craig Blackmore Signed-off-by: Helene CHELIN Signed-off-by: Paolo Savini Signed-off-by: Crai

Re: [PATCH] user: Extract common MMAP API to 'user/mmap.h'

On Fri, Jan 17, 2025 at 10:13 AM Philippe Mathieu-Daudé wrote: > Keep common MMAP-related declarations in a single place. > > Note, this disable ThreadSafetyAnalysis on Linux for: > - mmap_fork_start() > - mmap_fork_end(). > > Signed-off-by: Philippe Mathieu-Daudé > --- > bsd-user/qemu.h

[PULL v2 21/50] target/riscv: Add Smrnmi CSRs

From: Tommy Wu The Smrnmi extension adds the 'mnscratch', 'mnepc', 'mncause', 'mnstatus' CSRs. Signed-off-by: Frank Chang Signed-off-by: Tommy Wu Reviewed-by: Alistair Francis Message-ID: <20250106054336.1878291-3-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.

[PULL v2 20/50] target/riscv: Add 'ext_smrnmi' in the RISCVCPUConfig

From: Tommy Wu The boolean variable 'ext_smrnmi' is used to determine whether the Smrnmi extension exists. Signed-off-by: Frank Chang Signed-off-by: Tommy Wu Reviewed-by: Alistair Francis Message-ID: <20250106054336.1878291-2-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- targe

[PULL v2 47/50] target/riscv: Add Smdbltrp ISA extension enable switch

From: Clément Léger Add the switch to enable the Smdbltrp ISA extension and disable it for the max cpu. Indeed, OpenSBI when Smdbltrp is present, M-mode double trap is enabled by default and MSTATUS.MDT needs to be cleared to avoid taking a double trap. OpenSBI does not currently support it so di

[PULL v2 22/50] target/riscv: Handle Smrnmi interrupt and exception

From: Tommy Wu Because the RNMI interrupt trap handler address is implementation defined. We add the 'rnmi-interrupt-vector' and 'rnmi-exception-vector' as the property of the harts. It’s very easy for users to set the address based on their expectation. This patch also adds the functionality to

[PULL v2 48/50] hw/riscv/riscv-iommu.c: Introduce a translation tag for the page table cache

From: Jason Chien This commit introduces a translation tag to avoid invalidating an entry that should not be invalidated when IOMMU executes invalidation commands. E.g. IOTINVAL.VMA with GV=0, AV=0, PSCV=1 invalidates both a mapping of single stage translation and a mapping of nested translation

[PULL v2 41/50] target/riscv: Implement Ssdbltrp sret, mret and mnret behavior

From: Clément Léger When the Ssdbltrp extension is enabled, SSTATUS.SDT field is cleared when executing sret. When executing mret/mnret, SSTATUS.SDT is cleared when returning to U, VS or VU and VSSTATUS.SDT is cleared when returning to VU from HS. Signed-off-by: Clément Léger Reviewed-by: Alist

[PULL v2 40/50] target/riscv: Add Ssdbltrp CSRs handling

From: Clément Léger Add ext_ssdbltrp in RISCVCPUConfig and implement MSTATUS.SDT, {H|M}ENVCFG.DTE and modify the availability of MTVAL2 based on the presence of the Ssdbltrp ISA extension. Signed-off-by: Clément Léger Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-

[PULL v2 29/50] target/riscv: Decouple AIA processing from xiselect and xireg

From: Kaiwen Xue Since xiselect and xireg also will be of use in sxcsrind, AIA should have its own separated interface when those CSRs are accessed. Signed-off-by: Kaiwen Xue Reviewed-by: Alistair Francis Signed-off-by: Atish Patra Message-ID: <20250110-counter_delegation-v5-2-e83d797ae...@ri

[PULL v2 50/50] hw/char/riscv_htif: Convert HTIF_DEBUG() to trace events

From: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Message-ID: <20250116223609.81594-1-phi...@linaro.org> Signed-off-by: Alistair Francis --- hw/char/riscv_htif.c | 15 +++ hw/char/trace-events | 4 2 files changed, 7 insertions(

[PULL v2 45/50] target/riscv: Implement Smdbltrp sret, mret and mnret behavior

From: Clément Léger When the Ssdbltrp extension is enabled, SSTATUS.MDT field is cleared when executing sret if executed in M-mode. When executing mret/mnret, SSTATUS.MDT is cleared. Signed-off-by: Clément Léger Reviewed-by: Alistair Francis Message-ID: <20250110125441.3208676-8-cle...@rivosin

[PULL v2 34/50] target/riscv: Add select value range check for counter delegation

From: Kaiwen Xue This adds checks in ops performed on xireg and xireg2-xireg6 so that the counter delegation function will receive a valid xiselect value with the proper extensions enabled. Co-developed-by: Atish Patra Signed-off-by: Kaiwen Xue Reviewed-by: Alistair Francis Signed-off-by: Ati

[PULL v2 49/50] target/riscv: Support Supm and Sspm as part of Zjpm v1.0

From: Alexey Baturo The Zjpm v1.0 spec states there should be Supm and Sspm extensions that are used in profile specification. Enabling Supm extension enables both Ssnpm and Smnpm, while Sspm enables only Smnpm. Signed-off-by: Alexey Baturo Reviewed-by: Daniel Henrique Barboza Message-ID: <202

[PULL v2 46/50] target/riscv: Implement Smdbltrp behavior

From: Clément Léger When the Smsdbltrp ISA extension is enabled, if a trap happens while MSTATUS.MDT is already set, it will trigger an abort or an NMI is the Smrnmi extension is available. Signed-off-by: Clément Léger Reviewed-by: Alistair Francis Message-ID: <20250110125441.3208676-9-cle...@

[PULL v2 33/50] target/riscv: Add counter delegation definitions

From: Kaiwen Xue This adds definitions for counter delegation, including the new scountinhibit register and the mstateen.CD bit. Signed-off-by: Kaiwen Xue Reviewed-by: Alistair Francis Signed-off-by: Atish Patra Message-ID: <20250110-counter_delegation-v5-6-e83d797ae...@rivosinc.com> Signed-o

[PULL v2 42/50] target/riscv: Implement Ssdbltrp exception handling

From: Clément Léger When the Ssdbltrp ISA extension is enabled, if a trap happens in S-mode while SSTATUS.SDT isn't cleared, generate a double trap exception to M-mode. Signed-off-by: Clément Léger Reviewed-by: Alistair Francis Message-ID: <20250110125441.3208676-5-cle...@rivosinc.com> Signed-

[PULL v2 35/50] target/riscv: Add counter delegation/configuration support

From: Kaiwen Xue The Smcdeleg/Ssccfg adds the support for counter delegation via S*indcsr and Ssccfg. It also adds a new shadow CSR scountinhibit and menvcfg enable bit (CDE) to enable this extension and scountovf virtualization. Signed-off-by: Kaiwen Xue Co-developed-by: Atish Patra Reviewed

[PULL v2 32/50] target/riscv: Add properties for counter delegation ISA extensions

From: Atish Patra This adds the properties for counter delegation ISA extensions (Smcdeleg/Ssccfg). Definitions of new registers and and implementation will come in the next set of patches. Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Signed-off-by: Atish Patra Message-I

[PULL v2 43/50] target/riscv: Add Ssdbltrp ISA extension enable switch

From: Clément Léger Add the switch to enable the Ssdbltrp ISA extension. Signed-off-by: Clément Léger Reviewed-by: Alistair Francis Message-ID: <20250110125441.3208676-6-cle...@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff

[PULL v2 11/50] target/riscv: use RISCVException enum in exception helpers

From: Daniel Henrique Barboza Do a cosmetic change in riscv_raise_exception() to change 'exception' type from uint32_t to RISCVException, making it a bit clear that the arg is directly correlated to the RISCVException enum. As a side effect, change 'excp' type from int to RISCVException in gener

[PULL v2 39/50] target/riscv: Fix henvcfg potentially containing stale bits

From: Clément Léger With the current implementation, if we had the following scenario: - Set bit x in menvcfg - Set bit x in henvcfg - Clear bit x in menvcfg then, the internal variable env->henvcfg would still contain bit x due to both a wrong menvcfg mask used in write_henvcfg() as well as a mi

[PULL v2 19/50] target/riscv: Enable updates for pointer masking variables and thus enable pointer masking extension

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis Message-ID: <20250106102346.1100149-8-baturo.ale...@gmail.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.

[PULL v2 30/50] target/riscv: Enable S*stateen bits for AIA

From: Atish Patra As per the ratified AIA spec v1.0, three stateen bits control AIA CSR access. Bit 60 controls the indirect CSRs Bit 59 controls the most AIA CSR state Bit 58 controls the IMSIC state such as stopei and vstopei Enable the corresponding bits in [m|h]stateen and enable correspond

[PULL v2 25/50] target/riscv: Add Zicfilp support for Smrnmi

From: Frank Chang Zicfilp extension introduces the MNPELP (bit 9) in mnstatus. The MNPELP field holds the previous ELP. When a RNMI trap is delivered, the MNPELP is set to ELP and ELP set to NO_LP_EXPECTED. Upon a mnret, if the mnstatus.MNPP holds the value y, then ELP is set to the value of MNP

[PULL v2 38/50] target/riscv: Add configuration for S[m|s]csrind, Smcdeleg/Ssccfg

From: Atish Patra Add configuration options so that they can be enabled/disabld from qemu commandline. Acked-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza Signed-off-by: Atish Patra Message-ID: <20250110-counter_delegation-v5-11-e83d797ae...@rivosinc.com> Signed-off-by: Alistair F

[PULL v2 13/50] target/riscv: Remove obsolete pointer masking extension code.

From: Alexey Baturo Zjpm extension is finally ratified. And it's much simplier compared to the experimental one. The newer version doesn't allow to specify custom mask or base for pointer masking. Instead it allows only certain options for masking top bits. Signed-off-by: Alexey Baturo Acked-

[PULL v2 06/50] target/riscv: add shtvala

From: Daniel Henrique Barboza shtvala is described in RVA22 as: "htval must be written with the faulting guest physical address in all circumstances permitted by the ISA." This is the case since commit 3067553993, so claim support for shtvala. Signed-off-by: Daniel Henrique Barboza Reviewed-b

[PULL v2 23/50] target/riscv: Add Smrnmi mnret instruction

From: Tommy Wu This patch adds a new instruction 'mnret'. 'mnret' is an M-mode-only instruction that uses the values in `mnepc` and `mnstatus` to return to the program counter, privilege mode, and virtualization mode of the interrupted context. Signed-off-by: Frank Chang Signed-off-by: Tommy Wu

[PULL v2 44/50] target/riscv: Add Smdbltrp CSRs handling

From: Clément Léger Add `ext_smdbltrp`in RISCVCPUConfig and implement MSTATUS.MDT behavior. Also set MDT to 1 at reset according to the specification. Signed-off-by: Clément Léger Reviewed-by: Alistair Francis Message-ID: <20250110125441.3208676-7-cle...@rivosinc.com> Signed-off-by: Alistair F

[PULL v2 31/50] target/riscv: Support generic CSR indirect access

From: Kaiwen Xue This adds the indirect access registers required by sscsrind/smcsrind and the operations on them. Note that xiselect and xireg are used for both AIA and sxcsrind, and the behavior of accessing them depends on whether each extension is enabled and the value stored in xiselect. Co

[PULL v2 18/50] target/riscv: Apply pointer masking for virtualized memory accesses

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20250106102346.1100149-7-baturo.ale...@gmail.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 1 + target/riscv/internals.h | 54 ++

[PULL v2 08/50] target/riscv: add shvsatpa

From: Daniel Henrique Barboza shvsatpa is defined in RVA22 as: "All translation modes supported in satp must be supported in vsatp." This is always true in TCG so let's claim support for it. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20241218114026.1652

[PULL v2 15/50] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20250106102346.1100149-4-baturo.ale...@gmail.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h| 5 +++ target/riscv/cpu_helper.c | 78 ++

qemu-devel@nongnu.org

From: Philippe Mathieu-Daudé virt_machine_init() creates the HARTs vCPUs, then later virt_machine_done() calls create_fdt_sockets(), so the latter has access to the first vCPU via: RISCVVirtState { RISCVHartArrayState { RISCVCPU *harts; ... } soc[VIRT_SOCKETS_MAX]; ...

[PULL v2 28/50] target/riscv: Add properties for Indirect CSR Access extension

From: Kaiwen Xue This adds the properties for sxcsrind. Definitions of new registers and implementations will come with future patches. Signed-off-by: Kaiwen Xue Reviewed-by: Daniel Henrique Barboza Acked-by: Alistair Francis Signed-off-by: Atish Patra Message-ID: <20250110-counter_delegatio

[PULL v2 12/50] target/riscv: add trace in riscv_raise_exception()

From: Daniel Henrique Barboza When using system mode we can get the CPU traps being taken via the 'riscv_trap' trace or the "-d int" qemu log. User mode does not a way of logging/showing exceptions to users. Add a trace in riscv_raise_exception() to allow qemu-riscv(32/64) users to check all exc

[PULL v2 10/50] target/riscv/tcg: add sha

From: Daniel Henrique Barboza 'sha' is the augmented hypervisor extension, defined in RVA22 as a set of the following extensions: - RVH - Ssstateen - Shcounterenw (always present) - Shvstvala (always present) - Shtvala (always present) - Shvstvecd (always present) - Shvsatpa (always present) - S

[PULL v2 00/50] riscv-to-apply queue

The following changes since commit 0e3aff9ec34059512d597eacfcf4d1b5d4570c50: Merge tag 'pull-10.0-gdb-plugins-doc-updates-170125-1' of https://gitlab.com/stsquad/qemu into staging (2025-01-17 10:13:07 -0500) are available in the Git repository at: https://github.com/alistair23/qemu.git tags

[PULL v2 26/50] target/riscv: Have kvm_riscv_get_timebase_frequency() take RISCVCPU cpu

From: Philippe Mathieu-Daudé Keep kvm_riscv_get_timebase_frequency() prototype aligned with the other ones declared in "kvm_riscv.h", have it take a RISCVCPU cpu as argument. Include "target/riscv/cpu-qom.h" which declares the RISCVCPU typedef. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by:

[PULL v2 14/50] target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v1.0

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20250106102346.1100149-3-baturo.ale...@gmail.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 8 target/riscv/cpu_bits.h | 4 tar

[PULL v2 24/50] target/riscv: Add Smrnmi cpu extension

From: Tommy Wu This adds the properties for ISA extension Smrnmi. Also, when Smrnmi is present, the firmware (e.g., OpenSBI) must set mnstatus.NMIE to 1 before enabling any interrupts. Otherwise, all interrupts will be disabled. Since our current OpenSBI does not support Smrnmi yet, let's disabl

[PULL v2 04/50] target/riscv: add shcounterenw

From: Daniel Henrique Barboza shcounterenw is defined in RVA22 as: "For any hpmcounter that is not read-only zero, the corresponding bit in hcounteren must be writable." This is always true in TCG so let's claim support for it. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Fran

[PULL v2 09/50] target/riscv: add shgatpa

From: Daniel Henrique Barboza shgatpa is defined in RVA22 as: "For each supported virtual memory scheme SvNN supported in satp, the corresponding hgatp SvNNx4 mode must be supported. The hgatp mode Bare must also be supported." Claim support for shgatpa since this is always true for TCG. Signe

[PULL v2 16/50] target/riscv: Add pointer masking tb flags

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: LIU Zhiwei Message-ID: <20250106102346.1100149-5-baturo.ale...@gmail.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h| 3 +++ target/riscv/cpu_helper

[PULL v2 05/50] target/riscv: add shvstvala

From: Daniel Henrique Barboza shvstvala is defined in RVA22 as: "vstval must be written in all cases described above for stval." By "cases describe above" the doc refer to the description of sstvala: "stval must be written with the faulting virtual address for load, store, and instruction page

[PULL v2 07/50] target/riscv: add shvstvecd

From: Daniel Henrique Barboza shvstvecd is defined in RVA22 as: "vstvec.MODE must be capable of holding the value 0 (Direct). When vstvec.MODE=Direct, vstvec.BASE must be capable of holding any valid four-byte-aligned address." This is always true for TCG so let's claim support for it. Signed-

[PULL v2 17/50] target/riscv: Update address modify functions to take into account pointer masking

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-ID: <20250106102346.1100149-6-baturo.ale...@gmail.com> Signed-off-by: Alistair Francis --- target/riscv/translate.c | 22 -- target/riscv/vector_helpe

[PULL v2 03/50] riscv/gdbstub: add V bit to priv reg

From: Yanfeng Liu This adds virtualization mode (V bit) as bit(2) of register `priv` per RiscV debug spec v1.0.0-rc4. Checked with gdb-multiarch v12.1. Note that GDB may display `INVALID` tag for `priv` reg when V bit is set, this doesn't affect actual access to the bit though. Signed-off-by: Y

[PULL v2 01/50] target/riscv: rvv: fix typo in vext continuous ldst function names

From: Craig Blackmore Replace `continus` with `continuous`. Signed-off-by: Craig Blackmore Reviewed-by: Daniel Henrique Barboza Reviewed-by: Max Chou Reviewed-by: Richard Henderson Message-ID: <20241218142353.1027938-2-craig.blackm...@embecosm.com> Signed-off-by: Alistair Francis --- targe

Re: [PATCH] vvfat: refresh writing long filename

On Sun, 19 Jan 2025, Michael Tokarev wrote: 18.01.2025 23:54, BALATON Zoltan wrote: +typedef struct lfn_direntry_t { +    uint8_t sequence; +    uint8_t name01[10]; +    uint8_t attributes; +    uint8_t direntry_type; +    uint8_t sfn_checksum; +    uint8_t name0e[12]; +    uint16_t begin; +   

Re: [PULL 00/68] tcg patch queue

Hi Richard, 1. This pull request is not a signed tag. Please push a signed tag. 2. I can't find a key for richard.hender...@linaro.org on keys.openpgp.org. Please check again and send the key fingerprint. Thanks, Stefan signature.asc Description: PGP signature

[PATCH v2] vvfat: refresh writing long filename

In function create_long_filname(), the array name[8 + 3] in struct direntry_t is used as if it were defined as name[32]. This is intentional and works. It's nevertheless an out of bounds array access. To avoid this problem, this patch adds a struct lfn_direntry_t with multiple name arrays. A direct

Re: [PATCH v2] vvfat: refresh writing long filename

19.01.2025 00:26, Michael Tokarev wrote: +static unsigned write_lfn_part(uint8_t *dest, unsigned dsize, + const gunichar2 *lptr, const gunichar2 *lend) +{ +unsigned i = 0; +for (; i < dsize / 2 && lptr + i <= lend; ++i) { /* incl. trailing U+ */ +

Re: [PATCH] vvfat: refresh writing long filename

Am 18.01.25 um 21:55 schrieb Michael Tokarev: > 18.01.2025 23:32, Volker Rümelin wrote: > >> The rules are: >> If the file name length in characters is a multiple of 13 you are done. >> Otherwise the remaining unused LFN direntry name array elements have to >> be filled with one 0x (a 16 bit 0)

Re: [PATCH] vvfat: refresh writing long filename

18.01.2025 23:54, BALATON Zoltan wrote: +typedef struct lfn_direntry_t { +    uint8_t sequence; +    uint8_t name01[10]; +    uint8_t attributes; +    uint8_t direntry_type; +    uint8_t sfn_checksum; +    uint8_t name0e[12]; +    uint16_t begin; +    uint8_t name1c[4]; +} QEMU_PACKED lfn_dirent

Re: [PATCH] vvfat: refresh writing long filename

18.01.2025 23:32, Volker Rümelin wrote: The rules are: If the file name length in characters is a multiple of 13 you are done. Otherwise the remaining unused LFN direntry name array elements have to be filled with one 0x (a 16 bit 0) and the rest with 0x. BTW, are we really okay with a

Re: [PATCH] vvfat: refresh writing long filename

On Sat, 18 Jan 2025, Michael Tokarev wrote: In function create_long_filname(), the array name[8 + 3] in struct direntry_t is used as if it were defined as name[32]. This is intentional and works. It's nevertheless an out of bounds array access. To avoid this problem, this patch adds a struct lfn_

Re: [PATCH] vvfat: refresh writing long filename

18.01.2025 23:32, Volker Rümelin wrote: +static unsigned write_lfn_part(uint8_t *dest, unsigned dsize, + const gunichar2 *lptr, const gunichar2 *lend) +{ +unsigned i; +for(i = 0; i < dsize / 2 && lptr + i < lend; ++i) { +dest[i / 2 + 0] = lptr[i] & 0

Re: [PATCH] vvfat: refresh writing long filename

Am 18.01.25 um 18:35 schrieb Michael Tokarev: > In function create_long_filname(), the array name[8 + 3] in > struct direntry_t is used as if it were defined as name[32]. > This is intentional and works. It's nevertheless an out of > bounds array access. To avoid this problem, this patch adds a > s

Re: [PATCH 0/2] net: Fix announce_self with vhost

17.01.2025 14:17, Laurent Vivier wrote: announce_self that sends a RARP packet after migration or with announce_self QMP/HMP command doesn't work with vhost because of the vnet headers. announce_self is the only user of QEMU_NET_PACKET_FLAG_RAW and this flag is not correctly managed. This serie

Re: [PATCH] gdbstub/user-target: fix gdbserver int format (%d -> %x)

27.12.2024 20:04, Dominik 'Disconnect3d' Czarnota wrote: From: disconnect3d This commit fixes an incorrect format string for formatting integers provided to GDB when debugging a target run in QEMU user mode. The correct format is hexadecimal for both success and errno values, some of which can

[PATCH] vvfat: refresh writing long filename

In function create_long_filname(), the array name[8 + 3] in struct direntry_t is used as if it were defined as name[32]. This is intentional and works. It's nevertheless an out of bounds array access. To avoid this problem, this patch adds a struct lfn_direntry_t with multiple name arrays. A direct

[PATCH v7 4/4] qemu-options.hx: describe hub chardev and aggregation of several backends

This adds a few lines describing `hub` aggregator configuration for aggregation of several backend devices with a single frontend device. Signed-off-by: Roman Penyaev Cc: "Marc-André Lureau" Cc: qemu-devel@nongnu.org --- qemu-options.hx | 48 1 f

[PATCH v7 2/4] chardev/char-hub: implement backend chardev aggregator

This patch implements a new chardev backend `hub` device, which aggregates input from multiple backend devices and forwards it to a single frontend device. Additionally, `hub` device takes the output from the frontend device and sends it back to all the connected backend devices. This allows for se

[PATCH v7 0/4] chardev: implement backend chardev multiplexing

Mux is a character backend (host side) device, which multiplexes multiple frontends with one backend device. The following is a few lines from the QEMU manpage [1]: A multiplexer is a "1:N" device, and here the "1" end is your specified chardev backend, and the "N" end is the various parts o

[PATCH v7 3/4] tests/unit/test-char: add unit tests for hub chardev backend

This commit introduces a new test function `char_hub_test` to validate the functionality and constraints of the "hub" chardev backend in QEMU. The test includes multiple scenarios: 1. Invalid hub creation: - Creating a hub without defining `chardevs.N` (expects an error). - Creating a hub wi

[PATCH v7 1/4] chardev/char-pty: send CHR_EVENT_CLOSED on disconnect

Change makes code symmetric to the code, which handles the "connected" state, i.e. send CHR_EVENT_CLOSED when state changes from "connected" to "disconnected". This behavior is similar to char-socket, for example. Signed-off-by: Roman Penyaev Cc: "Marc-André Lureau" Cc: qemu-devel@nongnu.org --

Re: [PATCH] vvfat: fix out of bounds array write

05.01.2025 16:59, Volker Rümelin wrote: In function create_long_filname(), the array name[8 + 3] in struct direntry_t is used as if it were defined as name[32]. This is intentional and works. It's nevertheless an out of bounds array access. To avoid this problem, this patch adds a struct lfn_dire

Re: [PATCH 0/2] support block encryption/decryption in parallel

Thank you for the additional background and suggestions. I will resend the second version. On 2025/1/17 20:55, Daniel 【外部账号】P. Berrangé wrote: On Thu, Jan 16, 2025 at 01:37:44PM +0100, Kevin Wolf wrote: Am 13.12.2024 um 16:56 hat Daniel P. Berrangé geschrieben: On Thu, Nov 28, 2024 at 06:51:20

Re: [PATCH v7 1/2] memory: Update inline documentation

On Sat, Jan 18, 2025 at 07:15:56PM +0900, Akihiko Odaki wrote: > On 2025/01/18 2:46, Peter Xu wrote: > > On Fri, Jan 17, 2025 at 03:24:34PM +0900, Akihiko Odaki wrote: > > > On 2025/01/16 23:33, Peter Xu wrote: > > > > On Thu, Jan 16, 2025 at 02:37:38PM +0900, Akihiko Odaki wrote: > > > > > On 2025

Re: [PATCH v7 1/2] memory: Update inline documentation

On 2025/01/18 2:46, Peter Xu wrote: On Fri, Jan 17, 2025 at 03:24:34PM +0900, Akihiko Odaki wrote: On 2025/01/16 23:33, Peter Xu wrote: On Thu, Jan 16, 2025 at 02:37:38PM +0900, Akihiko Odaki wrote: On 2025/01/16 1:14, Peter Xu wrote: On Thu, Jan 16, 2025 at 12:52:56AM +0900, Akihiko Odaki wr

Re: [PATCH 2/2] net/dump: Correctly compute Ethernet packet offset

On 2025/01/17 20:17, Laurent Vivier wrote: When a packet is sent with QEMU_NET_PACKET_FLAG_RAW by QEMU it never includes virtio-net header even if qemu_get_vnet_hdr_len() is not 0, and filter-dump is not managing this case. The only user of QEMU_NET_PACKET_FLAG_RAW is announce_self, we can show

Re: [PATCH 1/2] net: Fix announce_self

On 2025/01/17 20:17, Laurent Vivier wrote: b9ad513e1876 ("net: Remove receive_raw()") adds an iovec entry in qemu_deliver_packet_iov() to add the virtio-net header in the data when QEMU_NET_PACKET_FLAG_RAW is set but forgets to increase the number of iovec entries in the array, so receive_iov() w

Re: [PATCH 2/2] docs/cpu-features: Update "PAuth" (Pointer Authentication) details

On Fri, 17 Jan 2025 19:11:06 +, Kashyap Chamarthy wrote: > > PAuth (Pointer Authentication), a security feature in software, is > relevant for both KVM and QEMU. Relect this fact into the docs: > > - For KVM, `pauth` is a binary, "on" vs "off" option. The host CPU > will choose the c

Re: [PATCH v2] checkpatch: Check .m, .build, .hx, .json and .plist

On 2025/01/17 22:12, Daniel P. Berrangé wrote: On Sat, Jan 11, 2025 at 05:07:48PM +0900, Akihiko Odaki wrote: Check more text files: Objective-C, Meson, "hx", JSON, and property list. Objective-C looks sensible at least. For the others though, I'm wondering if any of the current checks perfor

Re: [PATCH v3 0/4] qtest/libqos/pci: pci and msix fixes

On 2025/01/18 2:22, Nicholas Piggin wrote: Since v2: The e1000e|igb series got decoupled from this one and split into its own series. Thank you for working on e1000e/igb. I appreciate fixes for interrupt throttling you added with the new version. Patch 4 was added. For this series, Revi

Re: [PATCH 6/9] net/e1000e|igb: Fix interrupt throttling logic

On 2025/01/18 2:03, Nicholas Piggin wrote: Interrupt throttling is broken in several ways: - Timer expiry sends an interrupt even if there is no cause. - Timer expiry that results in an interrupt does not re-arm the timer so an interrupt can appear immediately after the timer expiry interru

Re: [PATCH 5/9] net/igb: Fix EITR LLI and counter fields

On 2025/01/18 2:03, Nicholas Piggin wrote: IGB EITR registers have counter fields which reflect the current ITR and LLI counter values, as well as a bit to enable LLI moderation, and a bit to write the register without modifying the counter fields. Implement the ITR counter and log an unimp mess

Re: [PATCH 4/9] net/igb: Fix interrupt throttling interval calculation

On 2025/01/18 2:03, Nicholas Piggin wrote: IGB throttling granularity is 1us, and interval field is in bits 2..14 of the EITRx registers. Signed-off-by: Nicholas Piggin Please add Fixes: as described in docs/devel/submitting-a-patch.rst --- hw/net/igb_regs.h | 3 +++ hw/net/igb_core.c |

Re: [PATCH 3/9] qtest/e1000e|igb: assert irqs are clear before triggering an irq

On 2025/01/18 2:02, Nicholas Piggin wrote: Assert there is no existing irq raised that would lead to a false positive interrupt test. e1000e has to disable interrupt throttling for this test, because it can cause delayed superfluous interrupts which trip the assertions. Signed-off-by: Nicholas