在 2024/10/28 上午10:38, Bibo Mao 写道:
Add unistd_64.h on arm64,loongarch and riscv platform, and update
linux headers to Linux v6.12-rc5.
Pass to compile on aarch64, arm, loongarch64, x86_64, i386, riscv64,
riscv32 softmmu and linux-user.
---
v2 ... v3:
1. Add unistd_64.h on arm64 and riscv pla
Hi,
On 2024/10/24 17:06, Jiqian Chen wrote:
> In PVH dom0, when passthrough a device to domU, QEMU code
> xen_pt_realize->xc_physdev_map_pirq wants to use gsi, but in current codes
> the gsi number is got from file /sys/bus/pci/devices//irq, that is
> wrong, because irq is not equal with gsi, they
Hi,
This is a continued discussion following previous month's:
https://lore.kernel.org/qemu-devel/Zvr%2Fbf7KgLN1cjOl@Asurada-Nvidia/
Kernel changes are getting closer to merge, as Jason's planning to
take vIOMMU series and smmuv3_nesting series into the iommufd tree:
https://lore.kernel.org/all/c
> > prefix is just used to print warning. So here we should check prefix
> > for warn_report.
> >
> > +} else if (env->avx10_version) {
> > +if (prefix) {
> > +warn_report("%s: avx10.%d.", prefix, env->avx10_version);
> > +}
> > +have_filtered_features = tru
It passed to compile on riscv machine, and the testbed is riscv qemu VM.
Regards
Bibo Mao
On 2024/10/30 下午12:06, Alistair Francis wrote:
On Wed, Oct 30, 2024 at 11:47 AM gaosong wrote:
在 2024/10/28 下午5:55, maobibo 写道:
On 2024/10/28 下午3:39, gaosong wrote:
在 2024/10/28 上午10:38, Bibo Mao 写道
On Fri, Nov 01, 2024 at 12:52:12AM +0800, Zhao Liu wrote:
> > @@ -7578,7 +7607,27 @@ static bool x86_cpu_filter_features(X86CPU *cpu,
> > bool verbose)
> > }
> > }
> >
> > -return x86_cpu_have_filtered_features(cpu);
> > +have_filtered_features = x86_cpu_have_filtered_featu
On Fri, Nov 01, 2024 at 10:31:12AM +0800, Tao Su wrote:
> Date: Fri, 1 Nov 2024 10:31:12 +0800
> From: Tao Su
> Subject: Re: [PATCH v3 4/8] target/i386: add AVX10 feature and AVX10
> version property
>
> On Fri, Nov 01, 2024 at 10:44:23AM +0800, Zhao Liu wrote:
> > > > prefix is just used to pri
On Fri, Nov 01, 2024 at 10:44:23AM +0800, Zhao Liu wrote:
> > > prefix is just used to print warning. So here we should check prefix
> > > for warn_report.
> > >
> > > +} else if (env->avx10_version) {
> > > +if (prefix) {
> > > +warn_report("%s: avx10.%d.", prefix, env->av
Hi Phil,
> > -static uint32_t cpuid1f_topo_type(enum CPUTopoLevel topo_level)
> > +static uint32_t cpuid1f_topo_type(enum CpuTopologyLevel topo_level)
> > {
> > switch (topo_level) {
> > -case CPU_TOPO_LEVEL_INVALID:
> > +case CPU_TOPOLOGY_LEVEL_INVALID:
>
> Since we use an enum,
FEAT_CMOW introduces support for controlling cache maintenance
instructions executed in EL0/1 and is mandatory from Armv8.8.
On real hardware, the main use for this feature is to prevent processes
from invalidating or flushing cache lines for addresses they only have
read permission, which can imp
>On Thu, 31 Oct 2024, Lei Huang wrote:
>>> On Wed, 30 Oct 2024, Lei Huang wrote:
Use a convergence factor to make the VM's input
global coordinates more closely approach the global
coordinates of host.
Change-Id: I2c3f12f1fe7dfb9306d1fc40c4fd4d299937f4c6
Signed-off-by:
Since the last keyboard device has now been converted over to use
qemu_input_handler_register(), the legacy qemu_add_kbd_event_handler() function
is now unused and can be removed.
Signed-off-by: Mark Cave-Ayland
---
include/ui/console.h | 2 --
ui/input-legacy.c| 37
Convert the next-kbd device from the legacy UI qemu_add_kbd_event_handler()
function to use qemu_input_handler_register().
Signed-off-by: Mark Cave-Ayland
---
hw/m68k/next-kbd.c | 158 +
1 file changed, 103 insertions(+), 55 deletions(-)
diff --git a/
This series converts the next-kbd device to use
qemu_input_handler_register(), and then removes the now-unused legacy
qemu_add_kbd_event_handler() function.
Signed-off-by: Mark Cave-Ayland
v2:
- Rebase onto master
- Add patch 2 to remove the legacy qemu_add_kbd_event_handler()
function
Mark
Hi Avihai,
On 31.10.2024 15:21, Avihai Horon wrote:
Hi Maciej,
On 29/10/2024 16:58, Maciej S. Szmigiero wrote:
External email: Use caution opening links or attachments
From: "Maciej S. Szmigiero"
This way both the start and end points of migrating a particular VFIO
device are known.
Add a
On Thu, Oct 31, 2024 at 03:53:48PM +, Daniel P. Berrangé wrote:
> In cases where object_new() is not being passed a static, const
> string, the caller cannot be sure what type they are instantiating.
> There is a risk that instantiation could fail, if it is an abstract
> type.
>
> Convert such
This gives greater opportunity for reassociation on x86 targets,
since addition can use the LEA instruction.
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/cc_helper_template.h.inc | 24
1 file changed, 12 insertions(+), 12 deletions(-)
On 10/8/2024 5:32 PM, Peter Xu wrote:
On Tue, Oct 08, 2024 at 05:05:01PM -0400, Steven Sistare wrote:
On 10/8/2024 12:26 PM, Peter Xu wrote:
On Tue, Oct 08, 2024 at 11:17:46AM -0400, Steven Sistare wrote:
On 10/7/2024 12:28 PM, Peter Xu wrote:
On Mon, Oct 07, 2024 at 11:49:25AM -0400, Peter X
Dmitry Osipenko writes:
> Add support for DRM native contexts to VirtIO-GPU. DRM context is enabled
> using a new virtio-gpu-gl device option "drm=on".
I feel like using "drm" is confusing in this context because drm exists
for the host and guest. What about "native-context" or even
"context=[op
The ACPI CPU hotplug state `is_enabled` must be migrated along with
other vCPU hotplug states to the destination VM. Update the GED's VM
State Description (VMSD) table subsection to include the CPU Hotplug
VM State Description (VMSD).
Question: How to stop `is_enabled` state being migrated in case
Update DSDT golden master files for x86/pc and x86/q35 platforms to accommodate
changes made in the architecture-agnostic CPU AML. These updates notify the
guest OS of vCPU hot-plug and hot-unplug status using the ACPI `_STA.Enabled`
bit.
The following is a diff of the changes in the .dsl file gen
list changed files in tests/qtest/bios-tables-test-allowed-diff.h
Reported-by: Zhao Liu
Signed-off-by: Salil Mehta
---
tests/qtest/bios-tables-test-allowed-diff.h | 41 +
1 file changed, 41 insertions(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtes
Update the CPUs AML code to reflect the ACPI CPU Hotplug `is_enabled`
state in the `_STA.Enabled` Bit when the ACPI `_STA` method is evaluated
by the Guest Kernel during initialization, as well as when vCPUs are
hot-plugged or hot-unplugged.
Signed-off-by: Salil Mehta
Reviewed-by: Gustavo Romero
Update the `is_enabled` state in `AcpiCpuStatus` when vCPUs are
hot-plugged or hot-unplugged.
Signed-off-by: Salil Mehta
Reviewed-by: Gustavo Romero
---
hw/acpi/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/acpi/cpu.c b/hw/acpi/cpu.c
index 238a0edbc1..8940687f90 100644
--- a/hw
On most architectures, during vCPU hot-plug and hot-unplug actions,
firmware or the VMM/QEMU can convey vCPU status to the OS by
toggling the ACPI method `_STA.Present` Bit. However, certain CPU
architecture specifications prohibit [1] modifications to CPU's
`presence` after the kernel has booted.
Change Log
==
Patch V1 -> V2:
1. Addressed Igor Mammedov's (Redhat) raised issues:
- Removed `ACPICPUstatus::is_present` State and its handling in the
ACPI APUs AML code and now all QOM vCPUs are present.
- Dropped the concept of `acpi_persistent` because now QOM vCPUs
stat
On Thu, Oct 31, 2024 at 03:53:45PM +, Daniel P. Berrangé wrote:
> With code like
>
> Object *obj = object_new(TYPE_BLAH)
>
> the caller can be pretty confident that they will successfully create
> an object instance of TYPE_BLAH. They know exactly what type has been
> requested, so it pas
On 10/31/24 02:24, Daniel P. Berrangé wrote:
On Wed, Oct 30, 2024 at 09:04:26PM -0700, Pierrick Bouvier wrote:
MacOS and Linux are straightforward, but Windows needs a bit more
details.
Signed-off-by: Pierrick Bouvier
---
docs/about/build-platforms.rst | 4 +-
docs/devel/build-system.rst
On 10/31/24 04:01, Michael Tokarev wrote:
29.10.2024 21:09, Pierrick Bouvier wrote:
On 10/23/24 00:39, Pierrick Bouvier wrote:
This file was created by mistake in recent ed7667188 (9p: remove
'proxy' filesystem backend driver).
When cloning the repository using native git for windows, we see t
On Thu, Oct 31, 2024 at 03:53:50PM +, Daniel P. Berrangé wrote:
> Since object_new() will assert(), it should only be used in scenarios
> where the caller knows exactly what type it is asking to be created,
> and can thus be confident in avoiding abstract types.
>
> Enforce this by using a mac
On Thu, Oct 31, 2024 at 03:53:49PM +, Daniel P. Berrangé wrote:
> object_new() has a failure scenario where it will assert() if given
> an abstract type. Callers which are creating objects based on user
> input, or unknown/untrusted type names, must manually check the
> result of object_class_i
On Thu, Oct 31, 2024 at 03:53:47PM +, Daniel P. Berrangé wrote:
> Since object_new_with_class() accepts a non-const parameter for
> the class, callers should be prepared for failures from unexpected
> input. Add an Error parameter for this and make callers check.
> If the caller does not alread
On 10/31/24 03:44, Thomas Huth wrote:
On 31/10/2024 10.28, Daniel P. Berrangé wrote:
On Wed, Oct 30, 2024 at 09:04:21PM -0700, Pierrick Bouvier wrote:
This attribute is not recognized by clang, but the associated option is.
Signed-off-by: Pierrick Bouvier
---
meson.build
Manos,
I apologize for extracting these parts of your code without making my
intention fully clear with you first. My intention was to move the CI
integration forward while you focused on the procedural macros,
because right now the partial CI is limiting other potential
contributors.
In order to
Right now, QEMU is using the "feature" and "bits" fields of ExtSaveArea
to query the accelerator for the support status of extended save areas.
This is a problem for AVX10, which attaches two feature bits (AVX512F
and AVX10) to the same extended save states.
To keep the AVX10 hacks to the minimum,
> 30 окт. 2024 г., в 22:03, Phil Dennis-Jordan написал(а):
>
>
> On Wed 30. Oct 2024 at 15:09, Anastasia Belova wrote:
> default case has no condition. So if it is placed
> higher that other cases, they are unreachable.
>
> Move dafult case down.
>
> The stylistic merits might be debatable,
A straight forward conversion, only the usual changes were required
here (i.e. adjustment for asset downloading, machine selection).
Message-ID: <20241023051754.813412-1-th...@redhat.com>
Signed-off-by: Thomas Huth
---
MAINTAINERS | 2 +-
.../test_aarch64_tcg_p
In cases where object_new() is not being passed a static, const
string, the caller cannot be sure what type they are instantiating.
There is a risk that instantiation could fail, if it is an abstract
type.
Convert such cases over to use object_new_dynamic() such that they
are forced to expect fail
Push an Error object into object_initialize_with_type, so that
reporting of attempts to create an abstract type is handled at
the lowest level.
Signed-off-by: Daniel P. Berrangé
---
qom/object.c | 28 ++--
1 file changed, 18 insertions(+), 10 deletions(-)
diff --git a/qo
Do not assume that the distro-installed meson is compatible with the one
in the virtual environment.
Signed-off-by: Paolo Bonzini
---
.gitlab-ci.d/buildtest-template.yml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/.gitlab-ci.d/buildtest-template.yml
b/.gitlab-ci.d/buildt
From: Richard Henderson
Assert that op is known and that cc_op_live_ is populated.
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/cpu.h| 1 -
target/i386/tcg/translate.c | 21 ++---
target/i386/tcg/decode-new.c.inc | 2 +-
ta
From: Daniel P. Berrangé
We previously added a new job running Fedora with nightly rust
toolchain.
The standard rust toolchain distributed by Fedora is new enough,
however, to let us enable a CI build with that too.
Signed-off-by: Daniel P. Berrangé
Link: https://lore.kernel.org/r/202410151339
If the operands of the arithmetic instruction fit within a half-register,
it's easiest to use a comparison instruction to compute the carry.
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/cc_helper_template.h.inc | 37
1 file changed, 37
From: Richard Henderson
Give the first few enumerators explicit integer constants,
align the BWLQ enumerators.
This will be used to simplify ((op - CC_OP_*B) & 3).
Signed-off-by: Richard Henderson
Link:
https://lore.kernel.org/r/20240701025115.1265117-4-richard.hender...@linaro.org
Signed-off
From: Tao Su
Since the highest supported vector length for a processor implies that
all lesser vector lengths are also supported, add the dependencies of
the supported vector lengths. If all vector lengths aren't supported,
clear AVX10 enable bit as well.
Note that the order of AVX10 related dep
This reverts commit 73ceb12960e686b763415f0880cc5171ccce01cf.
The "r2d" machine can work in big endian mode, see:
https://lore.kernel.org/qemu-devel/d6755445-1060-48a8-82b6-2f392c21f...@landley.net/
So the reasoning for removing sh4eb was wrong.
Message-ID: <20241024082735.42324-2-th...@redha
The following changes since commit 58d49b5895f2e0b5cfe4b2901bf24f3320b74f29:
Merge tag 'net-pull-request' of https://github.com/jasowang/qemu into staging
(2024-10-29 14:00:43 +)
are available in the Git repository at:
https://gitlab.com/thuth/qemu.git tags/pull-request-2024-10-31
for
From: Richard Henderson
Make const. Use the read-only strings directly; do not copy
them into an on-stack buffer with snprintf. Allow for holes
in the cc_op_str array, now present with CC_OP_POPCNT.
Fixes: 460231ad369 ("target/i386: give CC_OP_POPCNT low bits corresponding to
MO_TL")
Signed-o
The call to xgetbv() is passing the ecx value for cpuid function 0xD,
index 0. The xgetbv call thus returns false (OSXSAVE is bit 27, which is
well out of the range of CPUID[0xD,0].ECX) and eax is not modified. While
fixing it, cache the whole computation of supported XCR0 bits since it
will be use
From: Sandipan Das
CPUID leaf 0x8022, i.e. ExtPerfMonAndDbg, advertises new performance
monitoring features for AMD processors. Bit 0 of EAX indicates support
for Performance Monitoring Version 2 (PerfMonV2) features. If found to
be set during PMU initialization, the EBX bits can be used to d
From: Dorjoy Chowdhury
This is in preparation for the next commit where the nitro-enclave
machine type will need to instead use a memfd backend, for the built-in
vhost-user-vsock device to work.
Signed-off-by: Dorjoy Chowdhury
Reviewed-by: Alexander Graf
Link: https://lore.kernel.org/r/2024100
object_initialize() can use modules (it was added there because
virtio-gpu-device is a child device of virtio-gpu-pci; commit
64f7aece8ea, "object_initialize: try module load", 2020-09-15).
object_new() cannot; make things consistent.
qdev_new() is now just a simple wrapper that returns DeviceStat
From: Babu Moger
Rename CPUID_8000_0021_EAX_No_NESTED_DATA_BP to
CPUID_8000_0021_EAX_NO_NESTED_DATA_BP.
No functional change intended.
Signed-off-by: Babu Moger
Link:
https://lore.kernel.org/r/a6749acd125670d3930f4ca31736a91b1d965f2f.1729807947.git.babu.mo...@amd.com
Signed-off-by: Pao
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index d3bbcf7317c..6e89d4faef1 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/t
This removes the 256 byte parity table from the executable.
Suggested-by: Richard Henderson
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
include/qemu/host-utils.h| 9 ++
target/i386/tcg/helper-tcg.h | 6 +++-
target/i386/tcg/cc_helper_templa
Mostly used for TEST+JG and TEST+JLE, but it is easy to cover
also JBE/JA and JL/JGE; shaves about 0.5% TCG ops.
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/target/i386/tc
From: Dorjoy Chowdhury
AWS nitro enclaves[1] is an Amazon EC2[2] feature that allows creating
isolated execution environments, called enclaves, from Amazon EC2
instances which are used for processing highly sensitive data. Enclaves
have no persistent storage and no external networking. The enclav
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 4
1 file changed, 4 insertions(+)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 6e89d4faef1..5d729e68c98 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/
Prepare for filtering non-boolean features such as AVX10 version.
Signed-off-by: Paolo Bonzini
Reviewed-by: Zhao Liu
Signed-off-by: Tao Su
Link: https://lore.kernel.org/r/20241031085233.425388-4-tao1...@linux.intel.com
Signed-off-by: Paolo Bonzini
---
target/i386/cpu.c | 20 +++---
From: Tao Su
When AVX10 enable bit is set, the 0x24 leaf will be present as "AVX10
Converged Vector ISA leaf" containing fields for the version number and
the supported vector bit lengths.
Introduce avx10-version property so that avx10 version can be controlled
by user and cpu model. Per spec, a
From: Tao Su
Update GraniteRapids CPU model to add AVX10 and the missing features(ss,
tsc-adjust, cldemote, movdiri, movdir64b).
Tested-by: Xuelian Guo
Signed-off-by: Tao Su
Link: https://lore.kernel.org/r/20241028024512.156724-7-tao1...@linux.intel.com
Reviewed-by: Zhao Liu
Signed-off-by: Pa
From: Daniel P. Berrangé
Although we're not enabling rust by default yet, we can still add
rust and bindgen to the CI package list.
This demonstrates that we're not accidentally triggering unexpected
build behaviour merely from Rust being present. When we do dev work
to enable rust by default, t
From: Richard Henderson
Replace arithmetic on cc_op with a helper function.
Assert that the op has a size and that it is valid
for the configuration.
Signed-off-by: Richard Henderson
Link:
https://lore.kernel.org/r/20240701025115.1265117-6-richard.hender...@linaro.org
Signed-off-by: Paolo Bonz
From: Dorjoy Chowdhury
Signed-off-by: Dorjoy Chowdhury
Reviewed-by: Alexander Graf
Link: https://lore.kernel.org/r/20241008211727.49088-7-dorjoychy...@gmail.com
Signed-off-by: Paolo Bonzini
---
MAINTAINERS| 1 +
docs/system/i386/nitro-enclave.rst | 78
This makes it easier for the compiler to understand which bits are set,
and it also removes "cltq" instructions to canonicalize the output value
as 32-bit signed.
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/cc_helper_template.h.inc | 46 --
From: Tao Su
AVX10 state enumeration in CPUID leaf D and enabling in XCR0 register
are identical to AVX512 state regardless of the supported vector lengths.
Given that some E-cores will support AVX10 but not support AVX512, add
AVX512 state components to guest when AVX10 is enabled.
Based on a
Put together the common code of object_initialize() and
module_object_class_by_name() into a function that supports
Error **. Rename the existing function type_get_by_name() to
clarify that it will only look at defined types; this is often
okay within object.c to look at the parents, but not outsi
Move the OrangePi tests from tests/avocado/boot_linux_console.py into
a new file dedicated for OrangePi tests in the functional framework
and update the hash sums of the assets to sha256 along the way.
For the buildroot image and the Armbian image, we've got to switch to
a newer version since the o
Just use CC_OP_EFLAGS; it is not that likely that the flags computed by
CC_OP_CLR survive the end of the basic block, in which case there is no
need to spill cc_op_src.
cc_op_src now does need spilling if the XOR is followed by a memory
operation, but this only costs 0.2% extra TCG ops. They will
From: Dorjoy Chowdhury
libcbor dependecy is necessary for adding virtio-nsm and nitro-enclave
machine support in the following commits. libvirt-ci has already been
updated with the dependency upstream and this commit updates libvirt-ci
submodule in QEMU to latest upstream. Also the libcbor depend
From: Tao Su
Introduce features for the supported vector bit lengths.
Signed-off-by: Tao Su
Link: https://lore.kernel.org/r/20241028024512.156724-3-tao1...@linux.intel.com
Link: https://lore.kernel.org/r/20241028024512.156724-4-tao1...@linux.intel.com
Signed-off-by: Paolo Bonzini
Reviewed-by:
Most uses of CC_OP_DYNAMIC are for CMP/JB/JE or similar sequences.
We can optimize many of them to avoid computation of the flags.
This eliminates both TCG ops to set up the new cc_op, and helper
instructions because evaluating just ZF is much cheaper.
Reviewed-by: Richard Henderson
Signed-off-by
A small optimization/code simplification, that also makes it clear that
we won't look for a type in a not-loaded-yet module---the module will
have been loaded by a call to module_object_class_by_name(), if present.
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by:
The function has been unused since commit 4fa28f23906 ("ppc/pnv:
Instantiate cores separately", 2019-12-17). The idea was that
you could use it to build an array of objects via pointer
arithmetic, but no one is doing it anymore.
Cc: Dr. David Alan Gilbert
Reviewed-by: Daniel P. Berrangé
Reviewe
ops is assigned again just below, and the result of the assignment must
be non-NULL.
Originally, the check for NULL was meant to be a check for the existence
of the ops class:
ops = ACCEL_OPS_CLASS(object_class_by_name(ops_name));
...
g_assert(ops != NULL);
(where the ops assignment
Signed-off-by: Paolo Bonzini
Reviewed-by: Zhao Liu
Link: https://lore.kernel.org/r/20241031085233.425388-2-tao1...@linux.intel.com
Signed-off-by: Paolo Bonzini
---
target/i386/cpu.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
i
There is no real reason to make user-creatable classes different
from other backends in this respect. This also allows modularized
character devices to be treated by qom-list-properties just like
builtin ones.
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
qom/object_interface
From: Zhao Liu
X86 architecture has always been a focus of my work. I would like to
help to review more related patches.
Signed-off-by: Zhao Liu
Link: https://lore.kernel.org/r/20241022023628.1743686-1-zhao1@intel.com
Signed-off-by: Paolo Bonzini
---
MAINTAINERS | 1 +
1 file changed, 1 i
Prefer it to gen_ext_tl in the common case where the destination is known.
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/t
From: Xiaoyao Li
The check of cpu->phys_bits to be in range between
[32, TARGET_PHYS_ADDR_SPACE_BITS] in host_cpu_realizefn()
is duplicated with check in x86_cpu_realizefn().
Since the ckeck in x86_cpu_realizefn() is called later and can cover all
the x86 cases. Remove the one in host_cpu_realiz
From: Dorjoy Chowdhury
Nitro Secure Module (NSM)[1] device is used in AWS Nitro Enclaves[2]
for stripped down TPM functionality like cryptographic attestation.
The requests to and responses from NSM device are CBOR[3] encoded.
This commit adds support for NSM device in QEMU. Although related to
From: Babu Moger
Add following bits related Speculative Return Stack Overflow (SRSO).
Guests can make use of these bits if supported.
These bits are reported via CPUID Fn8000_0021_EAX.
===
Bit Feature Description
===
From: Dorjoy Chowdhury
An EIF (Enclave Image Format)[1] file is used to boot an AWS nitro
enclave[2] virtual machine. The EIF file contains the necessary kernel,
cmdline, ramdisk(s) sections to boot.
Some helper functions have been introduced for extracting the necessary
sections from an EIF fil
From: Babu Moger
Newer AMD CPUs support ERAPS (Enhanced Return Address Prediction Security)
feature that enables the auto-clear of RSB entries on a TLB flush, context
switches and VMEXITs. The number of default RSP entries is reflected in
RapSize.
Add the feature bit and feature word to support
LFENCE and SFENCE were introduced with the original SSE instruction set;
marking them incorrectly as cpuid(SSE2) causes failures for CPU models
that lack SSE2, for example pentium3.
Reported-by: Guenter Roeck
Tested-by: Guenter Roeck
Cc: qemu-sta...@nongnu.org
Signed-off-by: Paolo Bonzini
---
From: Pierrick Bouvier
This file was created by mistake in recent ed7667188 (9p: remove
'proxy' filesystem backend driver).
When cloning the repository using native git for windows, we see this:
Error: error: invalid path 'scripts/meson-buildoptions.'
Error: The process 'C:\Program Files\Git\bin
qapi_event_send_device_deleted is always included (together with the
rest of QAPI) in libqemuutil.a if either system-mode emulation or tools
are being built, and in that case the stub causes a duplicate symbol
to appear in libqemuutil.a.
Add the symbol only if events are not being requested.
Cc:
The mipsel architecture is not available in Debian Trixie, and it will
likely be a hard failure as soon as we drop support for the old Rust
toolchain in Debian Bookworm. Prepare by deprecating 32-bit little
endian MIPS in QEMU 9.2.
Signed-off-by: Paolo Bonzini
---
docs/about/build-platforms.rst
The following changes since commit 58d49b5895f2e0b5cfe4b2901bf24f3320b74f29:
Merge tag 'net-pull-request' of https://github.com/jasowang/qemu into staging
(2024-10-29 14:00:43 +)
are available in the Git repository at:
https://gitlab.com/bonzini/qemu.git tags/for-upstream-i386
for you
While right now 64-bit MIPS and 32-bit MIPS share the code in QEMU,
Rust uses different rules for the target. Set $cpu correctly to
either mips or mips64 (--cpu=mips64* is already accepted in the case
statement that canonicalizes cpu/host_arch/linux_arch), and adjust
the checks to account for the
Cirrus-CI stopped providing the possibility to run macOS 15 jobs.
Quoting https://cirrus-ci.org/guide/macOS/ :
"Cirrus CI Cloud only allows ghcr.io/cirruslabs/macos-runner:sonoma image ..."
If you still try to run a Sequoia image, it gets automatically "upgraded"
to Sonoma instead. So the macos-
From: Daniel P. Berrangé
This ensures that if a functional test runs QEMU with a writable
disk pointing to a cached asset, an error will be reported, rather
than silently modifying the cache file.
As an example, tweaking test_sbsaref.py to set snapshot=off,
results in a clear error:
Command:
Commit e779e5c05a ("hw/pci-bridge: Add a Kconfig switch for the
normal PCI bridge") added a config switch for the pci-bridge, so
that the device is not included in the s390x target anymore (since
the pci-bridge is not really useful on s390x).
However, it seems like libvirt is still adding pci-brid
The avocado test defined test functions for both, riscv32 and riscv64.
Since we can run the whole file with multiple targets in the new
framework, we can now consolidate the functions so we have to only
define one function per machine now.
Message-ID: <20240821082748.65853-23-th...@redhat.com>
Rev
From: Mark Cave-Ayland
These were accidentally introduced by my last series.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Thomas Huth
Message-ID: <20241023085852.1061031-2-mark.cave-ayl...@ilande.co.uk>
Signed-off-by: Thomas Huth
---
hw/m68k/next-cube.c | 10 +-
1 file changed, 5 ins
Move the BananaPi tests from tests/avocado/boot_linux_console.py into
a new file dedicated for Banana Pi tests in the functional framework.
Update the hash sums of the assets to sha256 along the way and fix the
broken link for the buildroot image from storage.kernelci.org.
(Note: The test_arm_bpim
I forgot to add the tests to the meson.build file and looks
like I even managed to somehow mix up the hashsums in the
ppc64 test!
Message-ID: <20241023141919.930689-1-th...@redhat.com>
Signed-off-by: Thomas Huth
---
tests/functional/meson.build | 3 +++
tests/functional/test_ppc64_tuxru
From: Mark Cave-Ayland
The parameter is not used.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Thomas Huth
Message-ID: <20241023085852.1061031-5-mark.cave-ayl...@ilande.co.uk>
Signed-off-by: Thomas Huth
---
hw/m68k/next-cube.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff -
From: Daniel P. Berrangé
The zstd command will preserve the input archive permissions on the
output file. So when we decompress the readonly cached image, the
resulting per-test run private disk image will also be readonly.
We need it to be writable, so make it so.
Signed-off-by: Daniel P. Berra
Now that we are aware of binaries that are available for sh4eb,
we should make sure that there are no regressions with this
target and test it regularly in our CI.
Message-ID: <20241024082735.42324-3-th...@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Thomas Huth
---
tests/func
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