From: Tao Su <tao1...@linux.intel.com> AVX10 state enumeration in CPUID leaf D and enabling in XCR0 register are identical to AVX512 state regardless of the supported vector lengths.
Given that some E-cores will support AVX10 but not support AVX512, add AVX512 state components to guest when AVX10 is enabled. Based on a patch by Tao Su <tao1...@linux.intel.com> Signed-off-by: Paolo Bonzini <pbonz...@redhat.com> Reviewed-by: Zhao Liu <zhao1....@intel.com> Tested-by: Xuelian Guo <xuelian....@intel.com> Signed-off-by: Tao Su <tao1...@linux.intel.com> Link: https://lore.kernel.org/r/20241031085233.425388-8-tao1...@linux.intel.com Signed-off-by: Paolo Bonzini <pbonz...@redhat.com> --- target/i386/cpu.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index d056285a034..7666a50bf06 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7156,7 +7156,15 @@ static bool cpuid_has_xsave_feature(CPUX86State *env, const ExtSaveArea *esa) return false; } - return (env->features[esa->feature] & esa->bits); + if (env->features[esa->feature] & esa->bits) { + return true; + } + if (esa->feature == FEAT_7_0_EBX && esa->bits == CPUID_7_0_EBX_AVX512F + && (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10)) { + return true; + } + + return false; } static void x86_cpu_reset_hold(Object *obj, ResetType type) -- 2.47.0
