On 10/17/24 08:47, Markus Armbruster wrote:
Fux build broken by semantic conflict with commit
8f525028bc6 (qapi/crypto: Rename QCryptoAFAlg to QCryptoAFAlgo).
Fixes: 90c3dc60735a (crypto/hash-afalg: Implement new hash API)
Signed-off-by: Markus Armbruster
My bad :/ Obviously, I didn't catch t
Hi Michael:
On Wed, Oct 16, 2024 at 1:58 AM Michael Tokarev wrote:
>
> On 15.09.2024 04:06, Akihiko Odaki wrote:
> > Most of this series are fixes for software RSS and hash reporting, which
> > should have no production user.
> >
> > However there is one exception; patch "virtio-net: Fix size che
Fux build broken by semantic conflict with commit
8f525028bc6 (qapi/crypto: Rename QCryptoAFAlg to QCryptoAFAlgo).
Fixes: 90c3dc60735a (crypto/hash-afalg: Implement new hash API)
Signed-off-by: Markus Armbruster
---
crypto/hash-afalg.c | 10 +-
1 file changed, 5 insertions(+), 5 deletion
From: Hyman Huang
Since CPU throttling only occurs when auto-converge
is on, stop it conditionally.
Signed-off-by: Hyman Huang
---
migration/migration.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/migration/migration.c b/migration/migration.c
index 021faee2f3..37a200
From: Hyman Huang
Move cpu-throttle.c from system to migration since it's
only used for migration; this makes us avoid exporting the
util functions and variables in misc.h but export them in
migration.h when implementing the periodic ramblock dirty
sync feature in the upcoming commits.
Since CPU
From: Hyman Huang
Signed-off-by: Hyman Huang
---
accel/tcg/icount-common.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/accel/tcg/icount-common.c b/accel/tcg/icount-common.c
index 8d3d3a7e9d..30bf8500dc 100644
--- a/accel/tcg/icount-common.c
+++ b/accel/tcg/icount-common.c
@@ -36,7 +36,6
From: Hyman Huang
When VM is configured with huge memory, the current throttle logic
doesn't look like to scale, because migration_trigger_throttle()
is only called for each iteration, so it won't be invoked for a long
time if one iteration can take a long time.
The periodic dirty sync aims to f
From: Hyman Huang
Signed-off-by: Hyman Huang
Reviewed-by: Peter Xu
---
tests/qtest/migration-test.c | 32
1 file changed, 32 insertions(+)
diff --git a/tests/qtest/migration-test.c b/tests/qtest/migration-test.c
index 95e45b5029..e6a2803e71 100644
--- a/tests/
From: Hyman Huang
The global static variable ram_state in fact is referred to by the
"rs" parameter in migration_bitmap_sync_precopy. For ease of calling
by the callees, use the global variable directly in
migration_bitmap_sync_precopy and remove "rs" parameter.
The migration_bitmap_sync_precopy
From: Hyman Huang
v4:
1. split the [PATCH v3 1/6] into smaller patches.
2. refine some comment and commit message
3. fix race issue for the throttle_dirty_sync_timer
4. refine the util function cpu_throttle_dirty_sync_timer
Thanks Peter for the suggestions.
Please review.
Yong
v3:
1. drop the
Daniel P. Berrangé writes:
> From: Alejandro Zeise
>
> Updates the afalg hash driver to support the new accumulative
> hashing changes as part of the patch series.
>
> Implements opening/closing of contexts, updating hash data
> and finalizing the hash digest.
>
> In order to support the update
Philippe Mathieu-Daudé writes:
> On 10/10/24 12:01, Markus Armbruster wrote:
>> The error message doesn't matter much, as the "openpic" device isn't
>> user-creatable. But it's the last use of
>> QERR_PROPERTY_VALUE_OUT_OF_RANGE, which has to go. Change the message
>> just like the previous com
Hi Daniel,
Thanks for the review, I will send a V2 addressing the comments.
Regards,
Sai Pavan
>-Original Message-
>From: Daniel Henrique Barboza
>Sent: Wednesday, October 16, 2024 1:28 AM
>To: Boddu, Sai Pavan ; qemu-devel@nongnu.org;
>qemu-ri...@nongnu.org
>Cc: Paolo Bonzini ; Palmer
On 16/10/2024 22.38, Cédric Le Goater wrote:
This is a simple conversion of the tests with some cleanups and
adjustments to match the new test framework. Replace the zephyr image
MD5 hashes with SHA256 hashes while at it.
The SDK tests depend on a ssh class from avocado.utils which is
difficult
Paolo Bonzini writes:
> offset_of! was stabilized in Rust 1.77.0. Use an alternative implemenation
> that was found on the Rust forums, and whose author agreed to license as
> MIT for use in QEMU.
>
> The alternative allows only one level of field access, but apart
> from this can be used just
On 16/10/2024 18.22, Daniel P. Berrangé wrote:
On Wed, Oct 16, 2024 at 06:07:12PM +0200, Thomas Huth wrote:
The linker on OpenBSD complains:
ld: warning: dirtyrate.c:447 (../src/migration/dirtyrate.c:447)(...):
warning: strcpy() is almost always misused, please use strlcpy()
Is that the o
On 2024/10/17 11:52, Richard Henderson wrote:
On 10/16/24 19:57, LIU Zhiwei wrote:
Hi Richard,
On 2024/10/17 02:38, Richard Henderson wrote:
2595: if (dec->cfg->ext_zcmop) {
2690: if (dec->cfg->ext_zcmp && ((inst >> 12) & 0b01)) {
2716: if (!dec->cfg->ex
On 10/15/24 5:22 AM, Salil Mehta wrote:
Certain CPU architecture specifications [1][2][3] prohibit changes to CPU
presence after the kernel has booted. This limitation exists because many system
initializations rely on the exact CPU count at boot time and do not expect it to
change later. For exa
On 10/15/24 5:22 AM, Salil Mehta wrote:
Certain CPU architecture specifications [1][2][3] prohibit changes to CPU
presence after the kernel has booted. This limitation exists because many system
initializations rely on the exact CPU count at boot time and do not expect it to
change later. For exa
On Sat, Oct 12, 2024 at 4:52 AM Ved Shanbhogue wrote:
>
> Alistair Francis wrote:
> >> When the Ssdbltrp extension is enabled, SSTATUS.SDT field is cleared
> >> when executing sret. When executing mret/mnret, SSTATUS.SDT is cleared
> >> when returning to U, VS or VU and VSSTATUS.SDT is cleared whe
On Mon, Oct 14, 2024 at 5:43 PM Clément Léger wrote:
>
>
>
> On 11/10/2024 05:22, Alistair Francis wrote:
> > On Wed, Sep 25, 2024 at 9:59 PM Clément Léger wrote:
> >>
> >> When the Ssdbltrp ISA extension is enabled, if a trap happens in S-mode
> >> while SSTATUS.SDT isn't cleared, generate a dou
On Wed, Oct 16, 2024 at 8:32 PM Trd thg wrote:
>
> Sorry about the email style, I'm not familiar with it yet
No worries! It takes some getting used to. Mostly just plain text
emails and reply inline :)
Alistair
>
> > It's probably worth including this in the commit message.
> Agree, I'll do it.
Signed-off-by: Huang Shiyuan
Co-authored-by: TANG Tiancheng
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zhiwei
Reviewed-by: Richard Henderson
Signed-off-by: Swung0x48
Hi,
We should remove the tag "Signed-off-by: swung0x48swung0...@outlook.com" since the
author's real name, Huang Shiyuan, is
On Thu, Oct 17, 2024 at 2:35 AM htafr wrote:
>
> (I) Summary
> ===
>
> This patch is the beginning of the support of the Security Protocol and
> Data Model (SPDM). There are some known issues (see II), but it's
> usable and no
On Thu, Oct 17, 2024 at 2:49 AM Peter Xu wrote:
> On Wed, Oct 16, 2024 at 03:56:44PM +0800, yong.hu...@smartx.com wrote:
> > From: Hyman Huang
> >
> > When VM is configured with huge memory, the current throttle logic
> > doesn't look like to scale, because migration_trigger_throttle()
> > is on
On Wed, Oct 16, 2024 at 11:50 PM Peter Xu wrote:
> On Wed, Oct 16, 2024 at 03:56:42PM +0800, yong.hu...@smartx.com wrote:
> > From: Hyman Huang
> >
> > Move cpu-throttle.c from system to migration since it's
> > only used for migration; this makes us avoid exporting the
> > util functions and va
On 10/16/24 19:57, LIU Zhiwei wrote:
Hi Richard,
On 2024/10/17 02:38, Richard Henderson wrote:
2595: if (dec->cfg->ext_zcmop) {
2690: if (dec->cfg->ext_zcmp && ((inst >> 12) & 0b01)) {
2716: if (!dec->cfg->ext_zcmt) {
2726: if (!dec->
Hi Richard,
On 2024/10/17 02:38, Richard Henderson wrote:
2595: if (dec->cfg->ext_zcmop) {
2690: if (dec->cfg->ext_zcmp && ((inst >> 12) & 0b01)) {
2716: if (!dec->cfg->ext_zcmt) {
2726: if (!dec->cfg->ext_zcmp) {
4028:
I want to build qemu with libslirp which built from source code but not
from the system.
Maybe the "subprojects/slirp.wrap" is the right way, is it? But I can't
find more information about how to use it on the internet. Is there some
notes about that? Thanks.
From: Jared Rossi
Allow attempts to boot from multiple IPL devices. If the first device fails to
IPL, select the pre-built IPLB for the next device in the boot order and attempt
to IPL from it. Continue this process until IPL is successful or there are no
devices left to try.
Signed-off-by: Jare
From: Jared Rossi
Remove panic-on-error from Netboot specific functions so that error recovery
may be possible in the future.
Functions that would previously panic now provide a return code.
Signed-off-by: Jared Rossi
---
pc-bios/s390-ccw/s390-ccw.h | 2 +-
pc-bios/s390-ccw/bootmap.c|
From: Jared Rossi
Update docs to show that s390x PC BIOS can support more than one boot device.
Signed-off-by: Jared Rossi
Reviewed-by: Thomas Huth
---
docs/system/bootindex.rst | 7 ---
docs/system/s390x/bootdevices.rst | 9 ++---
2 files changed, 10 insertions(+), 6 deletion
This update contains the required header changes for LoongArch
KVM LBT feature.
Signed-off-by: Bibo Mao
---
include/standard-headers/drm/drm_fourcc.h | 43 +++
include/standard-headers/linux/const.h| 17 +
include/standard-headers/linux/ethtool.h | 226 +
include/s
linux-headers/asm/unistd.h:3:10: fatal error: asm/unistd_64.h: No such file or
directory
#include
Also update linux-headers to v6.12-rc3
---
v1 ... v2:
1. update header files in directory linux-headers to v6.12-rc3
---
Bibo Mao (2):
linux-headers: loongarch: Add kvm_para.h and unistd_64.h
KVM LBT supports on LoongArch depends on the linux-header file
kvm_para.h, also unistd_64.h is required by unistd.h on LoongArch
since 6.11, otherwise there will be compiling error such as:
linux-headers/asm/unistd.h:3:10: fatal error: asm/unistd_64.h: No such file or
directory
#include
Signed
From: Jared Rossi
Build an IPLB for any device with a bootindex (up to a maximum of 8 devices).
The IPLB chain is placed immediately before the BIOS in memory. Because this
is not a fixed address, the location of the next IPLB and number of remaining
boot devices is stored in the QIPL global var
From: Jared Rossi
Add two new qtests to verify that a valid IPL device can successfully boot after
failed IPL attempts from one or more invalid devices.
cdrom-test/as-fallback-device: Defines the primary boot target as a device that
is invalid for IPL and a second boot target that is valid for I
From: Jared Rossi
Add a loadparm property to the VirtioCcwDevice object so that different
loadparms can be defined on a per-device basis for CCW boot devices.
The machine/global loadparm is still supported. If both a global and per-device
loadparm are defined, the per-device value will override
From: Jared Rossi
Remove panic-on-error from ECKD block device IPL specific functions so that
error recovery may be possible in the future.
Functions that would previously panic now provide a return code.
Signed-off-by: Jared Rossi
---
pc-bios/s390-ccw/bootmap.h | 1 +
pc-bios/s390-ccw/boot
From: Jared Rossi
Because virtio-scsi type devices use a non-architected IPLB pbt code they cannot
be set and stored normally. Instead, the IPLB must be rebuilt during re-ipl.
As s390x does not natively support multiple boot devices, the devno field is
used to store the position in the boot orde
From: Jared Rossi
We are going to link the SLOF libc into the s390-ccw.img, and this
libc needs more memory for providing space for malloc() and friends.
Thus bump the memory size that we reserve for the bios to 3 MiB
instead of only 2 MiB. While we're at it, add a proper check that
there is real
From: Jared Rossi
Now that the netboot code has been merged into the main s390-ccw.img,
it also does not make sense to keep the build rules in a separate
file. Thus let's merge netboot.mak into the main Makefile.
Co-authored by: Thomas Huth
Signed-off-by: Jared Rossi
---
pc-bios/s390-ccw/netb
From: Jared Rossi
Remove panic-on-error from DASD IPL specific functions so that error recovery
may be possible in the future.
Functions that would previously panic now provide a return code.
Signed-off-by: Jared Rossi
Reviewed-by: Thomas Huth
---
pc-bios/s390-ccw/dasd-ipl.h | 2 +-
pc-bios
From: Jared Rossi
Remove the information about the separate s390-netboot.img from
the documentation.
Co-authored by: Thomas Huth
Signed-off-by: Jared Rossi
---
docs/system/s390x/bootdevices.rst | 20 +++-
1 file changed, 7 insertions(+), 13 deletions(-)
diff --git a/docs/syst
From: Jared Rossi
Currently, structures defined in both hw/s390x/ipl.h and pc-bios/s390-ccw/iplb.h
must be kept in sync, which is prone to error. Instead, create a new directory
at include/hw/s390x/ipl/ to contain the definitions that must be shared.
Signed-off-by: Jared Rossi
Reviewed-by: Thom
From: Jared Rossi
Since the netboot code has now been merged into the main s390-ccw.img
binary, we don't need the separate s390-netboot.img anymore. Remove
it and the code that was responsible for loading it.
Co-authored by: Thomas Huth
Signed-off-by: Jared Rossi
---
hw/s390x/ipl.h
From: Jared Rossi
Remove panic-on-error from IPL ISO El Torito specific functions so that error
recovery may be possible in the future.
Functions that would previously panic now provide a return code.
Signed-off-by: Jared Rossi
---
pc-bios/s390-ccw/bootmap.h | 15 +++
pc-bios/s390-ccw/s3
From: Jared Rossi
Remove panic-on-error from virtio-scsi IPL specific functions so that error
recovery may be possible in the future.
Functions that would previously panic now provide a return code.
Signed-off-by: Jared Rossi
---
pc-bios/s390-ccw/iplb.h | 2 +
pc-bios/s390-ccw/boot
From: Jared Rossi
We originally built a separate binary for the netboot code since it
was considered as experimental and we could not be sure that the
necessary SLOF module had been checked out. Time passed, the code
proved its usefulness, and the build system nowadays makes sure that
the SLOF mo
From: Jared Rossi
Remove panic-on-error from IPL functions such that a return code is propagated
back to the main IPL calling function (rather than terminating immediately),
which facilitates possible error recovery in the future.
A select few panics remain, which indicate fatal non-devices erro
From: Jared Rossi
We are already using the libc from SLOF for the s390-netboot.img, and
this libc implementation is way more complete and accurate than the
simple implementation that we currently use for the s390-ccw.img binary.
Since we are now always assuming that the SLOF submodule is availabl
From: Jared Rossi
changes v3 -> v4:
- Ensure signed-ness of return values is appropriate
- Add missing newline character in replacements of sclp_print_int()
- Add a missing return in a SCSI error path
- Restore break that was incorrectly removed for Virtio CU devices
- Remove an extra/early retur
On 2024/10/16 下午4:41, gaosong wrote:
在 2024/10/16 下午4:13, maobibo 写道:
ping.
@Song
Could you give some comments since it is LoongArch specific?
Regards
Bibo Mao
On 2024/9/29 下午3:22, Bibo Mao wrote:
KVM LBT supports on LoongArch requires the linux-header kvm_para.h,
also unistd_64.h is req
Am 15. Oktober 2024 09:27:40 UTC schrieb Peter Maydell
:
>On Mon, 14 Oct 2024 at 19:50, Bernhard Beschow wrote:
>>
>>
>>
>> Am 14. Oktober 2024 12:47:52 UTC schrieb Peter Maydell
>> :
>> >> +typedef struct Lan9118PhyState {
>> >> +uint32_t status;
>> >> +uint32_t control;
>> >> +u
Am 15. Oktober 2024 13:26:22 UTC schrieb Sai Pavan Boddu
:
>From: Michal Simek
>
>Add missing optional MDIO lines. Without it U-Boot is not working.
>
>Signed-off-by: Edgar E. Iglesias
>Signed-off-by: Michal Simek
Overall the code seems almost identical to the one in axienet. Doesn't it mak
This is a preparation for the next patch.
Signed-off-by: Bernhard Beschow
---
include/hw/resettable.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/hw/resettable.h b/include/hw/resettable.h
index fd862f1e9f..0f25beaf21 100644
--- a/include/hw/resettable.h
+++ b/include/hw/resettabl
A very similar implementation of the same device exists in imx_fec. Prepare for
a common implementation by extracting a device model into its own files.
Some migration state has been moved into the new device model which breaks
migration compatibility for the following machines:
* smdkc210
* realv
Prefer named constants over magic values for better readability.
Reviewed-by: Peter Maydell
Signed-off-by: Bernhard Beschow
---
include/hw/net/mii.h | 6 +
hw/net/lan9118_phy.c | 59 +++-
2 files changed, 43 insertions(+), 22 deletions(-)
diff --git
The real device advertises this mode and the device model already advertises
100 mbps half duplex and 10 mbps full+half duplex. So advertise this mode to
make the model more realistic.
Reviewed-by: Peter Maydell
Signed-off-by: Bernhard Beschow
---
hw/net/lan9118_phy.c | 4 ++--
1 file changed,
hw/net/imx_fec and hw/net/lan9118 implement the same Ethernet PHY with similar
but not quite the same code. This series consolidates the implementations into
one to fix code duplication. It then continues to make the code more readable by
reusing some existing constants.
Having a dedicated module
imx_fec models the same PHY as lan9118_phy. The code is almost the same with
imx_fec having more logging and tracing. Merge these improvements into
lan9118_phy and reuse in imx_fec to fix the code duplication.
Some migration state how resides in the new device model which breaks migration
compatib
Hi Salil,
On 10/14/24 16:22, Salil Mehta wrote:
Certain CPU architecture specifications [1][2][3] prohibit changes to CPU
presence after the kernel has booted. This limitation exists because many system
initializations rely on the exact CPU count at boot time and do not expect it to
change later
Yichen Wang writes:
> From: Hao Xiang
>
> * DSA device open and close.
> * DSA group contains multiple DSA devices.
> * DSA group configure/start/stop/clean.
>
> Signed-off-by: Hao Xiang
> Signed-off-by: Bryan Zhang
> Signed-off-by: Yichen Wang
> ---
> include/qemu/dsa.h | 103 ++
The RISC-V IOMMU PCI device we're going to add next is a reference
implementation of the riscv-iommu spec [1], which predicts that the
IOMMU can be implemented as a PCIe device.
However, RISC-V International (RVI), the entity that ratified the
riscv-iommu spec, didn't bother assigning a PCI ID for
Add a simple guideline to use the existing RISC-V IOMMU support we just
added.
This doc will be updated once we add the riscv-iommu-sys device.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
---
docs/specs/index.rst | 1 +
docs/specs/riscv-iommu.rst | 90 ++
Add an additional test to further exercise the IOMMU where we attempt to
initialize the command, fault and page-request queues.
These steps are taken from chapter 6.2 of the RISC-V IOMMU spec,
"Guidelines for initialization". It emulates what we expect from the
software/OS when initializing the IO
To test the RISC-V IOMMU emulation we'll use its PCI representation.
Create a new 'riscv-iommu-pci' libqos device that will be present with
CONFIG_RISCV_IOMMU. This config is only available for RISC-V, so this
device will only be consumed by the RISC-V libqos machine.
Start with basic tests: a PC
From: Tomasz Jeznach
DBG support adds three additional registers: tr_req_iova, tr_req_ctl and
tr_response.
The DBG cap is always enabled. No on/off toggle is provided for it.
Signed-off-by: Tomasz Jeznach
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Frank Chang
Reviewed-by: Alistair F
From: Tomasz Jeznach
The RISC-V IOMMU spec predicts that the IOMMU can use translation caches
to hold entries from the DDT. This includes implementation for all cache
commands that are marked as 'not implemented'.
There are some artifacts included in the cache that predicts s-stage and
g-stage e
From: Tomasz Jeznach
The RISC-V IOMMU specification is now ratified as-per the RISC-V
international process. The latest frozen specifcation can be found at:
https://github.com/riscv-non-isa/riscv-iommu/releases/download/v1.0/riscv-iommu.pdf
Add the foundation of the device emulation for RISC-V
From: Tomasz Jeznach
Generate device tree entry for riscv-iommu PCI device, along with
mapping all PCI device identifiers to the single IOMMU device instance.
Signed-off-by: Tomasz Jeznach
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Frank Chang
Reviewed-by: Alistair Francis
---
hw/r
From: Tomasz Jeznach
The RISC-V IOMMU can be modelled as a PCIe device following the
guidelines of the RISC-V IOMMU spec, chapter 7.1, "Integrating an IOMMU
as a PCIe device".
Signed-off-by: Tomasz Jeznach
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Frank Chang
Reviewed-by: Alistair F
From: Tomasz Jeznach
This header will be used by the RISC-V IOMMU emulation to be added
in the next patch. Due to its size it's being sent in separate for
an easier review.
One thing to notice is that this header can be replaced by the future
Linux RISC-V IOMMU driver header, which would become
Hi,
In this new version we fixed address alignment issues in some command
queue commands, pointed out by Jason in v9.
No other changes made. Series based on alistair/riscv-to-apply.next.
All patches reviewed.
Changes from v9:
- patch 3:
- fixed cmd.dword1 alignment in riscv_iommu_process_cq_t
From: Tomasz Jeznach
Add PCIe Address Translation Services (ATS) capabilities to the IOMMU.
This will add support for ATS translation requests in Fault/Event
queues, Page-request queue and IOATC invalidations.
Signed-off-by: Tomasz Jeznach
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Fr
From: Tomasz Jeznach
Extend memory transaction attributes with process identifier to allow
per-request address translation logic to use requester_id / process_id
to identify memory mapping (e.g. enabling IOMMU w/ PASID translations).
Signed-off-by: Tomasz Jeznach
Reviewed-by: Frank Chang
Revie
This is a simple conversion of the tests with some cleanups and
adjustments to match the new test framework. Replace the zephyr image
MD5 hashes with SHA256 hashes while at it.
The SDK tests depend on a ssh class from avocado.utils which is
difficult to replace. To be addressed separately.
Signed
From: Richard Henderson
In the fallback when STDBRX is not available, avoid clobbering
TCG_REG_TMP1, which might be h.base, which is still in use.
Use TCG_REG_TMP2 instead.
Cc: qemu-sta...@nongnu.org
Fixes: 01a112e2e9 ("tcg/ppc: Reorg tcg_out_tlb_read")
Signed-off-by: Richard Henderson
Tested-B
From: Marc-André Lureau
A filter function that wants to drop a message should return NULL, in
which case it must also unref the message itself.
Fixes: fa88b85de ("ui/dbus: filter out pending messages when scanout")
Signed-off-by: Marc-André Lureau
Reviewed-by: Akihiko Odaki
Message-ID: <20241
From: Peter Maydell
In commit b88cfee90268cad we defined masks for the IBRD and FBRD
integer and fractional baud rate divider registers, to prevent the
guest from writing invalid values which could cause division-by-zero.
Unfortunately we got the mask values the wrong way around: the FBRD
registe
From: Richard Henderson
Comparing a string of 4 bytes only works in little-endian.
Adjust bulk bswap to only apply to the note payload.
Perform swapping of the note header manually; the magic
is defined so that it does not need a runtime swap.
Fixes: 83f990eb5adb ("linux-user/elfload: Parse NT_
From: Marc-André Lureau
Fixes: 280c1e1cd ("audio/hda: create millisecond timers that handle IO")
Signed-off-by: Marc-André Lureau
Reviewed-by: Akihiko Odaki
Message-ID: <20241008125028.1177932-2-marcandre.lur...@redhat.com>
(cherry picked from commit f27206ceedbe2efae37c8d143c5eb2db05251508)
S
From: Alexandra Diupina
The result of 1 << regbit with regbit==31 has a 1 in the 32nd bit.
When cast to uint64_t (for further bitwise OR), the 32 most
significant bits will be filled with 1s. However, the documentation
states that the upper 32 bits of ICH_AP[0/1]R_EL2 are reserved.
Add an explic
From: Marc-André Lureau
When SET_STREAM_FORMAT is called, we should clear the existing setup.
Factor out common function to close a stream.
Direct leak of 144 byte(s) in 3 object(s) allocated from:
#0 0x7f91d38f7350 in calloc (/lib64/libasan.so.8+0xf7350) (BuildId:
a4ad7eb954b390cf00f07fa1
From: Richard Henderson
In tcg_out_qemu_ldst_i128, we need a non-zero index register,
which we then use as a base register in several address modes.
Since we always have TCG_REG_TMP2 available, use that.
Cc: qemu-sta...@nongnu.org
Fixes: 526cd4ec01f ("tcg/ppc: Support 128-bit load/store")
Resolv
From: Paolo Bonzini
Moving -mcx16 out of CPU_CFLAGS caused the detection of ATOMIC128 to
fail, because flags have to be specified by hand in cc.compiles and
cc.links invocations (why oh why??).
Ensure that these tests enable all the instruction set extensions that
will be used to build the emula
From: Marc-André Lureau
DisplaySurface may be free before the pixman image is freed, since the
image is refcounted and used by different objects, including pending
dbus messages.
Furthermore, setting the destroy function in
create_displaysurface_from() isn't appropriate, as it may not be used,
a
From: Marc-André Lureau
Filtering pending messages when a new scanout is given shouldn't discard
pending cursor changes, for example.
Since filtering happens in a different thread, use atomic set/get.
Fixes: fa88b85dea ("ui/dbus: filter out pending messages when scanout")
Signed-off-by: Marc-A
The following patches are queued for QEMU stable v9.1.1:
https://gitlab.com/qemu-project/qemu/-/commits/staging-9.1
Patch freeze is 2024-10-16 (frozen), and the release is planned for 2024-10-18:
https://wiki.qemu.org/Planning/9.1
Please respond here or CC qemu-sta...@nongnu.org on any addi
From: Alexandra Diupina
The result of 1 << regbit with regbit==31 has a 1 in the 32nd bit.
When cast to uint64_t (for further bitwise OR), the 32 most
significant bits will be filled with 1s. However, the documentation
states that the upper 32 bits of ICH_AP[0/1]R_EL2 are reserved.
Add an explic
From: Paolo Bonzini
Create a separate variable for compiler flags that enable
specific instruction set extensions, so that they can be used with
cc.compiles/cc.links.
Note that -mfpmath=sse is a code generation option but it does not
enable new instructions, therefore I did not make it part of
q
From: Philippe Mathieu-Daudé
load_flt_binary() calls load_flat_file() -> page_set_flags().
page_set_flags() must be called with the mmap_lock held,
otherwise it aborts:
$ qemu-arm -L stm32/lib/ stm32/bin/busybox
qemu-arm: ../accel/tcg/user-exec.c:505: page_set_flags: Assertion
`have_mmap_l
From: Richard Henderson
Returning a raw areg does not preserve the value if the areg
is subsequently modified. Fixes, e.g. "jsr (sp)", where the
return address is pushed before the branch.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2483
Signed-off-by: Richard Henderson
Message-Id:
From: Alexandra Diupina
The result of 1 << regbit with regbit==31 has a 1 in the 32nd bit.
When cast to uint64_t (for further bitwise OR), the 32 most
significant bits will be filled with 1s. However, the documentation
states that the upper 32 bits of ICC_AP[0/1]R_EL2 are reserved.
Add an explic
From: Pierrick Bouvier
s/mbmi1/mbmi/
When configuring with -Dx86_version >= 3, meson step works, but
compilation fails because option -mbmi1 is unknown.
Signed-off-by: Pierrick Bouvier
Reviewed-by: Alex Bennée
Tested-by: Alex Bennée
Link:
https://lore.kernel.org/r/20241004223715.1275428-1-p
On Tue, Oct 15, 2024 at 03:02:37PM -0700, Yichen Wang wrote:
> On Fri, Oct 11, 2024 at 9:32 AM Peter Xu wrote:
> >
> > On Wed, Oct 09, 2024 at 04:45:58PM -0700, Yichen Wang wrote:
> >
> > The doc update is still missing under docs/, we may need that for a final
> > merge.
> >
>
> I will work with
From: TANG Tiancheng
Add support for probing RISC-V vector extension availability in
the backend. This information will be used when deciding whether
to use vector instructions in code generation.
Cache lg2(vlenb) for the backend. The storing of lg2(vlenb) means
we can convert all of the divisio
The first immediate field is unsigned, whereas operand_vimm
extracts a signed value. There is no need to mask the result
with 'u'; just print the immediate with 'i'.
Fixes: 07f4964d178 ("disas/riscv.c: rvv: Add disas support for vector
instructions")
Signed-off-by: Richard Henderson
---
disas/
From: TANG Tiancheng
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zhiwei
Reviewed-by: Richard Henderson
Message-ID: <20241007025700.47259-9-zhiwei_...@linux.alibaba.com>
Signed-off-by: Richard Henderson
---
tcg/riscv/tcg-target.h | 4 ++--
tcg/riscv/tcg-target.c.inc | 41 +
From: TANG Tiancheng
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zhiwei
Message-ID: <20241007025700.47259-12-zhiwei_...@linux.alibaba.com>
Signed-off-by: Richard Henderson
---
tcg/riscv/tcg-target.h | 6 +++---
tcg/riscv/tcg-target.c.inc | 36
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